stm32f072_usb_mouse_keyboard: create project
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23
stm32f072_usb_mouse_keyboard/Core/Inc/usb_config.h
Normal file
23
stm32f072_usb_mouse_keyboard/Core/Inc/usb_config.h
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@ -0,0 +1,23 @@
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#ifndef CHERRYUSB_CONFIG_H
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#define CHERRYUSB_CONFIG_H
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#define CONFIG_USB_PRINTF(...) printf(__VA_ARGS__)
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#define CONFIG_USB_DBG_LEVEL USB_DBG_INFO
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#define CONFIG_USB_PRINTF_COLOR_ENABLE
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#define CONFIG_USB_ALIGN_SIZE 4
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#define USB_NOCACHE_RAM_SECTION
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/* ================ USB Device Port Configuration ================*/
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#define CONFIG_USBDEV_MAX_BUS 1
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#define CONFIG_USBDEV_EP_NUM 8
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/* ================= USB Device Stack Configuration ================ */
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#define CONFIG_USBDEV_REQUEST_BUFFER_LEN 256
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/* ---------------- FSDEV Configuration ---------------- */
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#define CONFIG_USBDEV_FSDEV_PMA_ACCESS 1
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#endif
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@ -21,7 +21,7 @@
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/* Private includes ----------------------------------------------------------*/
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/* USER CODE BEGIN Includes */
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#include "usbd_core.h"
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#include <stdio.h>
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#include "usb_hid.h"
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#include "bsp_key.h"
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#include "hid_keyboard_mouse.h"
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@ -62,20 +62,7 @@ static void MX_TIM6_Init(void);
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/* Private user code ---------------------------------------------------------*/
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/* USER CODE BEGIN 0 */
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void usb_dc_low_level_init(void)
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{
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__HAL_RCC_USB_CLK_ENABLE();
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HAL_NVIC_SetPriority(USB_IRQn, 0, 0);
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HAL_NVIC_EnableIRQ(USB_IRQn);
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}
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int fputc(int c, FILE *f)
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{
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uint8_t ch = c;
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HAL_UART_Transmit(&huart1, &ch, 1, 10);
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return c;
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}
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/* USER CODE END 0 */
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/**
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@ -116,8 +103,7 @@ int main(void)
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/* Infinite loop */
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/* USER CODE BEGIN WHILE */
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while (1)
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{
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while (1) {
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bsp_key_number_e key;
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bsp_key_event_type_e event;
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bsp_key_get_event(&key, &event);
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@ -148,7 +134,6 @@ int main(void)
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} else {
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__WFI();
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}
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/* USER CODE END WHILE */
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/* USER CODE BEGIN 3 */
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@ -319,7 +304,12 @@ static void MX_GPIO_Init(void)
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}
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/* USER CODE BEGIN 4 */
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int fputc(int c, FILE *f)
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{
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uint8_t ch = c;
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HAL_UART_Transmit(&huart1, &ch, 1, 10);
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return c;
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}
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/* USER CODE END 4 */
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/**
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@ -1,3 +1,4 @@
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/* USER CODE BEGIN Header */
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/**
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******************************************************************************
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@ -98,6 +99,7 @@ void HAL_TIM_Base_MspInit(TIM_HandleTypeDef* htim_base)
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/* USER CODE BEGIN TIM6_MspInit 1 */
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/* USER CODE END TIM6_MspInit 1 */
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}
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}
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@ -159,6 +161,7 @@ void HAL_UART_MspInit(UART_HandleTypeDef* huart)
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/* USER CODE BEGIN USART1_MspInit 1 */
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/* USER CODE END USART1_MspInit 1 */
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}
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}
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@ -193,5 +196,18 @@ void HAL_UART_MspDeInit(UART_HandleTypeDef* huart)
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}
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/* USER CODE BEGIN 1 */
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void usb_dc_low_level_init(void)
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{
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__HAL_RCC_USB_CLK_ENABLE();
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HAL_NVIC_SetPriority(USB_IRQn, 0, 0);
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HAL_NVIC_EnableIRQ(USB_IRQn);
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}
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void usb_dc_low_level_deinit(void)
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{
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__HAL_RCC_USB_CLK_DISABLE();
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HAL_NVIC_DisableIRQ(USB_IRQn);
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}
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/* USER CODE END 1 */
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@ -22,6 +22,7 @@
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#include "stm32f0xx_it.h"
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/* Private includes ----------------------------------------------------------*/
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/* USER CODE BEGIN Includes */
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/* USER CODE END Includes */
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/* Private typedef -----------------------------------------------------------*/
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@ -7,7 +7,7 @@
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2023 STMicroelectronics.
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* Copyright (c) 2021 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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@ -37,16 +37,12 @@ extern "C" {
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#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
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#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
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#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
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#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1)
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#if defined(STM32H7) || defined(STM32MP1)
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#define CRYP_DATATYPE_32B CRYP_NO_SWAP
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#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
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#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
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#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
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#if defined(STM32U5)
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#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF
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#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
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#endif /* STM32U5 */
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#endif /* STM32U5 || STM32H7 || STM32MP1 */
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#endif /* STM32H7 || STM32MP1 */
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/**
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* @}
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*/
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@ -279,7 +275,7 @@ extern "C" {
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#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
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#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
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#if defined(STM32G4) || defined(STM32L5) || defined(STM32H7) || defined (STM32U5)
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#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
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#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
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#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
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#endif
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@ -552,6 +548,16 @@ extern "C" {
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#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE
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#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE
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#endif /* STM32U5 */
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#if defined(STM32U0)
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#define OB_USER_nRST_STOP OB_USER_NRST_STOP
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#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
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#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
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#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL
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#define OB_USER_nBOOT0 OB_USER_NBOOT0
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#define OB_USER_nBOOT1 OB_USER_NBOOT1
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#define OB_nBOOT0_RESET OB_NBOOT0_RESET
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#define OB_nBOOT0_SET OB_NBOOT0_SET
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#endif /* STM32U0 */
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/**
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* @}
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@ -1243,10 +1249,10 @@ extern "C" {
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#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
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#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
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#if defined(STM32H5)
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#if defined(STM32H5) || defined(STM32H7RS)
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#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
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#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM
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#endif /* STM32H5 */
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#endif /* STM32H5 || STM32H7RS */
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#if defined(STM32WBA)
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#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
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@ -1258,10 +1264,10 @@ extern "C" {
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#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL
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#endif /* STM32WBA */
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#if defined(STM32H5) || defined(STM32WBA)
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#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
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#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE
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#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
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#endif /* STM32H5 || STM32WBA */
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#endif /* STM32H5 || STM32WBA || STM32H7RS */
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#if defined(STM32F7)
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#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
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@ -1599,6 +1605,8 @@ extern "C" {
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#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
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#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
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#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */
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/**
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* @}
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*/
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@ -1991,12 +1999,12 @@ extern "C" {
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/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
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* @{
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*/
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#if defined(STM32H5) || defined(STM32WBA)
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#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
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#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey
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#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock
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#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock
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#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets
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#endif /* STM32H5 || STM32WBA */
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#endif /* STM32H5 || STM32WBA || STM32H7RS */
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/**
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* @}
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@ -2311,8 +2319,8 @@ extern "C" {
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#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
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((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
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__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
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# endif
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# if defined(STM32F302xE) || defined(STM32F302xC)
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#endif
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#if defined(STM32F302xE) || defined(STM32F302xC)
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#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
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((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
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((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
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@ -2345,8 +2353,8 @@ extern "C" {
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((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
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((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
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__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
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# endif
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# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
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#endif
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#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
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#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
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((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
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((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
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@ -2403,8 +2411,8 @@ extern "C" {
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((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
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((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
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__HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
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# endif
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# if defined(STM32F373xC) ||defined(STM32F378xx)
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#endif
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#if defined(STM32F373xC) ||defined(STM32F378xx)
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#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
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__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
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#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
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@ -2421,7 +2429,7 @@ extern "C" {
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__HAL_COMP_COMP2_EXTI_GET_FLAG())
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#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
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__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
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# endif
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#endif
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#else
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#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
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__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
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@ -2723,6 +2731,12 @@ extern "C" {
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#define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET
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#define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET
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#define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET
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#if defined(STM32C0)
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#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET
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#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET
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#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET
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#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET
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#endif /* STM32C0 */
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#define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE
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#define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE
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#define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET
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@ -3646,8 +3660,12 @@ extern "C" {
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#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
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#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
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#if defined(STM32U0)
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#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK
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#endif
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#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
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defined(STM32WL) || defined(STM32C0)
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defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0)
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#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
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#else
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#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
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@ -3749,8 +3767,10 @@ extern "C" {
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#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
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#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
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#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
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#if !defined(STM32U0)
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#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
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#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
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#endif
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#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
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#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
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@ -3896,7 +3916,8 @@ extern "C" {
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*/
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#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
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defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
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defined (STM32WBA) || defined (STM32H5) || defined (STM32C0)
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defined (STM32WBA) || defined (STM32H5) || \
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defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0)
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#else
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#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
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#endif
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@ -3931,6 +3952,13 @@ extern "C" {
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__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
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#endif /* STM32F1 */
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#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \
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defined (STM32H7) || \
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defined (STM32L0) || defined (STM32L1) || \
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defined (STM32WB)
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#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG
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#endif
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#define IS_ALARM IS_RTC_ALARM
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#define IS_ALARM_MASK IS_RTC_ALARM_MASK
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#define IS_TAMPER IS_RTC_TAMPER
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@ -4212,6 +4240,9 @@ extern "C" {
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#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
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#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
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#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1
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#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2
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/**
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* @}
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*/
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@ -236,8 +236,8 @@ typedef enum
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*/
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#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
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#define IS_GPIO_PIN(__PIN__) (((((uint32_t)__PIN__) & GPIO_PIN_MASK) != 0x00U) &&\
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((((uint32_t)__PIN__) & ~GPIO_PIN_MASK) == 0x00U))
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#define IS_GPIO_PIN(__PIN__) (((((uint32_t)(__PIN__)) & GPIO_PIN_MASK) != 0x00U) &&\
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((((uint32_t)(__PIN__)) & ~GPIO_PIN_MASK) == 0x00U))
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|
||||
#define IS_GPIO_MODE(__MODE__) (((__MODE__) == GPIO_MODE_INPUT) ||\
|
||||
((__MODE__) == GPIO_MODE_OUTPUT_PP) ||\
|
||||
@ -118,8 +118,6 @@ typedef enum
|
||||
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
|
||||
process is ongoing */
|
||||
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
|
||||
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
|
||||
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
|
||||
|
||||
} HAL_I2C_StateTypeDef;
|
||||
|
||||
@ -403,7 +403,6 @@ typedef enum
|
||||
, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
|
||||
, HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
|
||||
, HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
|
||||
|
||||
, HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
|
||||
, HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
|
||||
, HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
|
||||
@ -1656,8 +1655,9 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
|
||||
#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
|
||||
((__CHANNEL__) == TIM_CHANNEL_2))
|
||||
|
||||
#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) \
|
||||
((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U))
|
||||
#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \
|
||||
(((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \
|
||||
((__PERIOD__) > 0U))
|
||||
|
||||
#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) || \
|
||||
@ -1710,7 +1710,6 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
|
||||
|
||||
#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
|
||||
|
||||
|
||||
#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
|
||||
((__STATE__) == TIM_BREAK_DISABLE))
|
||||
|
||||
@ -2048,7 +2047,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S
|
||||
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
|
||||
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
|
||||
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength);
|
||||
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
|
||||
uint32_t BurstLength);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
|
||||
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
|
||||
uint32_t BurstLength, uint32_t DataLength);
|
||||
@ -145,7 +145,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
|
||||
|
||||
HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart);
|
||||
HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart);
|
||||
|
||||
|
||||
/**
|
||||
@ -559,10 +559,10 @@ typedef struct
|
||||
/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
|
||||
* @{
|
||||
*/
|
||||
#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
|
||||
#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */
|
||||
#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
|
||||
#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
|
||||
#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
|
||||
#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
|
||||
#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
|
||||
/**
|
||||
* @}
|
||||
@ -822,11 +822,11 @@ typedef struct
|
||||
#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=6 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=5 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=6 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=8 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
|
||||
@ -1473,6 +1473,17 @@ __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
|
||||
CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
|
||||
* @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload
|
||||
* @param TIMx Timer instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
|
||||
{
|
||||
return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
|
||||
* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
|
||||
@ -213,7 +213,7 @@ __STATIC_INLINE uint32_t LL_GetFlashSize(void)
|
||||
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
|
||||
* @note When a RTOS is used, it is recommended to avoid changing the SysTick
|
||||
* configuration by calling this function, for a delay use rather osDelay RTOS service.
|
||||
* @param Ticks Number of ticks
|
||||
* @param Ticks Frequency of Ticks (Hz)
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
|
||||
@ -56,7 +56,7 @@
|
||||
*/
|
||||
#define __STM32F0xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
|
||||
#define __STM32F0xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */
|
||||
#define __STM32F0xx_HAL_VERSION_SUB2 (0x07U) /*!< [15:8] sub2 version */
|
||||
#define __STM32F0xx_HAL_VERSION_SUB2 (0x08U) /*!< [15:8] sub2 version */
|
||||
#define __STM32F0xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
|
||||
#define __STM32F0xx_HAL_VERSION ((__STM32F0xx_HAL_VERSION_MAIN << 24U)\
|
||||
|(__STM32F0xx_HAL_VERSION_SUB1 << 16U)\
|
||||
@ -137,6 +137,9 @@ void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t Sub
|
||||
/* Check the parameters */
|
||||
assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
|
||||
NVIC_SetPriority(IRQn,PreemptPriority);
|
||||
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(SubPriority);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -64,7 +64,7 @@
|
||||
(++) Provide exiting handle as parameter.
|
||||
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
|
||||
|
||||
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
|
||||
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_ClearConfigLine().
|
||||
(++) Provide exiting handle as parameter.
|
||||
|
||||
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
|
||||
@ -75,7 +75,7 @@
|
||||
|
||||
(#) Get interrupt pending bit using HAL_EXTI_GetPending().
|
||||
|
||||
(#) Clear interrupt pending bit using HAL_EXTI_GetPending().
|
||||
(#) Clear interrupt pending bit using HAL_EXTI_ClearPending().
|
||||
|
||||
(#) Generate software interrupt using HAL_EXTI_GenerateSWI().
|
||||
|
||||
@ -456,7 +456,7 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
* until the next reset.
|
||||
* @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F0 family
|
||||
* @param GPIO_Pin specifies the port bits to be locked.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
* This parameter can be any combination of GPIO_PIN_x where x can be (0..15).
|
||||
* @retval None
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
|
||||
@ -90,7 +90,7 @@
|
||||
add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
|
||||
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
|
||||
add their own code by customization of function pointer HAL_I2C_ErrorCallback()
|
||||
(+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
|
||||
(+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
|
||||
(+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
|
||||
add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
|
||||
(+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
|
||||
@ -156,7 +156,7 @@
|
||||
HAL_I2C_Master_Seq_Receive_IT() or using HAL_I2C_Master_Seq_Receive_DMA()
|
||||
(+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and users can
|
||||
add their own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
|
||||
(++) Abort a master IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
|
||||
(++) Abort a master or memory IT or DMA I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
|
||||
(+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
|
||||
add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
|
||||
(++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT()
|
||||
@ -214,7 +214,7 @@
|
||||
add their own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
|
||||
(+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and users can
|
||||
add their own code by customization of function pointer HAL_I2C_ErrorCallback()
|
||||
(+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
|
||||
(+) Abort a master or memory I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
|
||||
(+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and users can
|
||||
add their own code by customization of function pointer HAL_I2C_AbortCpltCallback()
|
||||
(+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
|
||||
@ -608,7 +608,12 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
|
||||
/* Configure I2Cx: Addressing Master mode */
|
||||
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
|
||||
{
|
||||
hi2c->Instance->CR2 = (I2C_CR2_ADD10);
|
||||
SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear the I2C ADD10 bit */
|
||||
CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
|
||||
}
|
||||
/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
|
||||
hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
|
||||
@ -1115,6 +1120,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
|
||||
uint16_t Size, uint32_t Timeout)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
uint32_t xfermode;
|
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_READY)
|
||||
{
|
||||
@ -1138,18 +1144,39 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
|
||||
hi2c->XferCount = Size;
|
||||
hi2c->XferISR = NULL;
|
||||
|
||||
/* Send Slave Address */
|
||||
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
|
||||
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
||||
{
|
||||
hi2c->XferSize = MAX_NBYTE_SIZE;
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
|
||||
I2C_GENERATE_START_WRITE);
|
||||
xfermode = I2C_RELOAD_MODE;
|
||||
}
|
||||
else
|
||||
{
|
||||
hi2c->XferSize = hi2c->XferCount;
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
|
||||
xfermode = I2C_AUTOEND_MODE;
|
||||
}
|
||||
|
||||
if (hi2c->XferSize > 0U)
|
||||
{
|
||||
/* Preload TX register */
|
||||
/* Write data to TXDR */
|
||||
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
|
||||
|
||||
/* Increment Buffer pointer */
|
||||
hi2c->pBuffPtr++;
|
||||
|
||||
hi2c->XferCount--;
|
||||
hi2c->XferSize--;
|
||||
|
||||
/* Send Slave Address */
|
||||
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode,
|
||||
I2C_GENERATE_START_WRITE);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Send Slave Address */
|
||||
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode,
|
||||
I2C_GENERATE_START_WRITE);
|
||||
}
|
||||
|
||||
@ -1261,7 +1288,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAd
|
||||
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
|
||||
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
||||
{
|
||||
hi2c->XferSize = MAX_NBYTE_SIZE;
|
||||
hi2c->XferSize = 1U;
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
|
||||
I2C_GENERATE_START_READ);
|
||||
}
|
||||
@ -1352,6 +1379,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
|
||||
uint32_t Timeout)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
uint16_t tmpXferCount;
|
||||
HAL_StatusTypeDef error;
|
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_READY)
|
||||
{
|
||||
@ -1378,14 +1407,6 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
|
||||
/* Enable Address Acknowledge */
|
||||
hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
|
||||
|
||||
/* Wait until ADDR flag is set */
|
||||
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
|
||||
{
|
||||
/* Disable Address Acknowledge */
|
||||
hi2c->Instance->CR2 |= I2C_CR2_NACK;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Preload TX data if no stretch enable */
|
||||
if (hi2c->Init.NoStretchMode == I2C_NOSTRETCH_ENABLE)
|
||||
{
|
||||
@ -1399,6 +1420,18 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
|
||||
hi2c->XferCount--;
|
||||
}
|
||||
|
||||
/* Wait until ADDR flag is set */
|
||||
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
|
||||
{
|
||||
/* Disable Address Acknowledge */
|
||||
hi2c->Instance->CR2 |= I2C_CR2_NACK;
|
||||
|
||||
/* Flush TX register */
|
||||
I2C_Flush_TXDR(hi2c);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Clear ADDR flag */
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
|
||||
|
||||
@ -1410,6 +1443,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
|
||||
{
|
||||
/* Disable Address Acknowledge */
|
||||
hi2c->Instance->CR2 |= I2C_CR2_NACK;
|
||||
|
||||
/* Flush TX register */
|
||||
I2C_Flush_TXDR(hi2c);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
@ -1422,6 +1459,10 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
|
||||
{
|
||||
/* Disable Address Acknowledge */
|
||||
hi2c->Instance->CR2 |= I2C_CR2_NACK;
|
||||
|
||||
/* Flush TX register */
|
||||
I2C_Flush_TXDR(hi2c);
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
@ -1445,13 +1486,29 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
|
||||
}
|
||||
|
||||
/* Wait until AF flag is set */
|
||||
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
|
||||
error = I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart);
|
||||
|
||||
if (error != HAL_OK)
|
||||
{
|
||||
/* Check that I2C transfer finished */
|
||||
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
|
||||
/* Mean XferCount == 0 */
|
||||
|
||||
tmpXferCount = hi2c->XferCount;
|
||||
if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U))
|
||||
{
|
||||
/* Reset ErrorCode to NONE */
|
||||
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable Address Acknowledge */
|
||||
hi2c->Instance->CR2 |= I2C_CR2_NACK;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Flush TX register */
|
||||
I2C_Flush_TXDR(hi2c);
|
||||
|
||||
@ -1469,6 +1526,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
|
||||
|
||||
/* Clear STOP flag */
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
||||
}
|
||||
|
||||
/* Wait until BUSY flag is reset */
|
||||
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
|
||||
@ -1672,7 +1730,26 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
|
||||
|
||||
/* Send Slave Address */
|
||||
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
|
||||
if (hi2c->XferSize > 0U)
|
||||
{
|
||||
/* Preload TX register */
|
||||
/* Write data to TXDR */
|
||||
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
|
||||
|
||||
/* Increment Buffer pointer */
|
||||
hi2c->pBuffPtr++;
|
||||
|
||||
hi2c->XferCount--;
|
||||
hi2c->XferSize--;
|
||||
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode,
|
||||
I2C_GENERATE_START_WRITE);
|
||||
}
|
||||
else
|
||||
{
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode,
|
||||
I2C_GENERATE_START_WRITE);
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
@ -1732,7 +1809,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t De
|
||||
|
||||
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
||||
{
|
||||
hi2c->XferSize = MAX_NBYTE_SIZE;
|
||||
hi2c->XferSize = 1U;
|
||||
xfermode = I2C_RELOAD_MODE;
|
||||
}
|
||||
else
|
||||
@ -1895,6 +1972,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
|
||||
{
|
||||
uint32_t xfermode;
|
||||
HAL_StatusTypeDef dmaxferstatus;
|
||||
uint32_t sizetoxfer = 0U;
|
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_READY)
|
||||
{
|
||||
@ -1927,6 +2005,20 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
|
||||
xfermode = I2C_AUTOEND_MODE;
|
||||
}
|
||||
|
||||
if (hi2c->XferSize > 0U)
|
||||
{
|
||||
/* Preload TX register */
|
||||
/* Write data to TXDR */
|
||||
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
|
||||
|
||||
/* Increment Buffer pointer */
|
||||
hi2c->pBuffPtr++;
|
||||
|
||||
sizetoxfer = hi2c->XferSize;
|
||||
hi2c->XferCount--;
|
||||
hi2c->XferSize--;
|
||||
}
|
||||
|
||||
if (hi2c->XferSize > 0U)
|
||||
{
|
||||
if (hi2c->hdmatx != NULL)
|
||||
@ -1942,8 +2034,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
|
||||
hi2c->hdmatx->XferAbortCallback = NULL;
|
||||
|
||||
/* Enable the DMA channel */
|
||||
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
|
||||
hi2c->XferSize);
|
||||
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr,
|
||||
(uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
|
||||
}
|
||||
else
|
||||
{
|
||||
@ -1964,7 +2056,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
|
||||
{
|
||||
/* Send Slave Address */
|
||||
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U),
|
||||
xfermode, I2C_GENERATE_START_WRITE);
|
||||
|
||||
/* Update XferCount value */
|
||||
hi2c->XferCount -= hi2c->XferSize;
|
||||
@ -2003,7 +2096,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
|
||||
|
||||
/* Send Slave Address */
|
||||
/* Set NBYTES to write and generate START condition */
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, I2C_AUTOEND_MODE,
|
||||
I2C_GENERATE_START_WRITE);
|
||||
|
||||
/* Process Unlocked */
|
||||
@ -2065,7 +2158,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
|
||||
|
||||
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
||||
{
|
||||
hi2c->XferSize = MAX_NBYTE_SIZE;
|
||||
hi2c->XferSize = 1U;
|
||||
xfermode = I2C_RELOAD_MODE;
|
||||
}
|
||||
else
|
||||
@ -2159,11 +2252,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
|
||||
/* Note : The I2C interrupts must be enabled after unlocking current process
|
||||
to avoid the risk of I2C interrupt handle execution before current
|
||||
process unlock */
|
||||
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
|
||||
/* Enable ERR, TC, STOP, NACK, RXI interrupt */
|
||||
/* possible to enable all of these */
|
||||
/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
|
||||
I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
|
||||
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
|
||||
I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
@ -2612,7 +2705,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
|
||||
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
|
||||
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
||||
{
|
||||
hi2c->XferSize = MAX_NBYTE_SIZE;
|
||||
hi2c->XferSize = 1U;
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
|
||||
I2C_GENERATE_START_READ);
|
||||
}
|
||||
@ -2650,7 +2743,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
|
||||
|
||||
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
||||
{
|
||||
hi2c->XferSize = MAX_NBYTE_SIZE;
|
||||
hi2c->XferSize = 1U;
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t) hi2c->XferSize, I2C_RELOAD_MODE,
|
||||
I2C_NO_STARTSTOP);
|
||||
}
|
||||
@ -2728,6 +2821,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
|
||||
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
||||
|
||||
/* Prepare transfer parameters */
|
||||
hi2c->XferSize = 0U;
|
||||
hi2c->pBuffPtr = pData;
|
||||
hi2c->XferCount = Size;
|
||||
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
|
||||
@ -2849,11 +2943,11 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
|
||||
to avoid the risk of I2C interrupt handle execution before current
|
||||
process unlock */
|
||||
|
||||
/* Enable ERR, TC, STOP, NACK, RXI interrupt */
|
||||
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
|
||||
/* possible to enable all of these */
|
||||
/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
|
||||
I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
|
||||
I2C_Enable_IRQ(hi2c, (I2C_XFER_TX_IT | I2C_XFER_RX_IT));
|
||||
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
@ -3259,22 +3353,6 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
||||
}
|
||||
|
||||
/* Check if the maximum allowed number of trials has been reached */
|
||||
if (I2C_Trials == Trials)
|
||||
{
|
||||
/* Generate Stop */
|
||||
hi2c->Instance->CR2 |= I2C_CR2_STOP;
|
||||
|
||||
/* Wait until STOPF flag is reset */
|
||||
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Clear STOP Flag */
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
||||
}
|
||||
|
||||
/* Increment Trials */
|
||||
I2C_Trials++;
|
||||
} while (I2C_Trials < Trials);
|
||||
@ -3313,6 +3391,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16
|
||||
{
|
||||
uint32_t xfermode;
|
||||
uint32_t xferrequest = I2C_GENERATE_START_WRITE;
|
||||
uint32_t sizetoxfer = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
|
||||
@ -3344,6 +3423,21 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16
|
||||
xfermode = hi2c->XferOptions;
|
||||
}
|
||||
|
||||
if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \
|
||||
(XferOptions == I2C_FIRST_AND_LAST_FRAME)))
|
||||
{
|
||||
/* Preload TX register */
|
||||
/* Write data to TXDR */
|
||||
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
|
||||
|
||||
/* Increment Buffer pointer */
|
||||
hi2c->pBuffPtr++;
|
||||
|
||||
sizetoxfer = hi2c->XferSize;
|
||||
hi2c->XferCount--;
|
||||
hi2c->XferSize--;
|
||||
}
|
||||
|
||||
/* If transfer direction not change and there is no request to start another frame,
|
||||
do not generate Restart Condition */
|
||||
/* Mean Previous state is same as current state */
|
||||
@ -3365,7 +3459,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16
|
||||
}
|
||||
|
||||
/* Send Slave Address and set NBYTES to write */
|
||||
if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
|
||||
{
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
|
||||
}
|
||||
else
|
||||
{
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
@ -3405,6 +3506,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
|
||||
uint32_t xfermode;
|
||||
uint32_t xferrequest = I2C_GENERATE_START_WRITE;
|
||||
HAL_StatusTypeDef dmaxferstatus;
|
||||
uint32_t sizetoxfer = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
|
||||
@ -3436,6 +3538,21 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
|
||||
xfermode = hi2c->XferOptions;
|
||||
}
|
||||
|
||||
if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \
|
||||
(XferOptions == I2C_FIRST_AND_LAST_FRAME)))
|
||||
{
|
||||
/* Preload TX register */
|
||||
/* Write data to TXDR */
|
||||
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
|
||||
|
||||
/* Increment Buffer pointer */
|
||||
hi2c->pBuffPtr++;
|
||||
|
||||
sizetoxfer = hi2c->XferSize;
|
||||
hi2c->XferCount--;
|
||||
hi2c->XferSize--;
|
||||
}
|
||||
|
||||
/* If transfer direction not change and there is no request to start another frame,
|
||||
do not generate Restart Condition */
|
||||
/* Mean Previous state is same as current state */
|
||||
@ -3471,8 +3588,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
|
||||
hi2c->hdmatx->XferAbortCallback = NULL;
|
||||
|
||||
/* Enable the DMA channel */
|
||||
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
|
||||
hi2c->XferSize);
|
||||
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr,
|
||||
(uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
|
||||
}
|
||||
else
|
||||
{
|
||||
@ -3492,7 +3609,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
|
||||
if (dmaxferstatus == HAL_OK)
|
||||
{
|
||||
/* Send Slave Address and set NBYTES to write */
|
||||
if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
|
||||
{
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
|
||||
}
|
||||
else
|
||||
{
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
|
||||
}
|
||||
|
||||
/* Update XferCount value */
|
||||
hi2c->XferCount -= hi2c->XferSize;
|
||||
@ -3531,8 +3655,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
|
||||
|
||||
/* Send Slave Address */
|
||||
/* Set NBYTES to write and generate START condition */
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
|
||||
I2C_GENERATE_START_WRITE);
|
||||
if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
|
||||
{
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
|
||||
}
|
||||
else
|
||||
{
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
@ -3795,11 +3925,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16
|
||||
/* Note : The I2C interrupts must be enabled after unlocking current process
|
||||
to avoid the risk of I2C interrupt handle execution before current
|
||||
process unlock */
|
||||
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
|
||||
/* Enable ERR, TC, STOP, NACK, RXI interrupt */
|
||||
/* possible to enable all of these */
|
||||
/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
|
||||
I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
|
||||
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
|
||||
I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
@ -4434,7 +4564,7 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Abort a master I2C IT or DMA process communication with Interrupt.
|
||||
* @brief Abort a master or memory I2C IT or DMA process communication with Interrupt.
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
* the configuration information for the specified I2C.
|
||||
* @param DevAddress Target device address: The device 7 bits address value
|
||||
@ -4443,7 +4573,9 @@ HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
|
||||
{
|
||||
if (hi2c->Mode == HAL_I2C_MODE_MASTER)
|
||||
HAL_I2C_ModeTypeDef tmp_mode = hi2c->Mode;
|
||||
|
||||
if ((tmp_mode == HAL_I2C_MODE_MASTER) || (tmp_mode == HAL_I2C_MODE_MEM))
|
||||
{
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hi2c);
|
||||
@ -4842,8 +4974,12 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin
|
||||
hi2c->XferSize--;
|
||||
hi2c->XferCount--;
|
||||
}
|
||||
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
|
||||
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
|
||||
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) == RESET) && \
|
||||
((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
|
||||
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)))
|
||||
{
|
||||
/* Write data to TXDR */
|
||||
if (hi2c->XferCount != 0U)
|
||||
{
|
||||
/* Write data to TXDR */
|
||||
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
|
||||
@ -4854,6 +4990,7 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin
|
||||
hi2c->XferSize--;
|
||||
hi2c->XferCount--;
|
||||
}
|
||||
}
|
||||
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
|
||||
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
|
||||
{
|
||||
@ -4862,8 +4999,16 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin
|
||||
devaddress = (uint16_t)(hi2c->Instance->CR2 & I2C_CR2_SADD);
|
||||
|
||||
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
||||
{
|
||||
/* Errata workaround 170323 */
|
||||
if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
|
||||
{
|
||||
hi2c->XferSize = 1U;
|
||||
}
|
||||
else
|
||||
{
|
||||
hi2c->XferSize = MAX_NBYTE_SIZE;
|
||||
}
|
||||
I2C_TransferConfig(hi2c, devaddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
|
||||
}
|
||||
else
|
||||
@ -5017,8 +5162,16 @@ static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32
|
||||
if ((hi2c->XferCount != 0U) && (hi2c->XferSize == 0U))
|
||||
{
|
||||
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
||||
{
|
||||
/* Errata workaround 170323 */
|
||||
if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
|
||||
{
|
||||
hi2c->XferSize = 1U;
|
||||
}
|
||||
else
|
||||
{
|
||||
hi2c->XferSize = MAX_NBYTE_SIZE;
|
||||
}
|
||||
I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
|
||||
I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
|
||||
}
|
||||
@ -5039,14 +5192,28 @@ static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32
|
||||
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
|
||||
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
|
||||
{
|
||||
/* Disable Interrupt related to address step */
|
||||
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
|
||||
|
||||
/* Enable ERR, TC, STOP, NACK and RXI interrupts */
|
||||
I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
|
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
|
||||
{
|
||||
direction = I2C_GENERATE_START_READ;
|
||||
}
|
||||
|
||||
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
||||
{
|
||||
/* Errata workaround 170323 */
|
||||
if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
|
||||
{
|
||||
hi2c->XferSize = 1U;
|
||||
}
|
||||
else
|
||||
{
|
||||
hi2c->XferSize = MAX_NBYTE_SIZE;
|
||||
}
|
||||
|
||||
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
|
||||
I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
|
||||
@ -5103,8 +5270,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
|
||||
/* Call I2C Slave complete process */
|
||||
I2C_ITSlaveCplt(hi2c, tmpITFlags);
|
||||
}
|
||||
|
||||
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
|
||||
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
|
||||
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
|
||||
{
|
||||
/* Check that I2C transfer finished */
|
||||
@ -5267,8 +5433,16 @@ static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, ui
|
||||
|
||||
/* Prepare the new XferSize to transfer */
|
||||
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
||||
{
|
||||
/* Errata workaround 170323 */
|
||||
if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
|
||||
{
|
||||
hi2c->XferSize = 1U;
|
||||
}
|
||||
else
|
||||
{
|
||||
hi2c->XferSize = MAX_NBYTE_SIZE;
|
||||
}
|
||||
xfermode = I2C_RELOAD_MODE;
|
||||
}
|
||||
else
|
||||
@ -5405,6 +5579,9 @@ static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint3
|
||||
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
|
||||
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
|
||||
{
|
||||
/* Disable Interrupt related to address step */
|
||||
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
|
||||
|
||||
/* Enable only Error interrupt */
|
||||
I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
|
||||
|
||||
@ -5412,8 +5589,16 @@ static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint3
|
||||
{
|
||||
/* Prepare the new XferSize to transfer */
|
||||
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
||||
{
|
||||
/* Errata workaround 170323 */
|
||||
if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
|
||||
{
|
||||
hi2c->XferSize = 1U;
|
||||
}
|
||||
else
|
||||
{
|
||||
hi2c->XferSize = MAX_NBYTE_SIZE;
|
||||
}
|
||||
I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
|
||||
I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
|
||||
}
|
||||
@ -5447,14 +5632,28 @@ static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint3
|
||||
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
|
||||
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
|
||||
{
|
||||
/* Disable Interrupt related to address step */
|
||||
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
|
||||
|
||||
/* Enable only Error and NACK interrupt for data transfer */
|
||||
I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
|
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
|
||||
{
|
||||
direction = I2C_GENERATE_START_READ;
|
||||
}
|
||||
|
||||
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
||||
{
|
||||
/* Errata workaround 170323 */
|
||||
if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
|
||||
{
|
||||
hi2c->XferSize = 1U;
|
||||
}
|
||||
else
|
||||
{
|
||||
hi2c->XferSize = MAX_NBYTE_SIZE;
|
||||
}
|
||||
|
||||
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
|
||||
I2C_TransferConfig(hi2c, (uint16_t)hi2c->Devaddress, (uint8_t)hi2c->XferSize,
|
||||
@ -5524,8 +5723,7 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
|
||||
/* Call I2C Slave complete process */
|
||||
I2C_ITSlaveCplt(hi2c, ITFlags);
|
||||
}
|
||||
|
||||
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
|
||||
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
|
||||
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
|
||||
{
|
||||
/* Check that I2C transfer finished */
|
||||
@ -6125,6 +6323,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
|
||||
{
|
||||
uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
|
||||
uint32_t tmpITFlags = ITFlags;
|
||||
uint32_t tmpoptions = hi2c->XferOptions;
|
||||
HAL_I2C_StateTypeDef tmpstate = hi2c->State;
|
||||
|
||||
/* Clear STOP Flag */
|
||||
@ -6141,6 +6340,11 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
|
||||
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
|
||||
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
|
||||
}
|
||||
else if (tmpstate == HAL_I2C_STATE_LISTEN)
|
||||
{
|
||||
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
|
||||
hi2c->PreviousState = I2C_STATE_NONE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do nothing */
|
||||
@ -6207,6 +6411,57 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
|
||||
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
|
||||
}
|
||||
|
||||
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
|
||||
(I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET))
|
||||
{
|
||||
/* Check that I2C transfer finished */
|
||||
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
|
||||
/* Mean XferCount == 0*/
|
||||
/* So clear Flag NACKF only */
|
||||
if (hi2c->XferCount == 0U)
|
||||
{
|
||||
if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
|
||||
/* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
|
||||
Warning[Pa134]: left and right operands are identical */
|
||||
{
|
||||
/* Call I2C Listen complete process */
|
||||
I2C_ITListenCplt(hi2c, tmpITFlags);
|
||||
}
|
||||
else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
|
||||
{
|
||||
/* Clear NACK Flag */
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
||||
|
||||
/* Flush TX register */
|
||||
I2C_Flush_TXDR(hi2c);
|
||||
|
||||
/* Last Byte is Transmitted */
|
||||
/* Call I2C Slave Sequential complete process */
|
||||
I2C_ITSlaveSeqCplt(hi2c);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear NACK Flag */
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
|
||||
/* Clear NACK Flag */
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
||||
|
||||
/* Set ErrorCode corresponding to a Non-Acknowledge */
|
||||
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
|
||||
|
||||
if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
|
||||
{
|
||||
/* Call the corresponding callback to inform upper layer of End of Transfer */
|
||||
I2C_ITError(hi2c, hi2c->ErrorCode);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
hi2c->Mode = HAL_I2C_MODE_NONE;
|
||||
hi2c->XferISR = NULL;
|
||||
|
||||
@ -6623,9 +6878,17 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
|
||||
|
||||
/* Set the XferSize to transfer */
|
||||
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
||||
{
|
||||
/* Errata workaround 170323 */
|
||||
if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
|
||||
{
|
||||
hi2c->XferSize = 1U;
|
||||
}
|
||||
else
|
||||
{
|
||||
hi2c->XferSize = MAX_NBYTE_SIZE;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
hi2c->XferSize = hi2c->XferCount;
|
||||
@ -6735,6 +6998,12 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin
|
||||
{
|
||||
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
|
||||
{
|
||||
/* Check if an error is detected */
|
||||
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check for the Timeout */
|
||||
if (Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
@ -6846,16 +7115,18 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
|
||||
static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
|
||||
uint32_t Tickstart)
|
||||
{
|
||||
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) && (status == HAL_OK))
|
||||
{
|
||||
/* Check if an error is detected */
|
||||
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check if a STOPF is detected */
|
||||
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
|
||||
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && (status == HAL_OK))
|
||||
{
|
||||
/* Check if an RXNE is pending */
|
||||
/* Store Last receive data if any */
|
||||
@ -6863,19 +7134,14 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
|
||||
{
|
||||
/* Return HAL_OK */
|
||||
/* The Reading of data from RXDR will be done in caller function */
|
||||
return HAL_OK;
|
||||
status = HAL_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
|
||||
/* Check a no-acknowledge have been detected */
|
||||
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
|
||||
{
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
||||
hi2c->ErrorCode = HAL_I2C_ERROR_AF;
|
||||
}
|
||||
else
|
||||
{
|
||||
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
||||
}
|
||||
|
||||
/* Clear STOP Flag */
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
||||
@ -6889,12 +7155,16 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_ERROR;
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
||||
}
|
||||
}
|
||||
|
||||
/* Check for the Timeout */
|
||||
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
||||
if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK))
|
||||
{
|
||||
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET))
|
||||
{
|
||||
@ -6904,11 +7174,11 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_ERROR;
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
return HAL_OK;
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -7103,13 +7373,13 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
|
||||
|
||||
if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
|
||||
{
|
||||
/* Enable ERR, TC, STOP, NACK and RXI interrupts */
|
||||
/* Enable ERR, TC, STOP, NACK and TXI interrupts */
|
||||
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
|
||||
}
|
||||
|
||||
if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
|
||||
{
|
||||
/* Enable ERR, TC, STOP, NACK and TXI interrupts */
|
||||
/* Enable ERR, TC, STOP, NACK and RXI interrupts */
|
||||
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
|
||||
}
|
||||
|
||||
@ -7136,13 +7406,13 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
|
||||
|
||||
if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
|
||||
{
|
||||
/* Enable ERR, TC, STOP, NACK and RXI interrupts */
|
||||
/* Enable ERR, TC, STOP, NACK and TXI interrupts */
|
||||
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
|
||||
}
|
||||
|
||||
if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
|
||||
{
|
||||
/* Enable ERR, TC, STOP, NACK and TXI interrupts */
|
||||
/* Enable ERR, TC, STOP, NACK and RXI interrupts */
|
||||
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
|
||||
}
|
||||
|
||||
@ -7158,7 +7428,7 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
|
||||
tmpisr |= (I2C_IT_STOPI | I2C_IT_TCI);
|
||||
}
|
||||
|
||||
if ((hi2c->XferISR != I2C_Mem_ISR_DMA) && (InterruptRequest == I2C_XFER_RELOAD_IT))
|
||||
if (InterruptRequest == I2C_XFER_RELOAD_IT)
|
||||
{
|
||||
/* Enable TC interrupts */
|
||||
tmpisr |= I2C_IT_TCI;
|
||||
@ -1022,6 +1022,9 @@ void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_M
|
||||
assert_param(IS_RCC_MCODIV(RCC_MCODiv));
|
||||
assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
|
||||
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(RCC_MCOx);
|
||||
|
||||
/* Configure the MCO1 pin in alternate function mode */
|
||||
gpio.Mode = GPIO_MODE_AF_PP;
|
||||
gpio.Speed = GPIO_SPEED_FREQ_HIGH;
|
||||
@ -3822,13 +3822,16 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
|
||||
*/
|
||||
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
||||
{
|
||||
uint32_t itsource = htim->Instance->DIER;
|
||||
uint32_t itflag = htim->Instance->SR;
|
||||
|
||||
/* Capture compare 1 event */
|
||||
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
|
||||
if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
|
||||
{
|
||||
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
|
||||
if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
|
||||
{
|
||||
{
|
||||
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
|
||||
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
|
||||
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
|
||||
|
||||
/* Input capture event */
|
||||
@ -3856,11 +3859,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
||||
}
|
||||
}
|
||||
/* Capture compare 2 event */
|
||||
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
|
||||
if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
|
||||
{
|
||||
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
|
||||
if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
|
||||
{
|
||||
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
|
||||
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
|
||||
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
|
||||
/* Input capture event */
|
||||
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
|
||||
@ -3886,11 +3889,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
||||
}
|
||||
}
|
||||
/* Capture compare 3 event */
|
||||
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
|
||||
if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
|
||||
{
|
||||
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
|
||||
if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
|
||||
{
|
||||
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
|
||||
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
|
||||
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
|
||||
/* Input capture event */
|
||||
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
|
||||
@ -3916,11 +3919,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
||||
}
|
||||
}
|
||||
/* Capture compare 4 event */
|
||||
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
|
||||
if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
|
||||
{
|
||||
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
|
||||
if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
|
||||
{
|
||||
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
|
||||
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
|
||||
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
|
||||
/* Input capture event */
|
||||
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
|
||||
@ -3946,11 +3949,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
||||
}
|
||||
}
|
||||
/* TIM Update event */
|
||||
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
|
||||
if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
|
||||
{
|
||||
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
|
||||
if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
|
||||
{
|
||||
__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
|
||||
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
|
||||
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
||||
htim->PeriodElapsedCallback(htim);
|
||||
#else
|
||||
@ -3959,11 +3962,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
||||
}
|
||||
}
|
||||
/* TIM Break input event */
|
||||
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
|
||||
if ((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK))
|
||||
{
|
||||
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
|
||||
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
|
||||
{
|
||||
__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
|
||||
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK);
|
||||
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
||||
htim->BreakCallback(htim);
|
||||
#else
|
||||
@ -3972,11 +3975,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
||||
}
|
||||
}
|
||||
/* TIM Trigger detection event */
|
||||
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
|
||||
if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
|
||||
{
|
||||
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
|
||||
if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
|
||||
{
|
||||
__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
|
||||
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
|
||||
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
||||
htim->TriggerCallback(htim);
|
||||
#else
|
||||
@ -3985,11 +3988,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
||||
}
|
||||
}
|
||||
/* TIM commutation event */
|
||||
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
|
||||
if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
|
||||
{
|
||||
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
|
||||
if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
|
||||
{
|
||||
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
|
||||
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
|
||||
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
||||
htim->CommutationCallback(htim);
|
||||
#else
|
||||
@ -4476,7 +4479,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
|
||||
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength)
|
||||
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
|
||||
uint32_t BurstLength)
|
||||
{
|
||||
HAL_StatusTypeDef status;
|
||||
|
||||
@ -6819,6 +6823,13 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure
|
||||
/* Generate an update event to reload the Prescaler
|
||||
and the repetition counter (only for advanced timer) value immediately */
|
||||
TIMx->EGR = TIM_EGR_UG;
|
||||
|
||||
/* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
|
||||
if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
|
||||
{
|
||||
/* Clear the update flag */
|
||||
CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
@ -6833,11 +6844,12 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co
|
||||
uint32_t tmpccer;
|
||||
uint32_t tmpcr2;
|
||||
|
||||
/* Get the TIMx CCER register value */
|
||||
tmpccer = TIMx->CCER;
|
||||
|
||||
/* Disable the Channel 1: Reset the CC1E Bit */
|
||||
TIMx->CCER &= ~TIM_CCER_CC1E;
|
||||
|
||||
/* Get the TIMx CCER register value */
|
||||
tmpccer = TIMx->CCER;
|
||||
/* Get the TIMx CR2 register value */
|
||||
tmpcr2 = TIMx->CR2;
|
||||
|
||||
@ -6908,11 +6920,12 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
||||
uint32_t tmpccer;
|
||||
uint32_t tmpcr2;
|
||||
|
||||
/* Get the TIMx CCER register value */
|
||||
tmpccer = TIMx->CCER;
|
||||
|
||||
/* Disable the Channel 2: Reset the CC2E Bit */
|
||||
TIMx->CCER &= ~TIM_CCER_CC2E;
|
||||
|
||||
/* Get the TIMx CCER register value */
|
||||
tmpccer = TIMx->CCER;
|
||||
/* Get the TIMx CR2 register value */
|
||||
tmpcr2 = TIMx->CR2;
|
||||
|
||||
@ -6941,7 +6954,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
||||
tmpccer |= (OC_Config->OCNPolarity << 4U);
|
||||
/* Reset the Output N State */
|
||||
tmpccer &= ~TIM_CCER_CC2NE;
|
||||
|
||||
}
|
||||
|
||||
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
||||
@ -6984,11 +6996,12 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co
|
||||
uint32_t tmpccer;
|
||||
uint32_t tmpcr2;
|
||||
|
||||
/* Get the TIMx CCER register value */
|
||||
tmpccer = TIMx->CCER;
|
||||
|
||||
/* Disable the Channel 3: Reset the CC2E Bit */
|
||||
TIMx->CCER &= ~TIM_CCER_CC3E;
|
||||
|
||||
/* Get the TIMx CCER register value */
|
||||
tmpccer = TIMx->CCER;
|
||||
/* Get the TIMx CR2 register value */
|
||||
tmpcr2 = TIMx->CR2;
|
||||
|
||||
@ -7058,11 +7071,12 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co
|
||||
uint32_t tmpccer;
|
||||
uint32_t tmpcr2;
|
||||
|
||||
/* Get the TIMx CCER register value */
|
||||
tmpccer = TIMx->CCER;
|
||||
|
||||
/* Disable the Channel 4: Reset the CC4E Bit */
|
||||
TIMx->CCER &= ~TIM_CCER_CC4E;
|
||||
|
||||
/* Get the TIMx CCER register value */
|
||||
tmpccer = TIMx->CCER;
|
||||
/* Get the TIMx CR2 register value */
|
||||
tmpcr2 = TIMx->CR2;
|
||||
|
||||
@ -7253,9 +7267,9 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_
|
||||
uint32_t tmpccer;
|
||||
|
||||
/* Disable the Channel 1: Reset the CC1E Bit */
|
||||
tmpccer = TIMx->CCER;
|
||||
TIMx->CCER &= ~TIM_CCER_CC1E;
|
||||
tmpccmr1 = TIMx->CCMR1;
|
||||
tmpccer = TIMx->CCER;
|
||||
|
||||
/* Select the Input */
|
||||
if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
|
||||
@ -7343,9 +7357,9 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
|
||||
uint32_t tmpccer;
|
||||
|
||||
/* Disable the Channel 2: Reset the CC2E Bit */
|
||||
tmpccer = TIMx->CCER;
|
||||
TIMx->CCER &= ~TIM_CCER_CC2E;
|
||||
tmpccmr1 = TIMx->CCMR1;
|
||||
tmpccer = TIMx->CCER;
|
||||
|
||||
/* Select the Input */
|
||||
tmpccmr1 &= ~TIM_CCMR1_CC2S;
|
||||
@ -7382,9 +7396,9 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
|
||||
uint32_t tmpccer;
|
||||
|
||||
/* Disable the Channel 2: Reset the CC2E Bit */
|
||||
tmpccer = TIMx->CCER;
|
||||
TIMx->CCER &= ~TIM_CCER_CC2E;
|
||||
tmpccmr1 = TIMx->CCMR1;
|
||||
tmpccer = TIMx->CCER;
|
||||
|
||||
/* Set the filter */
|
||||
tmpccmr1 &= ~TIM_CCMR1_IC2F;
|
||||
@ -7426,9 +7440,9 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
|
||||
uint32_t tmpccer;
|
||||
|
||||
/* Disable the Channel 3: Reset the CC3E Bit */
|
||||
tmpccer = TIMx->CCER;
|
||||
TIMx->CCER &= ~TIM_CCER_CC3E;
|
||||
tmpccmr2 = TIMx->CCMR2;
|
||||
tmpccer = TIMx->CCER;
|
||||
|
||||
/* Select the Input */
|
||||
tmpccmr2 &= ~TIM_CCMR2_CC3S;
|
||||
@ -7474,9 +7488,9 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
|
||||
uint32_t tmpccer;
|
||||
|
||||
/* Disable the Channel 4: Reset the CC4E Bit */
|
||||
tmpccer = TIMx->CCER;
|
||||
TIMx->CCER &= ~TIM_CCER_CC4E;
|
||||
tmpccmr2 = TIMx->CCMR2;
|
||||
tmpccer = TIMx->CCER;
|
||||
|
||||
/* Select the Input */
|
||||
tmpccmr2 &= ~TIM_CCMR2_CC4S;
|
||||
@ -836,7 +836,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe
|
||||
|
||||
/* Disable the TIM Break interrupt (only if no more channel is active) */
|
||||
tmpccer = htim->Instance->CCER;
|
||||
if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
|
||||
if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
|
||||
{
|
||||
__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
|
||||
}
|
||||
@ -1082,17 +1082,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
|
||||
(+) Stop the Complementary PWM and disable interrupts.
|
||||
(+) Start the Complementary PWM and enable DMA transfers.
|
||||
(+) Stop the Complementary PWM and disable DMA transfers.
|
||||
(+) Start the Complementary Input Capture measurement.
|
||||
(+) Stop the Complementary Input Capture.
|
||||
(+) Start the Complementary Input Capture and enable interrupts.
|
||||
(+) Stop the Complementary Input Capture and disable interrupts.
|
||||
(+) Start the Complementary Input Capture and enable DMA transfers.
|
||||
(+) Stop the Complementary Input Capture and disable DMA transfers.
|
||||
(+) Start the Complementary One Pulse generation.
|
||||
(+) Stop the Complementary One Pulse.
|
||||
(+) Start the Complementary One Pulse and enable interrupts.
|
||||
(+) Stop the Complementary One Pulse and disable interrupts.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
@ -1318,7 +1307,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann
|
||||
|
||||
/* Disable the TIM Break interrupt (only if no more channel is active) */
|
||||
tmpccer = htim->Instance->CCER;
|
||||
if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
|
||||
if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
|
||||
{
|
||||
__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
|
||||
}
|
||||
@ -2113,7 +2102,7 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Hall commutation changed callback in non-blocking mode
|
||||
* @brief Commutation callback in non-blocking mode
|
||||
* @param htim TIM handle
|
||||
* @retval None
|
||||
*/
|
||||
@ -2127,7 +2116,7 @@ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
|
||||
*/
|
||||
}
|
||||
/**
|
||||
* @brief Hall commutation changed half complete callback in non-blocking mode
|
||||
* @brief Commutation half complete callback in non-blocking mode
|
||||
* @param htim TIM handle
|
||||
* @retval None
|
||||
*/
|
||||
@ -2142,7 +2131,7 @@ __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Hall Break detection callback in non-blocking mode
|
||||
* @brief Break detection callback in non-blocking mode
|
||||
* @param htim TIM handle
|
||||
* @retval None
|
||||
*/
|
||||
@ -2293,15 +2282,6 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
|
||||
}
|
||||
}
|
||||
else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
|
||||
{
|
||||
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
|
||||
|
||||
if (hdma->Init.Mode == DMA_NORMAL)
|
||||
{
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* nothing to do */
|
||||
@ -2370,13 +2350,13 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha
|
||||
{
|
||||
uint32_t tmp;
|
||||
|
||||
tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
|
||||
tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */
|
||||
|
||||
/* Reset the CCxNE Bit */
|
||||
TIMx->CCER &= ~tmp;
|
||||
|
||||
/* Set or reset the CCxNE Bit */
|
||||
TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
|
||||
TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
@ -105,7 +105,7 @@
|
||||
|
||||
[..]
|
||||
Use function HAL_UART_UnRegisterCallback() to reset a callback to the default
|
||||
weak (surcharged) function.
|
||||
weak function.
|
||||
HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
|
||||
and the Callback ID.
|
||||
This function allows to reset following callbacks:
|
||||
@ -127,10 +127,10 @@
|
||||
|
||||
[..]
|
||||
By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
|
||||
all callbacks are set to the corresponding weak (surcharged) functions:
|
||||
all callbacks are set to the corresponding weak functions:
|
||||
examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback().
|
||||
Exception done for MspInit and MspDeInit functions that are respectively
|
||||
reset to the legacy weak (surcharged) functions in the HAL_UART_Init()
|
||||
reset to the legacy weak functions in the HAL_UART_Init()
|
||||
and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
|
||||
If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit()
|
||||
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
|
||||
@ -147,7 +147,7 @@
|
||||
[..]
|
||||
When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
|
||||
not defined, the callback registration feature is not available
|
||||
and weak (surcharged) callbacks are used.
|
||||
and weak callbacks are used.
|
||||
|
||||
|
||||
@endverbatim
|
||||
@ -191,8 +191,8 @@
|
||||
/** @addtogroup UART_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
|
||||
static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
|
||||
static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
|
||||
static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
|
||||
static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
|
||||
static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
|
||||
@ -330,17 +330,19 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
|
||||
|
||||
__HAL_UART_DISABLE(huart);
|
||||
|
||||
/* Perform advanced settings configuration */
|
||||
/* For some items, configuration requires to be done prior TE and RE bits are set */
|
||||
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
||||
{
|
||||
UART_AdvFeatureConfig(huart);
|
||||
}
|
||||
|
||||
/* Set the UART Communication parameters */
|
||||
if (UART_SetConfig(huart) == HAL_ERROR)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
||||
{
|
||||
UART_AdvFeatureConfig(huart);
|
||||
}
|
||||
|
||||
/* In asynchronous mode, the following bits must be kept cleared:
|
||||
- LINEN (if LIN is supported) and CLKEN bits in the USART_CR2 register,
|
||||
- SCEN (if Smartcard is supported), HDSEL and IREN (if IrDA is supported) bits in the USART_CR3 register.*/
|
||||
@ -411,17 +413,19 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
|
||||
|
||||
__HAL_UART_DISABLE(huart);
|
||||
|
||||
/* Perform advanced settings configuration */
|
||||
/* For some items, configuration requires to be done prior TE and RE bits are set */
|
||||
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
||||
{
|
||||
UART_AdvFeatureConfig(huart);
|
||||
}
|
||||
|
||||
/* Set the UART Communication parameters */
|
||||
if (UART_SetConfig(huart) == HAL_ERROR)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
||||
{
|
||||
UART_AdvFeatureConfig(huart);
|
||||
}
|
||||
|
||||
/* In half-duplex mode, the following bits must be kept cleared:
|
||||
- LINEN (if LIN is supported) and CLKEN bits in the USART_CR2 register,
|
||||
- SCEN (if Smartcard is supported) and IREN (if IrDA is supported) bits in the USART_CR3 register.*/
|
||||
@ -512,17 +516,19 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe
|
||||
|
||||
__HAL_UART_DISABLE(huart);
|
||||
|
||||
/* Perform advanced settings configuration */
|
||||
/* For some items, configuration requires to be done prior TE and RE bits are set */
|
||||
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
||||
{
|
||||
UART_AdvFeatureConfig(huart);
|
||||
}
|
||||
|
||||
/* Set the UART Communication parameters */
|
||||
if (UART_SetConfig(huart) == HAL_ERROR)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
||||
{
|
||||
UART_AdvFeatureConfig(huart);
|
||||
}
|
||||
|
||||
/* In LIN mode, the following bits must be kept cleared:
|
||||
- LINEN and CLKEN bits in the USART_CR2 register,
|
||||
- SCEN(if Smartcard is supported) and IREN(if IrDA is supported) bits in the USART_CR3 register.*/
|
||||
@ -609,17 +615,19 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add
|
||||
|
||||
__HAL_UART_DISABLE(huart);
|
||||
|
||||
/* Perform advanced settings configuration */
|
||||
/* For some items, configuration requires to be done prior TE and RE bits are set */
|
||||
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
||||
{
|
||||
UART_AdvFeatureConfig(huart);
|
||||
}
|
||||
|
||||
/* Set the UART Communication parameters */
|
||||
if (UART_SetConfig(huart) == HAL_ERROR)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
||||
{
|
||||
UART_AdvFeatureConfig(huart);
|
||||
}
|
||||
|
||||
/* In multiprocessor mode, the following bits must be kept cleared:
|
||||
- LINEN (if LIN is supported) and CLKEN bits in the USART_CR2 register,
|
||||
- SCEN (if Smartcard is supported), HDSEL and IREN (if IrDA is supported) bits in the USART_CR3 register. */
|
||||
@ -738,7 +746,7 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
|
||||
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief Register a User UART Callback
|
||||
* To be used instead of the weak predefined callback
|
||||
* To be used to override the weak predefined callback
|
||||
* @note The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(),
|
||||
* HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to register
|
||||
* callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID
|
||||
@ -994,10 +1002,7 @@ HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pU
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(huart);
|
||||
|
||||
if (huart->gState == HAL_UART_STATE_READY)
|
||||
if (huart->RxState == HAL_UART_STATE_READY)
|
||||
{
|
||||
huart->RxEventCallback = pCallback;
|
||||
}
|
||||
@ -1008,9 +1013,6 @@ HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pU
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(huart);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
@ -1024,10 +1026,7 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(huart);
|
||||
|
||||
if (huart->gState == HAL_UART_STATE_READY)
|
||||
if (huart->RxState == HAL_UART_STATE_READY)
|
||||
{
|
||||
huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */
|
||||
}
|
||||
@ -1038,8 +1037,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart)
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(huart);
|
||||
return status;
|
||||
}
|
||||
|
||||
@ -3180,6 +3177,13 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
|
||||
/* Check whether the set of advanced features to configure is properly set */
|
||||
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
|
||||
|
||||
/* if required, configure RX/TX pins swap */
|
||||
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
|
||||
{
|
||||
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
|
||||
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
|
||||
}
|
||||
|
||||
/* if required, configure TX pin active level inversion */
|
||||
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
|
||||
{
|
||||
@ -3201,13 +3205,6 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
|
||||
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
|
||||
}
|
||||
|
||||
/* if required, configure RX/TX pins swap */
|
||||
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
|
||||
{
|
||||
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
|
||||
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
|
||||
}
|
||||
|
||||
/* if required, configure RX overrun detection disabling */
|
||||
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
|
||||
{
|
||||
@ -3333,7 +3330,7 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
|
||||
if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
|
||||
if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
|
||||
{
|
||||
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
|
||||
{
|
||||
@ -195,17 +195,19 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity,
|
||||
/* Disable the Peripheral */
|
||||
__HAL_UART_DISABLE(huart);
|
||||
|
||||
/* Perform advanced settings configuration */
|
||||
/* For some items, configuration requires to be done prior TE and RE bits are set */
|
||||
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
||||
{
|
||||
UART_AdvFeatureConfig(huart);
|
||||
}
|
||||
|
||||
/* Set the UART Communication parameters */
|
||||
if (UART_SetConfig(huart) == HAL_ERROR)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
||||
{
|
||||
UART_AdvFeatureConfig(huart);
|
||||
}
|
||||
|
||||
/* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
|
||||
SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
|
||||
|
||||
@ -634,7 +636,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
|
||||
{
|
||||
HAL_StatusTypeDef status;
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check that a Rx process is not already ongoing */
|
||||
if (huart->RxState == HAL_UART_STATE_READY)
|
||||
@ -659,11 +661,8 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t
|
||||
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
|
||||
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
||||
|
||||
status = UART_Start_Receive_IT(huart, pData, Size);
|
||||
(void)UART_Start_Receive_IT(huart, pData, Size);
|
||||
|
||||
/* Check Rx process has been successfully started */
|
||||
if (status == HAL_OK)
|
||||
{
|
||||
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
||||
{
|
||||
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
||||
@ -677,7 +676,6 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t
|
||||
In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
@ -788,7 +786,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_
|
||||
* @param huart UART handle.
|
||||
* @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values)
|
||||
*/
|
||||
HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart)
|
||||
HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart)
|
||||
{
|
||||
/* Return Rx Event type value, as stored in UART handle */
|
||||
return (huart->RxEventType);
|
||||
@ -7,7 +7,7 @@
|
||||
|
||||
<Targets>
|
||||
<Target>
|
||||
<TargetName>stm32f0_cherryusb</TargetName>
|
||||
<TargetName>stm32f072_usb_mouse_keyboard</TargetName>
|
||||
<ToolsetNumber>0x4</ToolsetNumber>
|
||||
<ToolsetName>ARM-ADS</ToolsetName>
|
||||
<pCCUsed>6160000::V6.16::ARMCLANG</pCCUsed>
|
||||
@ -48,8 +48,8 @@
|
||||
<NotGenerated>0</NotGenerated>
|
||||
<InvalidFlash>1</InvalidFlash>
|
||||
</TargetStatus>
|
||||
<OutputDirectory>stm32f0_cherryusb\</OutputDirectory>
|
||||
<OutputName>stm32f0_cherryusb</OutputName>
|
||||
<OutputDirectory>stm32f072_usb_mouse_keyboard\</OutputDirectory>
|
||||
<OutputName>stm32f072_usb_mouse_keyboard</OutputName>
|
||||
<CreateExecutable>1</CreateExecutable>
|
||||
<CreateLib>0</CreateLib>
|
||||
<CreateHexFile>1</CreateHexFile>
|
||||
@ -134,11 +134,11 @@
|
||||
<RunIndependent>0</RunIndependent>
|
||||
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
|
||||
<Capability>1</Capability>
|
||||
<DriverSelection>4096</DriverSelection>
|
||||
<DriverSelection>4101</DriverSelection>
|
||||
</Flash1>
|
||||
<bUseTDR>1</bUseTDR>
|
||||
<Flash2>BIN\UL2CM3.DLL</Flash2>
|
||||
<Flash3>"" ()</Flash3>
|
||||
<Flash2>BIN\UL2V8M.DLL</Flash2>
|
||||
<Flash3></Flash3>
|
||||
<Flash4></Flash4>
|
||||
<pFcarmOut></pFcarmOut>
|
||||
<pFcarmGrp></pFcarmGrp>
|
||||
@ -339,7 +339,7 @@
|
||||
<MiscControls></MiscControls>
|
||||
<Define>USE_HAL_DRIVER,STM32F072xB</Define>
|
||||
<Undefine></Undefine>
|
||||
<IncludePath>../Core/Inc;../Drivers/STM32F0xx_HAL_Driver/Inc;../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy;../Drivers/CMSIS/Device/ST/STM32F0xx/Include;../Drivers/CMSIS/Include;../3rdParty/CherryUSB/class/hid;../3rdParty/CherryUSB/common;../3rdParty/CherryUSB/core;../3rdParty/CherryUSB/port/fsdev</IncludePath>
|
||||
<IncludePath>../Core/Inc;../Drivers/STM32F0xx_HAL_Driver/Inc;../Drivers/STM32F0xx_HAL_Driver/Inc/Legacy;../Drivers/CMSIS/Device/ST/STM32F0xx/Include;../Drivers/CMSIS/Include;..\Third_Party\CherryUSB\class\hid;..\Third_Party\CherryUSB\common;..\Third_Party\CherryUSB\core;..\Third_Party\CherryUSB\port\fsdev</IncludePath>
|
||||
</VariousControls>
|
||||
</Cads>
|
||||
<Aads>
|
||||
@ -393,16 +393,6 @@
|
||||
<Group>
|
||||
<GroupName>Application/User/Core</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>hid_keyboard_mouse.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\Core\Src\hid_keyboard_mouse.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>bsp_key.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\Core\Src\bsp_key.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>main.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
@ -418,6 +408,16 @@
|
||||
<FileType>1</FileType>
|
||||
<FilePath>../Core/Src/stm32f0xx_hal_msp.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>bsp_key.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\Core\Src\bsp_key.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>hid_keyboard_mouse.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\Core\Src\hid_keyboard_mouse.c</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
@ -521,22 +521,27 @@
|
||||
</Files>
|
||||
</Group>
|
||||
<Group>
|
||||
<GroupName>3rdParty/CherryUSB</GroupName>
|
||||
<GroupName>Third_Party/CherryUSB</GroupName>
|
||||
<Files>
|
||||
<File>
|
||||
<FileName>usbd_core.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\3rdParty\CherryUSB\core\usbd_core.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>usbd_hid.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\3rdParty\CherryUSB\class\hid\usbd_hid.c</FilePath>
|
||||
<FilePath>..\Third_Party\CherryUSB\class\hid\usbd_hid.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>usbd_core.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\Third_Party\CherryUSB\core\usbd_core.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>usb_dc_fsdev.c</FileName>
|
||||
<FileType>1</FileType>
|
||||
<FilePath>..\3rdParty\CherryUSB\port\fsdev\usb_dc_fsdev.c</FilePath>
|
||||
<FilePath>..\Third_Party\CherryUSB\port\fsdev\usb_dc_fsdev.c</FilePath>
|
||||
</File>
|
||||
<File>
|
||||
<FileName>usb_config.h</FileName>
|
||||
<FileType>5</FileType>
|
||||
<FilePath>..\Core\Inc\usb_config.h</FilePath>
|
||||
</File>
|
||||
</Files>
|
||||
</Group>
|
||||
@ -553,7 +558,7 @@
|
||||
<component Cclass="CMSIS" Cgroup="CORE" Cvendor="ARM" Cversion="5.5.0" condition="ARMv6_7_8-M Device">
|
||||
<package name="CMSIS" schemaVersion="1.3" url="http://www.keil.com/pack/" vendor="ARM" version="5.8.0"/>
|
||||
<targetInfos>
|
||||
<targetInfo name="stm32f0_cherryusb"/>
|
||||
<targetInfo name="stm32f072_usb_mouse_keyboard"/>
|
||||
</targetInfos>
|
||||
</component>
|
||||
</components>
|
||||
@ -563,7 +568,7 @@
|
||||
<LayerInfo>
|
||||
<Layers>
|
||||
<Layer>
|
||||
<LayName>stm32f0_cherryusb</LayName>
|
||||
<LayName>stm32f072_usb_mouse_keyboard</LayName>
|
||||
<LayPrjMark>1</LayPrjMark>
|
||||
</Layer>
|
||||
</Layers>
|
||||
@ -34,29 +34,16 @@ Taking into account USB performance issues and trying to achieve the theoretical
|
||||
- Unlimited length make it easier to interface with hardware DMA and take advantage of DMA
|
||||
- Subcontracting function is handled in interrupt
|
||||
|
||||
## Directoy Structure
|
||||
|
||||
```
|
||||
.
|
||||
├── class
|
||||
├── common
|
||||
├── core
|
||||
├── demo
|
||||
├── docs
|
||||
├── osal
|
||||
├── packet capture
|
||||
└── port
|
||||
└── tools
|
||||
|
||||
```
|
||||
## Directory Structure
|
||||
|
||||
| Directory | Description |
|
||||
|:-------------:|:---------------------------:|
|
||||
|class | usb class driver |
|
||||
|common | usb spec macros and utils |
|
||||
|core | usb core implementation |
|
||||
|demo | different chips demo |
|
||||
|demo | usb device and host demo |
|
||||
|osal | os wrapper |
|
||||
|platform | class support for other os |
|
||||
|docs | doc for guiding |
|
||||
|port | usb dcd and hcd porting |
|
||||
|tools | tool url |
|
||||
@ -78,15 +65,17 @@ CherryUSB Device Stack has the following functions：
|
||||
- Support Device Firmware Upgrade CLASS (DFU)
|
||||
- Support USB MIDI CLASS (MIDI)
|
||||
- Support Remote NDIS (RNDIS)
|
||||
- Support WINUSB1.0、WINUSB2.0(with BOS)
|
||||
- Support WINUSB1.0、WINUSB2.0、WEBUSB、BOS
|
||||
- Support Vendor class
|
||||
- Support UF2
|
||||
- Support Android Debug Bridge (Only support shell)
|
||||
- Support multi device with the same USB IP
|
||||
|
||||
CherryUSB Device Stack resource usage (GCC 10.2 with -O2):
|
||||
|
||||
| file | FLASH (Byte) | No Cache RAM (Byte) | RAM (Byte) | Heap (Byte) |
|
||||
|:-------------:|:--------------:|:-------------------------:|:-------------:|:----------------:|
|
||||
|usbd_core.c | 3516 | 256(default) + 320 | 0 | 0 |
|
||||
|usbd_core.c | 3516 | 512(default) + 320 | 0 | 0 |
|
||||
|usbd_cdc.c | 392 | 0 | 0 | 0 |
|
||||
|usbd_msc.c | 2839 | 128 + 512(default) | 16 | 0 |
|
||||
|usbd_hid.c | 364 | 0 | 0 | 0 |
|
||||
@ -100,6 +89,7 @@ The CherryUSB Host Stack has a standard enumeration implementation for devices m
|
||||
|
||||
CherryUSB Host Stack has the following functions：
|
||||
|
||||
- Support low speed, full speed, high speed and super speed devices
|
||||
- Automatic loading of supported Class drivers
|
||||
- Support blocking transfers and asynchronous transfers
|
||||
- Support Composite Device
|
||||
@ -107,11 +97,11 @@ CherryUSB Host Stack has the following functions：
|
||||
- Support Communication Device Class (CDC_ACM, CDC_ECM)
|
||||
- Support Human Interface Device (HID)
|
||||
- Support Mass Storage Class (MSC)
|
||||
- Support USB Video CLASS (commercial charge)
|
||||
- Support USB Audio CLASS (commercial charge)
|
||||
- Support USB Video CLASS (UVC1.0、UVC1.5)
|
||||
- Support USB Audio CLASS (UAC1.0)
|
||||
- Support Remote NDIS (RNDIS)
|
||||
- Support USB Bluetooth class (support nimble and zephyr bluetooth stack, support **CLASS:0xE0** or vendor class like cdc acm)
|
||||
- Support Vendor class
|
||||
- Support Vendor class (serial, net, wifi)
|
||||
- Support USB modeswitch
|
||||
- Support multi host with the same USB IP
|
||||
|
||||
@ -121,14 +111,14 @@ CherryUSB Host Stack resource usage (GCC 10.2 with -O2):
|
||||
|
||||
| file | FLASH (Byte) | No Cache RAM (Byte) | RAM (Byte) | Heap (Byte) |
|
||||
|:-------------:|:--------------:|:-------------------------------:|:---------------------------:|:------------:|
|
||||
|usbh_core.c | ~7700 | 512 + 8 * (1+x) *n | 28 | 0 |
|
||||
|usbh_core.c | ~7700 | 512 + 8 * (1+x) *n | 28 | raw_config_desc |
|
||||
|usbh_hub.c | ~5600 | 32 + 4* (1+x) | 12 + sizeof(struct usbh_hub) * (1+x) | 0 |
|
||||
|usbh_cdc_acm.c | ~1200 | 7 | 4 + sizeof(struct usbh_cdc_acm) * x | 0 |
|
||||
|usbh_msc.c | ~2500 | 32 | 4 + sizeof(struct usbh_msc) * x | 0 |
|
||||
|usbh_hid.c | ~1000 | 128 | 4 + sizeof(struct usbh_hid) * x | 0 |
|
||||
|usbh_video.c | ~3700 | 128 | 4 + sizeof(struct usbh_video) * x | 0 |
|
||||
|usbh_audio.c | ~3100 | 128 | 4 + sizeof(struct usbh_audio) * x | 0 |
|
||||
|usbh_rndis.c | ~3900 | 4096 + 2 * 2048 | sizeof(struct usbh_rndis) * 1 | 0 |
|
||||
|usbh_rndis.c | ~3900 | 4096 + 2 * 2048(default)| sizeof(struct usbh_rndis) * 1 | 0 |
|
||||
|usbh_cdc_ecm.c | ~2500 | 2 * 1514 | sizeof(struct usbh_cdc_ecm) * 1 | 0 |
|
||||
|usbh_bluetooth.c | ~2300 | 2 * 2048(default) | sizeof(struct usbh_bluetooth) * 1 | 0 |
|
||||
|
||||
@ -165,6 +155,7 @@ Only standard and commercial USB IP are listed.
|
||||
| DWC2(synopsys) | DWC2 | DWC2 | √ |
|
||||
| MUSB(mentor) | MUSB | MUSB | √ |
|
||||
| FOTG210(faraday)| FOTG210 | EHCI | √ |
|
||||
| CHIPIDEA(synopsys)| CHIPIDEA | EHCI | √ |
|
||||
| CDNS2(cadence) | CDNS2 | CDNS2 | √ |
|
||||
| CDNS3(cadence) | CDNS3 | XHCI | × |
|
||||
| DWC3(synopsys) | DWC3 | XHCI | × |
|
||||
@ -188,16 +179,30 @@ USB basic concepts and how the CherryUSB Device stack is implemented, see [Cherr
|
||||
|Bouffalolab | BL702/BL616/BL808 | bouffalolab/ehci|[bouffalo_sdk](https://github.com/CherryUSB/bouffalo_sdk)|<= latest | Long-term |
|
||||
|ST | STM32F1x | fsdev |[stm32_repo](https://github.com/CherryUSB/cherryusb_stm32)|<= latest | Long-term |
|
||||
|ST | STM32F4/STM32H7 | dwc2 |[stm32_repo](https://github.com/CherryUSB/cherryusb_stm32)|<= latest | Long-term |
|
||||
|HPMicro | HPM6750 | hpm/ehci |[hpm_sdk](https://github.com/CherryUSB/hpm_sdk)|<= latest | Long-term |
|
||||
|HPMicro | HPM6000/HPM5000 | hpm/ehci |[hpm_sdk](https://github.com/CherryUSB/hpm_sdk)|<= latest | Long-term |
|
||||
|Essemi | ES32F36xx | musb |[es32f369_repo](https://github.com/CherryUSB/cherryusb_es32)|<= latest | Long-term |
|
||||
|Phytium | e2000 | pusb2/xhci |[phytium_repo](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk)|v0.10.2 | Long-term |
|
||||
|artinchip | d12x/d13x/d21x | dwc2/ehci/ohci |[luban-lite](https://gitee.com/artinchip/luban-lite)|<= latest | Long-term |
|
||||
|Espressif | esp32s2/esp32s3 | dwc2 |[esp32_repo](https://github.com/CherryUSB/cherryusb_esp32)|<= latest | the same with ST |
|
||||
|AllwinnerTech | F1C100S/F1C200S | musb |[cherryusb_rtt_f1c100s](https://github.com/CherryUSB/cherryusb_rtt_f1c100s)|<= latest | the same with Essemi |
|
||||
|Phytium | e2000 | pusb2/xhci |[phytium_repo](https://gitee.com/phytium_embedded/phytium-free-rtos-sdk)|>=1.4.0 | Long-term |
|
||||
|Artinchip | d12x/d13x/d21x | aic/ehci/ohci |[luban-lite](https://gitee.com/artinchip/luban-lite)|<= latest | Long-term |
|
||||
|Espressif | esp32s2/esp32s3/esp32p4 | dwc2 |[esp32_repo](https://github.com/CherryUSB/cherryusb_esp32)|<= latest | Long-term |
|
||||
|NXP | mcx | chipidea/ehci |[nxp_mcx_repo](https://github.com/CherryUSB/cherryusb_mcx)|<= latest | Long-term |
|
||||
|AllwinnerTech | F1C100S/F1C200S | musb |[cherryusb_rtt_f1c100s](https://github.com/CherryUSB/cherryusb_rtt_f1c100s)|<= latest | the same with musb |
|
||||
|Bekencorp | bk7256/bk7258 | musb |[bk_idk](https://github.com/CherryUSB/bk_idk)| v0.7.0 | the same with musb |
|
||||
|Sophgo | cv18xx | dwc2 |[cvi_alios_open](https://github.com/CherryUSB/cvi_alios_open)| v0.7.0 | TBD |
|
||||
|WCH | CH32V307/ch58x | ch32_usbfs/ch32_usbhs/ch58x |[wch_repo](https://github.com/CherryUSB/cherryusb_wch)|<= v0.10.2 | TBD |
|
||||
|Nordicsemi | Nrf52840 | nrf5x |[nrf5x_repo](https://github.com/CherryUSB/cherryusb_nrf5x)|<= v0.10.2 | No more updated |
|
||||
|Raspberry pi | rp2040 | rp2040 |[pico-examples](https://github.com/CherryUSB/pico-examples)|<= v0.10.2 | No more updated |
|
||||
|
||||
## Package Support
|
||||
|
||||
CherryUSB package is available as follows:
|
||||
|
||||
- [RT-Thread](https://packages.rt-thread.org/detail.html?package=CherryUSB)
|
||||
- [YOC](https://www.xrvm.cn/document?temp=usb-host-protocol-stack-device-driver-adaptation-instructions&slug=yocbook)
|
||||
- [ESP-Registry](https://components.espressif.com/components/cherry-embedded/cherryusb)
|
||||
|
||||
## Commercial Support
|
||||
|
||||
Refer to https://cherryusb.readthedocs.io/zh-cn/latest/support/index.html.
|
||||
|
||||
## Contact
|
||||
|
||||
CherryUSB discord: https://discord.com/invite/wFfvrSAey8.
|
||||
@ -206,4 +211,4 @@ CherryUSB discord: https://discord.com/invite/wFfvrSAey8.
|
||||
|
||||
Thanks to the following companies for their support (in no particular order).
|
||||
|
||||
<img src="docs/assets/bouffalolab.jpg" width="100" height="100"/> <img src="docs/assets/hpmicro.jpg" width="100" height="100" /> <img src="docs/assets/eastsoft.jpg" width="100" height="100" /> <img src="docs/assets/rtthread.jpg" width="100" height="100" /> <img src="docs/assets/sophgo.jpg" width="100" height="100" /> <img src="docs/assets/phytium.jpg" width="100" height="100" /> <img src="docs/assets/thead.jpg" width="100" height="100" /> <img src="docs/assets/nuvoton.jpg" width="100" height="100" /> <img src="docs/assets/artinchip.jpg" width="100" height="100" />
|
||||
<img src="docs/assets/bouffalolab.jpg" width="100" height="80"/> <img src="docs/assets/hpmicro.jpg" width="100" height="80" /> <img src="docs/assets/eastsoft.jpg" width="100" height="80" /> <img src="docs/assets/rtthread.jpg" width="100" height="80" /> <img src="docs/assets/sophgo.jpg" width="100" height="80" /> <img src="docs/assets/phytium.jpg" width="100" height="80" /> <img src="docs/assets/thead.jpg" width="100" height="80" /> <img src="docs/assets/nuvoton.jpg" width="100" height="80" /> <img src="docs/assets/artinchip.jpg" width="100" height="80" /> <img src="docs/assets/bekencorp.jpg" width="100" height="80" /> <img src="docs/assets/nxp.png" width="100" height="80" /> <img src="docs/assets/espressif.png" width="100" height="80" />
|
||||
@ -558,26 +558,24 @@ struct usb_hid_kbd_report
|
||||
};
|
||||
|
||||
/* Keyboard output report (1 byte) (HID B.1),
|
||||
* see USBHID_KBDOUT_* definitions
|
||||
* see HID_KBD_OUTPUT_* definitions
|
||||
*/
|
||||
|
||||
/* Mouse input report (HID B.2) */
|
||||
struct usb_hid_mouse_report
|
||||
{
|
||||
uint8_t buttons; /* See HID_MOUSE_INPUT_BUTTON_* definitions */
|
||||
uint8_t xdisp; /* X displacement */
|
||||
uint8_t ydisp; /* y displacement */
|
||||
int8_t xdisp; /* X displacement */
|
||||
int8_t ydisp; /* y displacement */
|
||||
/* Device specific additional bytes may follow */
|
||||
#ifdef CONFIG_INPUT_MOUSE_WHEEL
|
||||
uint8_t wdisp; /* Wheel displacement */
|
||||
#endif
|
||||
};
|
||||
|
||||
/* Joystick input report (1 bytes) (HID D.1) */
|
||||
struct usb_hid_js_report
|
||||
{
|
||||
uint8_t xpos; /* X position */
|
||||
uint8_t ypos; /* X position */
|
||||
int8_t xpos; /* X position */
|
||||
int8_t ypos; /* X position */
|
||||
uint8_t buttons; /* See USBHID_JSIN_* definitions */
|
||||
uint8_t throttle; /* Throttle */
|
||||
};
|
||||
@ -50,6 +50,8 @@ static int hid_class_interface_request_handler(uint8_t busid, struct usb_setup_p
|
||||
|
||||
struct usbd_interface *usbd_hid_init_intf(uint8_t busid, struct usbd_interface *intf, const uint8_t *desc, uint32_t desc_len)
|
||||
{
|
||||
(void)busid;
|
||||
|
||||
intf->class_interface_handler = hid_class_interface_request_handler;
|
||||
intf->class_endpoint_handler = NULL;
|
||||
intf->vendor_handler = NULL;
|
||||
@ -60,30 +62,65 @@ struct usbd_interface *usbd_hid_init_intf(uint8_t busid, struct usbd_interface *
|
||||
return intf;
|
||||
}
|
||||
|
||||
/*
|
||||
* Appendix G: HID Request Support Requirements
|
||||
*
|
||||
* The following table enumerates the requests that need to be supported by various types of HID class devices.
|
||||
* Device type GetReport SetReport GetIdle SetIdle GetProtocol SetProtocol
|
||||
* ------------------------------------------------------------------------------------------
|
||||
* Boot Mouse Required Optional Optional Optional Required Required
|
||||
* Non-Boot Mouse Required Optional Optional Optional Optional Optional
|
||||
* Boot Keyboard Required Optional Required Required Required Required
|
||||
* Non-Boot Keybrd Required Optional Required Required Optional Optional
|
||||
* Other Device Required Optional Optional Optional Optional Optional
|
||||
*/
|
||||
|
||||
__WEAK void usbd_hid_get_report(uint8_t busid, uint8_t intf, uint8_t report_id, uint8_t report_type, uint8_t **data, uint32_t *len)
|
||||
{
|
||||
(void)busid;
|
||||
(void)intf;
|
||||
(void)report_id;
|
||||
(void)report_type;
|
||||
(*data[0]) = 0;
|
||||
*len = 1;
|
||||
}
|
||||
|
||||
__WEAK uint8_t usbd_hid_get_idle(uint8_t busid, uint8_t intf, uint8_t report_id)
|
||||
{
|
||||
(void)busid;
|
||||
(void)intf;
|
||||
(void)report_id;
|
||||
return 0;
|
||||
}
|
||||
|
||||
__WEAK uint8_t usbd_hid_get_protocol(uint8_t busid, uint8_t intf)
|
||||
{
|
||||
(void)busid;
|
||||
(void)intf;
|
||||
return 0;
|
||||
}
|
||||
|
||||
__WEAK void usbd_hid_set_report(uint8_t busid, uint8_t intf, uint8_t report_id, uint8_t report_type, uint8_t *report, uint32_t report_len)
|
||||
{
|
||||
(void)busid;
|
||||
(void)intf;
|
||||
(void)report_id;
|
||||
(void)report_type;
|
||||
(void)report;
|
||||
(void)report_len;
|
||||
}
|
||||
|
||||
__WEAK void usbd_hid_set_idle(uint8_t busid, uint8_t intf, uint8_t report_id, uint8_t duration)
|
||||
{
|
||||
(void)busid;
|
||||
(void)intf;
|
||||
(void)report_id;
|
||||
(void)duration;
|
||||
}
|
||||
|
||||
__WEAK void usbd_hid_set_protocol(uint8_t busid, uint8_t intf, uint8_t protocol)
|
||||
{
|
||||
(void)busid;
|
||||
(void)intf;
|
||||
(void)protocol;
|
||||
}
|
||||
@ -36,11 +36,11 @@ int usbd_set_address(uint8_t busid, const uint8_t addr);
|
||||
/**
|
||||
* @brief Get USB device speed
|
||||
*
|
||||
* @param[in] port port index
|
||||
* @param[in] busid bus index
|
||||
*
|
||||
* @return port speed, USB_SPEED_LOW or USB_SPEED_FULL or USB_SPEED_HIGH
|
||||
*/
|
||||
uint8_t usbd_get_port_speed(uint8_t busid, const uint8_t port);
|
||||
uint8_t usbd_get_port_speed(uint8_t busid);
|
||||
|
||||
/**
|
||||
* @brief configure and enable endpoint.
|
||||
@ -34,6 +34,10 @@
|
||||
/**< maximum packet size (MPS) for EP 0 */
|
||||
#define USB_CTRL_EP_MPS 64
|
||||
|
||||
/**< maximum packet size (MPS) for bulk EP */
|
||||
#define USB_BULK_EP_MPS_HS 512
|
||||
#define USB_BULK_EP_MPS_FS 64
|
||||
|
||||
/* USB PID Types */
|
||||
#define USB_PID_OUT (0x01) /* Tokens */
|
||||
#define USB_PID_IN (0x09)
|
||||
@ -538,7 +542,7 @@ struct usb_msosv2_subset_function_descriptor {
|
||||
} __PACKED;
|
||||
|
||||
struct usb_msosv2_descriptor {
|
||||
uint8_t *compat_id;
|
||||
const uint8_t *compat_id;
|
||||
uint16_t compat_id_len;
|
||||
uint8_t vendor_code;
|
||||
};
|
||||
@ -612,12 +616,12 @@ struct usb_webusb_url_descriptor {
|
||||
|
||||
struct usb_webusb_url_ex_descriptor {
|
||||
uint8_t vendor_code;
|
||||
uint8_t *string;
|
||||
const uint8_t *string;
|
||||
uint32_t string_len;
|
||||
} __PACKED;
|
||||
|
||||
struct usb_bos_descriptor {
|
||||
uint8_t *string;
|
||||
const uint8_t *string;
|
||||
uint32_t string_len;
|
||||
};
|
||||
|
||||
@ -660,6 +664,27 @@ struct usb_desc_header {
|
||||
bmAttributes, /* bmAttributes */ \
|
||||
USB_CONFIG_POWER_MA(bMaxPower) /* bMaxPower */
|
||||
|
||||
#define USB_DEVICE_QUALIFIER_DESCRIPTOR_INIT(bcdUSB, bDeviceClass, bDeviceSubClass, bDeviceProtocol, bNumConfigurations) \
|
||||
0x0A, /* bLength */ \
|
||||
USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, /* bDescriptorType */ \
|
||||
WBVAL(bcdUSB), /* bcdUSB */ \
|
||||
bDeviceClass, /* bDeviceClass */ \
|
||||
bDeviceSubClass, /* bDeviceSubClass */ \
|
||||
bDeviceProtocol, /* bDeviceProtocol */ \
|
||||
0x40, /* bMaxPacketSize */ \
|
||||
bNumConfigurations, /* bNumConfigurations */ \
|
||||
0x00 /* bReserved */
|
||||
|
||||
#define USB_OTHER_SPEED_CONFIG_DESCRIPTOR_INIT(wTotalLength, bNumInterfaces, bConfigurationValue, bmAttributes, bMaxPower) \
|
||||
0x09, /* bLength */ \
|
||||
USB_DESCRIPTOR_TYPE_OTHER_SPEED, /* bDescriptorType */ \
|
||||
WBVAL(wTotalLength), /* wTotalLength */ \
|
||||
bNumInterfaces, /* bNumInterfaces */ \
|
||||
bConfigurationValue, /* bConfigurationValue */ \
|
||||
0x00, /* iConfiguration */ \
|
||||
bmAttributes, /* bmAttributes */ \
|
||||
USB_CONFIG_POWER_MA(bMaxPower) /* bMaxPower */
|
||||
|
||||
#define USB_INTERFACE_DESCRIPTOR_INIT(bInterfaceNumber, bAlternateSetting, bNumEndpoints, \
|
||||
bInterfaceClass, bInterfaceSubClass, bInterfaceProtocol, iInterface) \
|
||||
0x09, /* bLength */ \
|
||||
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Reference in New Issue
Block a user