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ch32v203_ir_box: add project

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wangyz1997 2025-02-11 00:25:37 +08:00
parent 21ea48ff4a
commit dc081f7551
46 changed files with 19860 additions and 0 deletions
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1
.gitignore vendored
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# Output folders
obj/
build/
# IDE setting folders
.settings
.vscode

3
.gitmodules vendored Normal file
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[submodule "ch32v203_ir_box/3rdparty/CherryUSB"]
path = ch32v203_ir_box/3rdparty/CherryUSB
url = https://github.com/cherry-embedded/CherryUSB.git

149
ch32v203_ir_box/.cproject Normal file
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ch32v203_ir_box/.project Normal file
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ch32v203_ir_box/.template Normal file
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Vendor=WCH
Toolchain=RISC-V
Series=CH32V203
RTOS=NoneOS
MCU=CH32V203G6U6
Link=WCH-Link
PeripheralVersion==2.2
Description==Website: http://www.wch.cn/products/CH32V203.html?\nROM(byte): 32K, SRAM(byte): 10K, CHIP PINS: 28, GPIO PORTS: 24.\nWCH CH32V2 series of mainstream MCUs covers the needs of a large variety of applications in the industrial,medical and consumer markets. High performance with first-class peripherals and low-power,low-voltage operation is paired with a high level of integration at accessible prices with a simple architecture and easy-to-use tools.
Mcu Type=CH32V20x
Address=0x08000000
Target Path=build\ch32v203_ir_box.hex
CLKSpeed=1
DebugInterfaceMode=-1
Erase All=true
Program=true
Verify=false
Reset=true
SDIPrintf=false

1
ch32v203_ir_box/3rdparty/CherryUSB vendored Submodule

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Subproject commit 1be34f4d367b52b7a57ccf3446f4cc7f7f006abe

BIN
ch32v203_ir_box/ch32v203_ir_box.wvproj Normal file
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ch32v203_ir_box/src/core/core_riscv.c Normal file
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/********************************** (C) COPYRIGHT *******************************
* File Name : core_riscv.c
* Author : WCH
* Version : V1.0.1
* Date : 2023/11/11
* Description : RISC-V V4 Core Peripheral Access Layer Source File for CH32V20x
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include <stdint.h>
/* define compiler specific symbols */
#if defined ( __CC_ARM )
#define __ASM __asm /* asm keyword for ARM Compiler */
#define __INLINE __inline /* inline keyword for ARM Compiler */
#elif defined ( __ICCARM__ )
#define __ASM __asm /* asm keyword for IAR Compiler */
#define __INLINE inline /* inline keyword for IAR Compiler. Only avaiable in High optimization mode */
#elif defined ( __GNUC__ )
#define __ASM __asm /* asm keyword for GNU Compiler */
#define __INLINE inline /* inline keyword for GNU Compiler */
#elif defined ( __TASKING__ )
#define __ASM __asm /* asm keyword for TASKING Compiler */
#define __INLINE inline /* inline keyword for TASKING Compiler */
#endif
/*********************************************************************
* @fn __get_MSTATUS
*
* @brief Return the Machine Status Register
*
* @return mstatus value
*/
uint32_t __get_MSTATUS(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "mstatus" : "=r" (result) );
return (result);
}
/*********************************************************************
* @fn __set_MSTATUS
*
* @brief Set the Machine Status Register
*
* @param value - set mstatus value
*
* @return none
*/
void __set_MSTATUS(uint32_t value)
{
__ASM volatile ("csrw mstatus, %0" : : "r" (value) );
}
/*********************************************************************
* @fn __get_MISA
*
* @brief Return the Machine ISA Register
*
* @return misa value
*/
uint32_t __get_MISA(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "misa" : "=r" (result) );
return (result);
}
/*********************************************************************
* @fn __set_MISA
*
* @brief Set the Machine ISA Register
*
* @param value - set misa value
*
* @return none
*/
void __set_MISA(uint32_t value)
{
__ASM volatile ("csrw misa, %0" : : "r" (value) );
}
/*********************************************************************
* @fn __get_MTVEC
*
* @brief Return the Machine Trap-Vector Base-Address Register
*
* @return mtvec value
*/
uint32_t __get_MTVEC(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "mtvec" : "=r" (result) );
return (result);
}
/*********************************************************************
* @fn __set_MTVEC
*
* @brief Set the Machine Trap-Vector Base-Address Register
*
* @param value - set mtvec value
*
* @return none
*/
void __set_MTVEC(uint32_t value)
{
__ASM volatile ("csrw mtvec, %0" : : "r" (value) );
}
/*********************************************************************
* @fn __get_MSCRATCH
*
* @brief Return the Machine Seratch Register
*
* @return mscratch value
*/
uint32_t __get_MSCRATCH(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "mscratch" : "=r" (result) );
return (result);
}
/*********************************************************************
* @fn __set_MSCRATCH
*
* @brief Set the Machine Seratch Register
*
* @param value - set mscratch value
*
* @return none
*/
void __set_MSCRATCH(uint32_t value)
{
__ASM volatile ("csrw mscratch, %0" : : "r" (value) );
}
/*********************************************************************
* @fn __get_MEPC
*
* @brief Return the Machine Exception Program Register
*
* @return mepc value
*/
uint32_t __get_MEPC(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "mepc" : "=r" (result) );
return (result);
}
/*********************************************************************
* @fn __set_MEPC
*
* @brief Set the Machine Exception Program Register
*
* @return mepc value
*/
void __set_MEPC(uint32_t value)
{
__ASM volatile ("csrw mepc, %0" : : "r" (value) );
}
/*********************************************************************
* @fn __get_MCAUSE
*
* @brief Return the Machine Cause Register
*
* @return mcause value
*/
uint32_t __get_MCAUSE(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "mcause" : "=r" (result) );
return (result);
}
/*********************************************************************
* @fn __set_MEPC
*
* @brief Set the Machine Cause Register
*
* @return mcause value
*/
void __set_MCAUSE(uint32_t value)
{
__ASM volatile ("csrw mcause, %0" : : "r" (value) );
}
/*********************************************************************
* @fn __get_MTVAL
*
* @brief Return the Machine Trap Value Register
*
* @return mtval value
*/
uint32_t __get_MTVAL(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "mtval" : "=r" (result) );
return (result);
}
/*********************************************************************
* @fn __set_MTVAL
*
* @brief Set the Machine Trap Value Register
*
* @return mtval value
*/
void __set_MTVAL(uint32_t value)
{
__ASM volatile ("csrw mtval, %0" : : "r" (value) );
}
/*********************************************************************
* @fn __get_MVENDORID
*
* @brief Return Vendor ID Register
*
* @return mvendorid value
*/
uint32_t __get_MVENDORID(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "mvendorid" : "=r" (result) );
return (result);
}
/*********************************************************************
* @fn __get_MARCHID
*
* @brief Return Machine Architecture ID Register
*
* @return marchid value
*/
uint32_t __get_MARCHID(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "marchid" : "=r" (result) );
return (result);
}
/*********************************************************************
* @fn __get_MIMPID
*
* @brief Return Machine Implementation ID Register
*
* @return mimpid value
*/
uint32_t __get_MIMPID(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "mimpid" : "=r" (result) );
return (result);
}
/*********************************************************************
* @fn __get_MHARTID
*
* @brief Return Hart ID Register
*
* @return mhartid value
*/
uint32_t __get_MHARTID(void)
{
uint32_t result;
__ASM volatile ( "csrr %0," "mhartid" : "=r" (result) );
return (result);
}
/*********************************************************************
* @fn __get_SP
*
* @brief Return SP Register
*
* @return SP value
*/
uint32_t __get_SP(void)
{
uint32_t result;
__ASM volatile ( "mv %0," "sp" : "=r"(result) : );
return (result);
}

589
ch32v203_ir_box/src/core/core_riscv.h Normal file
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/********************************** (C) COPYRIGHT *******************************
* File Name : core_riscv.h
* Author : WCH
* Version : V1.0.1
* Date : 2023/11/11
* Description : RISC-V V4 Core Peripheral Access Layer Header File for CH32V20x
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CORE_RISCV_H__
#define __CORE_RISCV_H__
#ifdef __cplusplus
extern "C" {
#endif
/* IO definitions */
#ifdef __cplusplus
#define __I volatile /* defines 'read only' permissions */
#else
#define __I volatile const /* defines 'read only' permissions */
#endif
#define __O volatile /* defines 'write only' permissions */
#define __IO volatile /* defines 'read / write' permissions */
/* Standard Peripheral Library old types (maintained for legacy purpose) */
typedef __I uint64_t vuc64; /* Read Only */
typedef __I uint32_t vuc32; /* Read Only */
typedef __I uint16_t vuc16; /* Read Only */
typedef __I uint8_t vuc8; /* Read Only */
typedef const uint64_t uc64; /* Read Only */
typedef const uint32_t uc32; /* Read Only */
typedef const uint16_t uc16; /* Read Only */
typedef const uint8_t uc8; /* Read Only */
typedef __I int64_t vsc64; /* Read Only */
typedef __I int32_t vsc32; /* Read Only */
typedef __I int16_t vsc16; /* Read Only */
typedef __I int8_t vsc8; /* Read Only */
typedef const int64_t sc64; /* Read Only */
typedef const int32_t sc32; /* Read Only */
typedef const int16_t sc16; /* Read Only */
typedef const int8_t sc8; /* Read Only */
typedef __IO uint64_t vu64;
typedef __IO uint32_t vu32;
typedef __IO uint16_t vu16;
typedef __IO uint8_t vu8;
typedef uint64_t u64;
typedef uint32_t u32;
typedef uint16_t u16;
typedef uint8_t u8;
typedef __IO int64_t vs64;
typedef __IO int32_t vs32;
typedef __IO int16_t vs16;
typedef __IO int8_t vs8;
typedef int64_t s64;
typedef int32_t s32;
typedef int16_t s16;
typedef int8_t s8;
typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus;
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
#define RV_STATIC_INLINE static inline
/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */
typedef struct{
__I uint32_t ISR[8];
__I uint32_t IPR[8];
__IO uint32_t ITHRESDR;
__IO uint32_t RESERVED;
__IO uint32_t CFGR;
__I uint32_t GISR;
__IO uint8_t VTFIDR[4];
uint8_t RESERVED0[12];
__IO uint32_t VTFADDR[4];
uint8_t RESERVED1[0x90];
__O uint32_t IENR[8];
uint8_t RESERVED2[0x60];
__O uint32_t IRER[8];
uint8_t RESERVED3[0x60];
__O uint32_t IPSR[8];
uint8_t RESERVED4[0x60];
__O uint32_t IPRR[8];
uint8_t RESERVED5[0x60];
__IO uint32_t IACTR[8];
uint8_t RESERVED6[0xE0];
__IO uint8_t IPRIOR[256];
uint8_t RESERVED7[0x810];
__IO uint32_t SCTLR;
}PFIC_Type;
/* memory mapped structure for SysTick */
typedef struct
{
__IO uint32_t CTLR;
__IO uint32_t SR;
__IO uint64_t CNT;
__IO uint64_t CMP;
}SysTick_Type;
#define PFIC ((PFIC_Type *) 0xE000E000 )
#define NVIC PFIC
#define NVIC_KEY1 ((uint32_t)0xFA050000)
#define NVIC_KEY2 ((uint32_t)0xBCAF0000)
#define NVIC_KEY3 ((uint32_t)0xBEEF0000)
#define SysTick ((SysTick_Type *) 0xE000F000)
/*********************************************************************
* @fn __enable_irq
*
* @brief Enable Global Interrupt
*
* @return none
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __enable_irq()
{
__asm volatile ("csrs 0x800, %0" : : "r" (0x88) );
}
/*********************************************************************
* @fn __disable_irq
*
* @brief Disable Global Interrupt
*
* @return none
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __disable_irq()
{
__asm volatile ("csrc 0x800, %0" : : "r" (0x88) );
}
/*********************************************************************
* @fn __NOP
*
* @brief nop
*
* @return none
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __NOP()
{
__asm volatile ("nop");
}
/*********************************************************************
* @fn NVIC_EnableIRQ
*
* @brief Enable Interrupt
*
* @param IRQn - Interrupt Numbers
*
* @return none
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
{
NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/*********************************************************************
* @fn NVIC_DisableIRQ
*
* @brief Disable Interrupt
*
* @param IRQn - Interrupt Numbers
*
* @return none
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
{
NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/*********************************************************************
* @fn NVIC_GetStatusIRQ
*
* @brief Get Interrupt Enable State
*
* @param IRQn - Interrupt Numbers
*
* @return 1 - Interrupt Pending Enable
* 0 - Interrupt Pending Disable
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
/*********************************************************************
* @fn NVIC_GetPendingIRQ
*
* @brief Get Interrupt Pending State
*
* @param IRQn - Interrupt Numbers
*
* @return 1 - Interrupt Pending Enable
* 0 - Interrupt Pending Disable
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
/*********************************************************************
* @fn NVIC_SetPendingIRQ
*
* @brief Set Interrupt Pending
*
* @param IRQn - Interrupt Numbers
*
* @return none
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/*********************************************************************
* @fn NVIC_ClearPendingIRQ
*
* @brief Clear Interrupt Pending
*
* @param IRQn - Interrupt Numbers
*
* @return none
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
}
/*********************************************************************
* @fn NVIC_GetActive
*
* @brief Get Interrupt Active State
*
* @param IRQn - Interrupt Numbers
*
* @return 1 - Interrupt Active
* 0 - Interrupt No Active
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
{
return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
}
/*********************************************************************
* @fn NVIC_SetPriority
*
* @brief Set Interrupt Priority
*
* @param IRQn - Interrupt Numbers
* interrupt nesting enable(CSR-0x804 bit1 = 1)
* priority - bit[7] - Preemption Priority
* bit[6:5] - Sub priority
* bit[4:0] - Reserve
* interrupt nesting disable(CSR-0x804 bit1 = 0)
* priority - bit[7:5] - Sub priority
* bit[4:0] - Reserve
*
* @return none
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority)
{
NVIC->IPRIOR[(uint32_t)(IRQn)] = priority;
}
/*********************************************************************
* @fn __WFI
*
* @brief Wait for Interrupt
*
* @return none
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void)
{
NVIC->SCTLR &= ~(1<<3); // wfi
asm volatile ("wfi");
}
/*********************************************************************
* @fn _SEV
*
* @brief Set Event
*
* @return none
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _SEV(void)
{
NVIC->SCTLR |= (1<<5);
}
/*********************************************************************
* @fn _WFE
*
* @brief Wait for Events
*
* @return none
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _WFE(void)
{
uint32_t tmp= NVIC->SCTLR;
tmp &= ~(1<<5);
tmp |= (1<<3);
NVIC->SCTLR = tmp;
asm volatile ("wfi");
}
/*********************************************************************
* @fn __WFE
*
* @brief Wait for Events
*
* @return none
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void)
{
_SEV();
_WFE();
_WFE();
if(*(vu32*)(0x40023800) & (1<<6))
{
NVIC->SCTLR |= (1<<5);
}
}
/*********************************************************************
* @fn SetVTFIRQ
*
* @brief Set VTF Interrupt
*
* @param addr - VTF interrupt service function base address.
* IRQn - Interrupt Numbers
* num - VTF Interrupt Numbers
* NewState - DISABLE or ENABLE
*
* @return none
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void SetVTFIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num, FunctionalState NewState)
{
if(num > 3) return ;
if (NewState != DISABLE)
{
NVIC->VTFIDR[num] = IRQn;
NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)|0x1);
}
else
{
NVIC->VTFIDR[num] = IRQn;
NVIC->VTFADDR[num] = ((addr&0xFFFFFFFE)&(~0x1));
}
}
/*********************************************************************
* @fn NVIC_SystemReset
*
* @brief Initiate a system reset request
*
* @return none
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SystemReset(void)
{
NVIC->CFGR = NVIC_KEY3|(1<<7);
}
/*********************************************************************
* @fn __AMOADD_W
*
* @brief Atomic Add with 32bit value
* Atomically ADD 32bit value with value in memory using amoadd.d.
*
* @param addr - Address pointer to data, address need to be 4byte aligned
* value - value to be ADDed
*
* @return return memory value + add value
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value)
{
int32_t result;
__asm volatile ("amoadd.w %0, %2, %1" : \
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr;
}
/*********************************************************************
* @fn __AMOAND_W
*
* @brief Atomic And with 32bit value
* Atomically AND 32bit value with value in memory using amoand.d.
*
* @param addr - Address pointer to data, address need to be 4byte aligned
* value - value to be ANDed
*
* @return return memory value & and value
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value)
{
int32_t result;
__asm volatile ("amoand.w %0, %2, %1" : \
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr;
}
/*********************************************************************
* @fn __AMOMAX_W
*
* @brief Atomic signed MAX with 32bit value
* Atomically signed max compare 32bit value with value in memory using amomax.d.
*
* @param addr - Address pointer to data, address need to be 4byte aligned
* value - value to be compared
*
* @return the bigger value
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value)
{
int32_t result;
__asm volatile ("amomax.w %0, %2, %1" : \
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr;
}
/*********************************************************************
* @fn __AMOMAXU_W
*
* @brief Atomic unsigned MAX with 32bit value
* Atomically unsigned max compare 32bit value with value in memory using amomaxu.d.
*
* @param addr - Address pointer to data, address need to be 4byte aligned
* value - value to be compared
*
* @return return the bigger value
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t value)
{
uint32_t result;
__asm volatile ("amomaxu.w %0, %2, %1" : \
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr;
}
/*********************************************************************
* @fn __AMOMIN_W
*
* @brief Atomic signed MIN with 32bit value
* Atomically signed min compare 32bit value with value in memory using amomin.d.
*
* @param addr - Address pointer to data, address need to be 4byte aligned
* value - value to be compared
*
* @return the smaller value
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value)
{
int32_t result;
__asm volatile ("amomin.w %0, %2, %1" : \
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr;
}
/*********************************************************************
* @fn __AMOMINU_W
*
* @brief Atomic unsigned MIN with 32bit value
* Atomically unsigned min compare 32bit value with value in memory using amominu.d.
*
* @param addr - Address pointer to data, address need to be 4byte aligned
* value - value to be compared
*
* @return the smaller value
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value)
{
uint32_t result;
__asm volatile ("amominu.w %0, %2, %1" : \
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr;
}
/*********************************************************************
* @fn __AMOOR_W
*
* @brief Atomic OR with 32bit value
* Atomically OR 32bit value with value in memory using amoor.d.
*
* @param addr - Address pointer to data, address need to be 4byte aligned
* value - value to be ORed
*
* @return return memory value | and value
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value)
{
int32_t result;
__asm volatile ("amoor.w %0, %2, %1" : \
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr;
}
/*********************************************************************
* @fn __AMOSWAP_W
*
* @brief Atomically swap new 32bit value into memory using amoswap.d.
*
* @param addr - Address pointer to data, address need to be 4byte aligned
* newval - New value to be stored into the address
*
* @return return the original value in memory
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval)
{
uint32_t result;
__asm volatile ("amoswap.w %0, %2, %1" : \
"=r"(result), "+A"(*addr) : "r"(newval) : "memory");
return result;
}
/*********************************************************************
* @fn __AMOXOR_W
*
* @brief Atomic XOR with 32bit value
* Atomically XOR 32bit value with value in memory using amoxor.d.
*
* @param addr - Address pointer to data, address need to be 4byte aligned
* value - value to be XORed
*
* @return return memory value ^ and value
*/
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value)
{
int32_t result;
__asm volatile ("amoxor.w %0, %2, %1" : \
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
return *addr;
}
/* Core_Exported_Functions */
extern uint32_t __get_MSTATUS(void);
extern void __set_MSTATUS(uint32_t value);
extern uint32_t __get_MISA(void);
extern void __set_MISA(uint32_t value);
extern uint32_t __get_MTVEC(void);
extern void __set_MTVEC(uint32_t value);
extern uint32_t __get_MSCRATCH(void);
extern void __set_MSCRATCH(uint32_t value);
extern uint32_t __get_MEPC(void);
extern void __set_MEPC(uint32_t value);
extern uint32_t __get_MCAUSE(void);
extern void __set_MCAUSE(uint32_t value);
extern uint32_t __get_MTVAL(void);
extern void __set_MTVAL(uint32_t value);
extern uint32_t __get_MVENDORID(void);
extern uint32_t __get_MARCHID(void);
extern uint32_t __get_MIMPID(void);
extern uint32_t __get_MHARTID(void);
extern uint32_t __get_SP(void);
#ifdef __cplusplus
}
#endif
#endif

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ENTRY( _start ) __stack_size = 2048; PROVIDE( _stack_size = __stack_size ); MEMORY { /* CH32V20x_D6 - CH32V203F6-CH32V203G6-CH32V203C6 */ FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 32K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 10K /* CH32V20x_D6 - CH32V203K8-CH32V203C8-CH32V203G8-CH32V203F8 */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K */ /* CH32V20x_D8 - CH32V203RB CH32V20x_D8W - CH32V208x FLASH + RAM supports the following configuration FLASH-128K + RAM-64K FLASH-144K + RAM-48K FLASH-160K + RAM-32K */ /* FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 160K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 32K */ } SECTIONS { .init : { _sinit = .; . = ALIGN(4); KEEP(*(SORT_NONE(.init))) . = ALIGN(4); _einit = .; } >FLASH AT>FLASH .vector : { *(.vector); . = ALIGN(64); } >FLASH AT>FLASH .text : { . = ALIGN(4); *(.text) *(.text.*) *(.rodata) *(.rodata*) *(.gnu.linkonce.t.*) . = ALIGN(4); } >FLASH AT>FLASH .fini : { KEEP(*(SORT_NONE(.fini))) . = ALIGN(4); } >FLASH AT>FLASH PROVIDE( _etext = . ); PROVIDE( _eitcm = . ); .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH AT>FLASH .init_array : { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH AT>FLASH .fini_array : { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); } >FLASH AT>FLASH .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is first. Because this is a wildcard, it doesn't matter if the user does not actually link against crtbegin.o; the linker won't look for a file to match a wildcard. The wildcard also means that it doesn't matter which directory crtbegin.o is in. */ KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) /* We don't want to include the .ctor section from the crtend.o file until after the sorted ctors. The .ctor section from the crtend file contains the end of ctors marker and it must be last */ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) } >FLASH AT>FLASH .dtors : { KEEP (*crtbegin.o(.dtors)) KEEP (*crtbegin?.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) } >FLASH AT>FLASH .dalign : { . = ALIGN(4); PROVIDE(_data_vma = .); } >RAM AT>FLASH .dlalign : { . = ALIGN(4); PROVIDE(_data_lma = .); } >FLASH AT>FLASH .data : { *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); PROVIDE( __global_pointer$ = . + 0x800 ); *(.sdata .sdata.*) *(.sdata2.*) *(.gnu.linkonce.s.*) . = ALIGN(8); *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) . = ALIGN(4); PROVIDE( _edata = .); } >RAM AT>FLASH .bss : { . = ALIGN(4); PROVIDE( _sbss = .); *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON*) . = ALIGN(4); PROVIDE( _ebss = .); } >RAM AT>FLASH PROVIDE( _end = _ebss); PROVIDE( end = . ); .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : { PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_susrstack = . ); . = . + __stack_size; PROVIDE( _eusrstack = .); } >RAM }

254
ch32v203_ir_box/src/core/startup_ch32v20x_D6.S Normal file
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;/********************************** (C) COPYRIGHT *******************************
;* File Name : startup_ch32v20x_D6.s
;* Author : WCH
;* Version : V1.0.1
;* Date : 2024/01/31
;* Description : CH32V203F6-CH32V203F8-CH32V203G6-CH32V203G8-CH32V203K8-CH32V203C6-CH32V203C8-CH32V203G8
;* vector table for eclipse toolchain.
;*********************************************************************************
;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
;* Attention: This software (modified or not) and binary are used for
;* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
.section .init,"ax",@progbits
.global _start
.align 1
_start:
j handle_reset
.section .vector,"ax",@progbits
.align 1
_vector_base:
.option norvc;
.word _start
.word 0
.word NMI_Handler /* NMI */
.word HardFault_Handler /* Hard Fault */
.word 0
.word Ecall_M_Mode_Handler /* Ecall M Mode */
.word 0
.word 0
.word Ecall_U_Mode_Handler /* Ecall U Mode */
.word Break_Point_Handler /* Break Point */
.word 0
.word 0
.word SysTick_Handler /* SysTick */
.word 0
.word SW_Handler /* SW */
.word 0
/* External Interrupts */
.word WWDG_IRQHandler /* Window Watchdog */
.word PVD_IRQHandler /* PVD through EXTI Line detect */
.word TAMPER_IRQHandler /* TAMPER */
.word RTC_IRQHandler /* RTC */
.word FLASH_IRQHandler /* Flash */
.word RCC_IRQHandler /* RCC */
.word EXTI0_IRQHandler /* EXTI Line 0 */
.word EXTI1_IRQHandler /* EXTI Line 1 */
.word EXTI2_IRQHandler /* EXTI Line 2 */
.word EXTI3_IRQHandler /* EXTI Line 3 */
.word EXTI4_IRQHandler /* EXTI Line 4 */
.word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
.word DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */
.word DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */
.word DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */
.word DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */
.word DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */
.word DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */
.word ADC1_2_IRQHandler /* ADC1_2 */
.word USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */
.word USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
.word CAN1_RX1_IRQHandler /* CAN1 RX1 */
.word CAN1_SCE_IRQHandler /* CAN1 SCE */
.word EXTI9_5_IRQHandler /* EXTI Line 9..5 */
.word TIM1_BRK_IRQHandler /* TIM1 Break */
.word TIM1_UP_IRQHandler /* TIM1 Update */
.word TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
.word TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.word TIM2_IRQHandler /* TIM2 */
.word TIM3_IRQHandler /* TIM3 */
.word TIM4_IRQHandler /* TIM4 */
.word I2C1_EV_IRQHandler /* I2C1 Event */
.word I2C1_ER_IRQHandler /* I2C1 Error */
.word I2C2_EV_IRQHandler /* I2C2 Event */
.word I2C2_ER_IRQHandler /* I2C2 Error */
.word SPI1_IRQHandler /* SPI1 */
.word SPI2_IRQHandler /* SPI2 */
.word USART1_IRQHandler /* USART1 */
.word USART2_IRQHandler /* USART2 */
.word USART3_IRQHandler /* USART3 */
.word EXTI15_10_IRQHandler /* EXTI Line 15..10 */
.word RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */
.word USBWakeUp_IRQHandler /* USB Wake up from suspend */
.word USBFS_IRQHandler /* USBFS Break */
.word USBFSWakeUp_IRQHandler /* USBFS Wake up from suspend */
.word UART4_IRQHandler /* UART4 */
.word DMA1_Channel8_IRQHandler /* DMA1 Channel8 */
.option rvc;
.section .text.vector_handler, "ax", @progbits
.weak NMI_Handler /* NMI */
.weak HardFault_Handler /* Hard Fault */
.weak Ecall_M_Mode_Handler /* Ecall M Mode */
.weak Ecall_U_Mode_Handler /* Ecall U Mode */
.weak Break_Point_Handler /* Break Point */
.weak SysTick_Handler /* SysTick */
.weak SW_Handler /* SW */
.weak WWDG_IRQHandler /* Window Watchdog */
.weak PVD_IRQHandler /* PVD through EXTI Line detect */
.weak TAMPER_IRQHandler /* TAMPER */
.weak RTC_IRQHandler /* RTC */
.weak FLASH_IRQHandler /* Flash */
.weak RCC_IRQHandler /* RCC */
.weak EXTI0_IRQHandler /* EXTI Line 0 */
.weak EXTI1_IRQHandler /* EXTI Line 1 */
.weak EXTI2_IRQHandler /* EXTI Line 2 */
.weak EXTI3_IRQHandler /* EXTI Line 3 */
.weak EXTI4_IRQHandler /* EXTI Line 4 */
.weak DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
.weak DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */
.weak DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */
.weak DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */
.weak DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */
.weak DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */
.weak DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */
.weak ADC1_2_IRQHandler /* ADC1_2 */
.weak USB_HP_CAN1_TX_IRQHandler /* USB HP and CAN1 TX */
.weak USB_LP_CAN1_RX0_IRQHandler /* USB LP and CAN1RX0 */
.weak CAN1_RX1_IRQHandler /* CAN1 RX1 */
.weak CAN1_SCE_IRQHandler /* CAN1 SCE */
.weak EXTI9_5_IRQHandler /* EXTI Line 9..5 */
.weak TIM1_BRK_IRQHandler /* TIM1 Break */
.weak TIM1_UP_IRQHandler /* TIM1 Update */
.weak TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
.weak TIM1_CC_IRQHandler /* TIM1 Capture Compare */
.weak TIM2_IRQHandler /* TIM2 */
.weak TIM3_IRQHandler /* TIM3 */
.weak TIM4_IRQHandler /* TIM4 */
.weak I2C1_EV_IRQHandler /* I2C1 Event */
.weak I2C1_ER_IRQHandler /* I2C1 Error */
.weak I2C2_EV_IRQHandler /* I2C2 Event */
.weak I2C2_ER_IRQHandler /* I2C2 Error */
.weak SPI1_IRQHandler /* SPI1 */
.weak SPI2_IRQHandler /* SPI2 */
.weak USART1_IRQHandler /* USART1 */
.weak USART2_IRQHandler /* USART2 */
.weak USART3_IRQHandler /* USART3 */
.weak EXTI15_10_IRQHandler /* EXTI Line 15..10 */
.weak RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */
.weak USBWakeUp_IRQHandler /* USB Wakeup from suspend */
.weak USBFS_IRQHandler /* USBFS */
.weak USBFSWakeUp_IRQHandler /* USBFS Wake Up */
.weak UART4_IRQHandler /* UART4 */
.weak DMA1_Channel8_IRQHandler /* DMA1 Channel8 */
NMI_Handler:
HardFault_Handler:
Ecall_M_Mode_Handler:
Ecall_U_Mode_Handler:
Break_Point_Handler:
SysTick_Handler:
SW_Handler:
WWDG_IRQHandler:
PVD_IRQHandler:
TAMPER_IRQHandler:
RTC_IRQHandler:
FLASH_IRQHandler:
RCC_IRQHandler:
EXTI0_IRQHandler:
EXTI1_IRQHandler:
EXTI2_IRQHandler:
EXTI3_IRQHandler:
EXTI4_IRQHandler:
DMA1_Channel1_IRQHandler:
DMA1_Channel2_IRQHandler:
DMA1_Channel3_IRQHandler:
DMA1_Channel4_IRQHandler:
DMA1_Channel5_IRQHandler:
DMA1_Channel6_IRQHandler:
DMA1_Channel7_IRQHandler:
ADC1_2_IRQHandler:
USB_HP_CAN1_TX_IRQHandler:
USB_LP_CAN1_RX0_IRQHandler:
CAN1_RX1_IRQHandler:
CAN1_SCE_IRQHandler:
EXTI9_5_IRQHandler:
TIM1_BRK_IRQHandler:
TIM1_UP_IRQHandler:
TIM1_TRG_COM_IRQHandler:
TIM1_CC_IRQHandler:
TIM2_IRQHandler:
TIM3_IRQHandler:
TIM4_IRQHandler:
I2C1_EV_IRQHandler:
I2C1_ER_IRQHandler:
I2C2_EV_IRQHandler:
I2C2_ER_IRQHandler:
SPI1_IRQHandler:
SPI2_IRQHandler:
USART1_IRQHandler:
USART2_IRQHandler:
USART3_IRQHandler:
EXTI15_10_IRQHandler:
RTCAlarm_IRQHandler:
USBWakeUp_IRQHandler:
USBFS_IRQHandler:
USBFSWakeUp_IRQHandler:
UART4_IRQHandler:
DMA1_Channel8_IRQHandler:
1:
j 1b
.section .text.handle_reset,"ax",@progbits
.weak handle_reset
.align 1
handle_reset:
.option push
.option norelax
la gp, __global_pointer$
.option pop
1:
la sp, _eusrstack
2:
/* Load data section from flash to RAM */
la a0, _data_lma
la a1, _data_vma
la a2, _edata
bgeu a1, a2, 2f
1:
lw t0, (a0)
sw t0, (a1)
addi a0, a0, 4
addi a1, a1, 4
bltu a1, a2, 1b
2:
/* Clear bss section */
la a0, _sbss
la a1, _ebss
bgeu a0, a1, 2f
1:
sw zero, (a0)
addi a0, a0, 4
bltu a0, a1, 1b
2:
/* Configure pipelining and instruction prediction */
li t0, 0x1f
csrw 0xbc0, t0
/* Enable interrupt nesting and hardware stack */
li t0, 0x3
csrw 0x804, t0
/* Enable global interrupt and configure privileged mode */
li t0, 0x88
csrw mstatus, t0
/* Configure the interrupt vector table recognition mode and entry address mode */
la t0, _vector_base
ori t0, t0, 3
csrw mtvec, t0
jal SystemInit
la t0, main
csrw mepc, t0
mret

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ch32v203_ir_box/src/periph/ch32v20x_adc.c Normal file
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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_adc.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* ADC firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_ADC_H
#define __CH32V20x_ADC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v20x.h"
/* ADC Init structure definition */
typedef struct
{
uint32_t ADC_Mode; /* Configures the ADC to operate in independent or
dual mode.
This parameter can be a value of @ref ADC_mode */
FunctionalState ADC_ScanConvMode; /* Specifies whether the conversion is performed in
Scan (multichannels) or Single (one channel) mode.
This parameter can be set to ENABLE or DISABLE */
FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in
Continuous or Single mode.
This parameter can be set to ENABLE or DISABLE. */
uint32_t ADC_ExternalTrigConv; /* Defines the external trigger used to start the analog
to digital conversion of regular channels. This parameter
can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */
uint32_t ADC_DataAlign; /* Specifies whether the ADC data alignment is left or right.
This parameter can be a value of @ref ADC_data_align */
uint8_t ADC_NbrOfChannel; /* Specifies the number of ADC channels that will be converted
using the sequencer for regular channel group.
This parameter must range from 1 to 16. */
uint32_t ADC_OutputBuffer; /* Specifies whether the ADC channel output buffer is enabled or disabled.
This parameter can be a value of @ref ADC_OutputBuffer */
uint32_t ADC_Pga; /* Specifies the PGA gain multiple.
This parameter can be a value of @ref ADC_Pga */
} ADC_InitTypeDef;
/* ADC_mode */
#define ADC_Mode_Independent ((uint32_t)0x00000000)
#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000)
#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000)
#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000)
#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000)
#define ADC_Mode_InjecSimult ((uint32_t)0x00050000)
#define ADC_Mode_RegSimult ((uint32_t)0x00060000)
#define ADC_Mode_FastInterl ((uint32_t)0x00070000)
#define ADC_Mode_SlowInterl ((uint32_t)0x00080000)
#define ADC_Mode_AlterTrig ((uint32_t)0x00090000)
/* ADC_external_trigger_sources_for_regular_channels_conversion */
#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000)
#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000)
#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000)
#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000)
#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000)
#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000)
#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000)
#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000)
#define ADC_ExternalTrigConv_T3_CC1 ((uint32_t)0x00000000)
#define ADC_ExternalTrigConv_T2_CC3 ((uint32_t)0x00020000)
#define ADC_ExternalTrigConv_T8_CC1 ((uint32_t)0x00060000)
#define ADC_ExternalTrigConv_T8_TRGO ((uint32_t)0x00080000)
#define ADC_ExternalTrigConv_T5_CC1 ((uint32_t)0x000A0000)
#define ADC_ExternalTrigConv_T5_CC3 ((uint32_t)0x000C0000)
/* ADC_data_align */
#define ADC_DataAlign_Right ((uint32_t)0x00000000)
#define ADC_DataAlign_Left ((uint32_t)0x00000800)
/* ADC_channels */
#define ADC_Channel_0 ((uint8_t)0x00)
#define ADC_Channel_1 ((uint8_t)0x01)
#define ADC_Channel_2 ((uint8_t)0x02)
#define ADC_Channel_3 ((uint8_t)0x03)
#define ADC_Channel_4 ((uint8_t)0x04)
#define ADC_Channel_5 ((uint8_t)0x05)
#define ADC_Channel_6 ((uint8_t)0x06)
#define ADC_Channel_7 ((uint8_t)0x07)
#define ADC_Channel_8 ((uint8_t)0x08)
#define ADC_Channel_9 ((uint8_t)0x09)
#define ADC_Channel_10 ((uint8_t)0x0A)
#define ADC_Channel_11 ((uint8_t)0x0B)
#define ADC_Channel_12 ((uint8_t)0x0C)
#define ADC_Channel_13 ((uint8_t)0x0D)
#define ADC_Channel_14 ((uint8_t)0x0E)
#define ADC_Channel_15 ((uint8_t)0x0F)
#define ADC_Channel_16 ((uint8_t)0x10)
#define ADC_Channel_17 ((uint8_t)0x11)
#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16)
#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17)
/*ADC_output_buffer*/
#define ADC_OutputBuffer_Enable ((uint32_t)0x04000000)
#define ADC_OutputBuffer_Disable ((uint32_t)0x00000000)
/*ADC_pga*/
#define ADC_Pga_1 ((uint32_t)0x00000000)
#define ADC_Pga_4 ((uint32_t)0x08000000)
#define ADC_Pga_16 ((uint32_t)0x10000000)
#define ADC_Pga_64 ((uint32_t)0x18000000)
/* ADC_sampling_time */
#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00)
#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01)
#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02)
#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03)
#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04)
#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05)
#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06)
#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07)
/* ADC_external_trigger_sources_for_injected_channels_conversion */
#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000)
#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000)
#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000)
#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000)
#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000)
#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000)
#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000)
#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000)
#define ADC_ExternalTrigInjecConv_T4_CC3 ((uint32_t)0x00002000)
#define ADC_ExternalTrigInjecConv_T8_CC2 ((uint32_t)0x00003000)
#define ADC_ExternalTrigInjecConv_T8_CC4 ((uint32_t)0x00004000)
#define ADC_ExternalTrigInjecConv_T5_TRGO ((uint32_t)0x00005000)
#define ADC_ExternalTrigInjecConv_T5_CC4 ((uint32_t)0x00006000)
/* ADC_injected_channel_selection */
#define ADC_InjectedChannel_1 ((uint8_t)0x14)
#define ADC_InjectedChannel_2 ((uint8_t)0x18)
#define ADC_InjectedChannel_3 ((uint8_t)0x1C)
#define ADC_InjectedChannel_4 ((uint8_t)0x20)
/* ADC_analog_watchdog_selection */
#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200)
#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200)
#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200)
#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000)
#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000)
#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000)
#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000)
/* ADC_interrupts_definition */
#define ADC_IT_EOC ((uint16_t)0x0220)
#define ADC_IT_AWD ((uint16_t)0x0140)
#define ADC_IT_JEOC ((uint16_t)0x0480)
/* ADC_flags_definition */
#define ADC_FLAG_AWD ((uint8_t)0x01)
#define ADC_FLAG_EOC ((uint8_t)0x02)
#define ADC_FLAG_JEOC ((uint8_t)0x04)
#define ADC_FLAG_JSTRT ((uint8_t)0x08)
#define ADC_FLAG_STRT ((uint8_t)0x10)
void ADC_DeInit(ADC_TypeDef *ADCx);
void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct);
void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct);
void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState);
void ADC_ResetCalibration(ADC_TypeDef *ADCx);
FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx);
void ADC_StartCalibration(ADC_TypeDef *ADCx);
FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx);
void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx);
void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number);
void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx);
uint32_t ADC_GetDualModeConversionValue(void);
void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv);
void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx);
void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length);
void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel);
void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog);
void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold);
void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel);
void ADC_TempSensorVrefintCmd(FunctionalState NewState);
FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG);
void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG);
ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT);
void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT);
s32 TempSensor_Volt_To_Temper(s32 Value);
void ADC_BufferCmd(ADC_TypeDef *ADCx, FunctionalState NewState);
int16_t Get_CalibrationValue(ADC_TypeDef *ADCx);
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_dma.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file provides all the DMA firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include "ch32v20x_dma.h"
#include "ch32v20x_rcc.h"
/* DMA1 Channelx interrupt pending bit masks */
#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1))
#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2))
#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3))
#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4))
#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5))
#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6))
#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7))
#define DMA1_Channel8_IT_Mask ((uint32_t)(DMA_GIF8 | DMA_TCIF8 | DMA_HTIF8 | DMA_TEIF8))
/* DMA2 FLAG mask */
#define FLAG_Mask ((uint32_t)0x10000000)
/* DMA registers Masks */
#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F)
/*********************************************************************
* @fn DMA_DeInit
*
* @brief Deinitializes the DMAy Channelx registers to their default
* reset values.
*
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
*
* @return none
*/
void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx)
{
DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN);
DMAy_Channelx->CFGR = 0;
DMAy_Channelx->CNTR = 0;
DMAy_Channelx->PADDR = 0;
DMAy_Channelx->MADDR = 0;
if(DMAy_Channelx == DMA1_Channel1)
{
DMA1->INTFCR |= DMA1_Channel1_IT_Mask;
}
else if(DMAy_Channelx == DMA1_Channel2)
{
DMA1->INTFCR |= DMA1_Channel2_IT_Mask;
}
else if(DMAy_Channelx == DMA1_Channel3)
{
DMA1->INTFCR |= DMA1_Channel3_IT_Mask;
}
else if(DMAy_Channelx == DMA1_Channel4)
{
DMA1->INTFCR |= DMA1_Channel4_IT_Mask;
}
else if(DMAy_Channelx == DMA1_Channel5)
{
DMA1->INTFCR |= DMA1_Channel5_IT_Mask;
}
else if(DMAy_Channelx == DMA1_Channel6)
{
DMA1->INTFCR |= DMA1_Channel6_IT_Mask;
}
else if(DMAy_Channelx == DMA1_Channel7)
{
DMA1->INTFCR |= DMA1_Channel7_IT_Mask;
}
else if(DMAy_Channelx == DMA1_Channel8)
{
DMA1->INTFCR |= DMA1_Channel8_IT_Mask;
}
}
/*********************************************************************
* @fn DMA_Init
*
* @brief Initializes the DMAy Channelx according to the specified
* parameters in the DMA_InitStruct.
*
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
* DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains
* contains the configuration information for the specified DMA Channel.
*
* @return none
*/
void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct)
{
uint32_t tmpreg = 0;
tmpreg = DMAy_Channelx->CFGR;
tmpreg &= CFGR_CLEAR_Mask;
tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
DMAy_Channelx->CFGR = tmpreg;
DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize;
DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr;
DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr;
}
/*********************************************************************
* @fn DMA_StructInit
*
* @brief Fills each DMA_InitStruct member with its default value.
*
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
* DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains
* contains the configuration information for the specified DMA Channel.
*
* @return none
*/
void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct)
{
DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
DMA_InitStruct->DMA_MemoryBaseAddr = 0;
DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
DMA_InitStruct->DMA_BufferSize = 0;
DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
}
/*********************************************************************
* @fn DMA_Cmd
*
* @brief Enables or disables the specified DMAy Channelx.
*
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
* NewState - new state of the DMAy Channelx(ENABLE or DISABLE).
*
* @return none
*/
void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
DMAy_Channelx->CFGR |= DMA_CFGR1_EN;
}
else
{
DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN);
}
}
/*********************************************************************
* @fn DMA_ITConfig
*
* @brief Enables or disables the specified DMAy Channelx interrupts.
*
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
* DMA_IT - specifies the DMA interrupts sources to be enabled
* or disabled.
* DMA_IT_TC - Transfer complete interrupt mask
* DMA_IT_HT - Half transfer interrupt mask
* DMA_IT_TE - Transfer error interrupt mask
* NewState - new state of the DMAy Channelx(ENABLE or DISABLE).
*
* @return none
*/
void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
{
if(NewState != DISABLE)
{
DMAy_Channelx->CFGR |= DMA_IT;
}
else
{
DMAy_Channelx->CFGR &= ~DMA_IT;
}
}
/*********************************************************************
* @fn DMA_SetCurrDataCounter
*
* @brief Sets the number of data units in the current DMAy Channelx transfer.
*
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
* DataNumber - The number of data units in the current DMAy Channelx
* transfer.
*
* @return none
*/
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber)
{
DMAy_Channelx->CNTR = DataNumber;
}
/*********************************************************************
* @fn DMA_GetCurrDataCounter
*
* @brief Returns the number of remaining data units in the current
* DMAy Channelx transfer.
*
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
* 1 to 7 for DMA1 and 1 to 11 for DMA2 to select the DMA Channel.
*
* @return DataNumber - The number of remaining data units in the current
* DMAy Channelx transfer.
*/
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx)
{
return ((uint16_t)(DMAy_Channelx->CNTR));
}
/*********************************************************************
* @fn DMA_GetFlagStatus
*
* @brief Checks whether the specified DMAy Channelx flag is set or not.
*
* @param DMAy_FLAG - specifies the flag to check.
* DMA1_FLAG_GL1 - DMA1 Channel1 global flag.
* DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag.
* DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag.
* DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag.
* DMA1_FLAG_GL2 - DMA1 Channel2 global flag.
* DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag.
* DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag.
* DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag.
* DMA1_FLAG_GL3 - DMA1 Channel3 global flag.
* DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag.
* DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag.
* DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag.
* DMA1_FLAG_GL4 - DMA1 Channel4 global flag.
* DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag.
* DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag.
* DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag.
* DMA1_FLAG_GL5 - DMA1 Channel5 global flag.
* DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag.
* DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag.
* DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag.
* DMA1_FLAG_GL6 - DMA1 Channel6 global flag.
* DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag.
* DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag.
* DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag.
* DMA1_FLAG_GL7 - DMA1 Channel7 global flag.
* DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag.
* DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag.
* DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag.
* DMA2_FLAG_GL1 - DMA2 Channel1 global flag.
* DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag.
* DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag.
* DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag.
* @return The new state of DMAy_FLAG (SET or RESET).
*/
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
{
FlagStatus bitstatus = RESET;
uint32_t tmpreg = 0;
tmpreg = DMA1->INTFR;
if((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn DMA_ClearFlag
*
* @brief Clears the DMAy Channelx's pending flags.
*
* @param DMAy_FLAG - specifies the flag to check.
* DMA1_FLAG_GL1 - DMA1 Channel1 global flag.
* DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag.
* DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag.
* DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag.
* DMA1_FLAG_GL2 - DMA1 Channel2 global flag.
* DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag.
* DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag.
* DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag.
* DMA1_FLAG_GL3 - DMA1 Channel3 global flag.
* DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag.
* DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag.
* DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag.
* DMA1_FLAG_GL4 - DMA1 Channel4 global flag.
* DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag.
* DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag.
* DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag.
* DMA1_FLAG_GL5 - DMA1 Channel5 global flag.
* DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag.
* DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag.
* DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag.
* DMA1_FLAG_GL6 - DMA1 Channel6 global flag.
* DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag.
* DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag.
* DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag.
* DMA1_FLAG_GL7 - DMA1 Channel7 global flag.
* DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag.
* DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag.
* DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag.
* DMA2_FLAG_GL1 - DMA2 Channel1 global flag.
* DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag.
* DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag.
* DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag.
* @return none
*/
void DMA_ClearFlag(uint32_t DMAy_FLAG)
{
DMA1->INTFCR = DMAy_FLAG;
}
/*********************************************************************
* @fn DMA_GetITStatus
*
* @brief Checks whether the specified DMAy Channelx interrupt has
* occurred or not.
*
* @param DMAy_IT - specifies the DMAy interrupt source to check.
* DMA1_IT_GL1 - DMA1 Channel1 global flag.
* DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag.
* DMA1_IT_HT1 - DMA1 Channel1 half transfer flag.
* DMA1_IT_TE1 - DMA1 Channel1 transfer error flag.
* DMA1_IT_GL2 - DMA1 Channel2 global flag.
* DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag.
* DMA1_IT_HT2 - DMA1 Channel2 half transfer flag.
* DMA1_IT_TE2 - DMA1 Channel2 transfer error flag.
* DMA1_IT_GL3 - DMA1 Channel3 global flag.
* DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag.
* DMA1_IT_HT3 - DMA1 Channel3 half transfer flag.
* DMA1_IT_TE3 - DMA1 Channel3 transfer error flag.
* DMA1_IT_GL4 - DMA1 Channel4 global flag.
* DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag.
* DMA1_IT_HT4 - DMA1 Channel4 half transfer flag.
* DMA1_IT_TE4 - DMA1 Channel4 transfer error flag.
* DMA1_IT_GL5 - DMA1 Channel5 global flag.
* DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag.
* DMA1_IT_HT5 - DMA1 Channel5 half transfer flag.
* DMA1_IT_TE5 - DMA1 Channel5 transfer error flag.
* DMA1_IT_GL6 - DMA1 Channel6 global flag.
* DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag.
* DMA1_IT_HT6 - DMA1 Channel6 half transfer flag.
* DMA1_IT_TE6 - DMA1 Channel6 transfer error flag.
* DMA1_IT_GL7 - DMA1 Channel7 global flag.
* DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag.
* DMA1_IT_HT7 - DMA1 Channel7 half transfer flag.
* DMA1_IT_TE7 - DMA1 Channel7 transfer error flag.
* DMA2_IT_GL1 - DMA2 Channel1 global flag.
* DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag.
* DMA2_IT_HT1 - DMA2 Channel1 half transfer flag.
* DMA2_IT_TE1 - DMA2 Channel1 transfer error flag.
* @return The new state of DMAy_IT (SET or RESET).
*/
ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
{
ITStatus bitstatus = RESET;
uint32_t tmpreg = 0;
tmpreg = DMA1->INTFR;
if((tmpreg & DMAy_IT) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn DMA_ClearITPendingBit
*
* @brief Clears the DMAy Channelx's interrupt pending bits.
*
* @param DMAy_IT - specifies the DMAy interrupt source to check.
* DMA1_IT_GL1 - DMA1 Channel1 global flag.
* DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag.
* DMA1_IT_HT1 - DMA1 Channel1 half transfer flag.
* DMA1_IT_TE1 - DMA1 Channel1 transfer error flag.
* DMA1_IT_GL2 - DMA1 Channel2 global flag.
* DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag.
* DMA1_IT_HT2 - DMA1 Channel2 half transfer flag.
* DMA1_IT_TE2 - DMA1 Channel2 transfer error flag.
* DMA1_IT_GL3 - DMA1 Channel3 global flag.
* DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag.
* DMA1_IT_HT3 - DMA1 Channel3 half transfer flag.
* DMA1_IT_TE3 - DMA1 Channel3 transfer error flag.
* DMA1_IT_GL4 - DMA1 Channel4 global flag.
* DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag.
* DMA1_IT_HT4 - DMA1 Channel4 half transfer flag.
* DMA1_IT_TE4 - DMA1 Channel4 transfer error flag.
* DMA1_IT_GL5 - DMA1 Channel5 global flag.
* DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag.
* DMA1_IT_HT5 - DMA1 Channel5 half transfer flag.
* DMA1_IT_TE5 - DMA1 Channel5 transfer error flag.
* DMA1_IT_GL6 - DMA1 Channel6 global flag.
* DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag.
* DMA1_IT_HT6 - DMA1 Channel6 half transfer flag.
* DMA1_IT_TE6 - DMA1 Channel6 transfer error flag.
* DMA1_IT_GL7 - DMA1 Channel7 global flag.
* DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag.
* DMA1_IT_HT7 - DMA1 Channel7 half transfer flag.
* DMA1_IT_TE7 - DMA1 Channel7 transfer error flag.
* DMA2_IT_GL1 - DMA2 Channel1 global flag.
* DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag.
* DMA2_IT_HT1 - DMA2 Channel1 half transfer flag.
* DMA2_IT_TE1 - DMA2 Channel1 transfer error flag.
* @return none
*/
void DMA_ClearITPendingBit(uint32_t DMAy_IT)
{
DMA1->INTFCR = DMAy_IT;
}

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_dma.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* DMA firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_DMA_H
#define __CH32V20x_DMA_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v20x.h"
/* DMA Init structure definition */
typedef struct
{
uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */
uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */
uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination.
This parameter can be a value of @ref DMA_data_transfer_direction */
uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel.
The data unit is equal to the configuration set in DMA_PeripheralDataSize
or DMA_MemoryDataSize members depending in the transfer direction. */
uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not.
This parameter can be a value of @ref DMA_peripheral_incremented_mode */
uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not.
This parameter can be a value of @ref DMA_memory_incremented_mode */
uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width.
This parameter can be a value of @ref DMA_peripheral_data_size */
uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width.
This parameter can be a value of @ref DMA_memory_data_size */
uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx.
This parameter can be a value of @ref DMA_circular_normal_mode.
@note: The circular buffer mode cannot be used if the memory-to-memory
data transfer is configured on the selected Channel */
uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx.
This parameter can be a value of @ref DMA_priority_level */
uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
This parameter can be a value of @ref DMA_memory_to_memory */
} DMA_InitTypeDef;
/* DMA_data_transfer_direction */
#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
/* DMA_peripheral_incremented_mode */
#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
/* DMA_memory_incremented_mode */
#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
/* DMA_peripheral_data_size */
#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
/* DMA_memory_data_size */
#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
/* DMA_circular_normal_mode */
#define DMA_Mode_Circular ((uint32_t)0x00000020)
#define DMA_Mode_Normal ((uint32_t)0x00000000)
/* DMA_priority_level */
#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
#define DMA_Priority_High ((uint32_t)0x00002000)
#define DMA_Priority_Medium ((uint32_t)0x00001000)
#define DMA_Priority_Low ((uint32_t)0x00000000)
/* DMA_memory_to_memory */
#define DMA_M2M_Enable ((uint32_t)0x00004000)
#define DMA_M2M_Disable ((uint32_t)0x00000000)
/* DMA_interrupts_definition */
#define DMA_IT_TC ((uint32_t)0x00000002)
#define DMA_IT_HT ((uint32_t)0x00000004)
#define DMA_IT_TE ((uint32_t)0x00000008)
#define DMA1_IT_GL1 ((uint32_t)0x00000001)
#define DMA1_IT_TC1 ((uint32_t)0x00000002)
#define DMA1_IT_HT1 ((uint32_t)0x00000004)
#define DMA1_IT_TE1 ((uint32_t)0x00000008)
#define DMA1_IT_GL2 ((uint32_t)0x00000010)
#define DMA1_IT_TC2 ((uint32_t)0x00000020)
#define DMA1_IT_HT2 ((uint32_t)0x00000040)
#define DMA1_IT_TE2 ((uint32_t)0x00000080)
#define DMA1_IT_GL3 ((uint32_t)0x00000100)
#define DMA1_IT_TC3 ((uint32_t)0x00000200)
#define DMA1_IT_HT3 ((uint32_t)0x00000400)
#define DMA1_IT_TE3 ((uint32_t)0x00000800)
#define DMA1_IT_GL4 ((uint32_t)0x00001000)
#define DMA1_IT_TC4 ((uint32_t)0x00002000)
#define DMA1_IT_HT4 ((uint32_t)0x00004000)
#define DMA1_IT_TE4 ((uint32_t)0x00008000)
#define DMA1_IT_GL5 ((uint32_t)0x00010000)
#define DMA1_IT_TC5 ((uint32_t)0x00020000)
#define DMA1_IT_HT5 ((uint32_t)0x00040000)
#define DMA1_IT_TE5 ((uint32_t)0x00080000)
#define DMA1_IT_GL6 ((uint32_t)0x00100000)
#define DMA1_IT_TC6 ((uint32_t)0x00200000)
#define DMA1_IT_HT6 ((uint32_t)0x00400000)
#define DMA1_IT_TE6 ((uint32_t)0x00800000)
#define DMA1_IT_GL7 ((uint32_t)0x01000000)
#define DMA1_IT_TC7 ((uint32_t)0x02000000)
#define DMA1_IT_HT7 ((uint32_t)0x04000000)
#define DMA1_IT_TE7 ((uint32_t)0x08000000)
#define DMA1_IT_GL8 ((uint32_t)0x10000000)
#define DMA1_IT_TC8 ((uint32_t)0x20000000)
#define DMA1_IT_HT8 ((uint32_t)0x40000000)
#define DMA1_IT_TE8 ((uint32_t)0x80000000)
/* DMA_flags_definition */
#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
#define DMA1_FLAG_GL8 ((uint32_t)0x10000000)
#define DMA1_FLAG_TC8 ((uint32_t)0x20000000)
#define DMA1_FLAG_HT8 ((uint32_t)0x40000000)
#define DMA1_FLAG_TE8 ((uint32_t)0x80000000)
void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx);
void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct);
void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct);
void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState);
void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber);
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx);
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
void DMA_ClearFlag(uint32_t DMAy_FLAG);
ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
void DMA_ClearITPendingBit(uint32_t DMAy_IT);
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_exti.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file provides all the EXTI firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include "ch32v20x_exti.h"
/* No interrupt selected */
#define EXTI_LINENONE ((uint32_t)0x00000)
/*********************************************************************
* @fn EXTI_DeInit
*
* @brief Deinitializes the EXTI peripheral registers to their default
* reset values.
*
* @return none.
*/
void EXTI_DeInit(void)
{
EXTI->INTENR = 0x00000000;
EXTI->EVENR = 0x00000000;
EXTI->RTENR = 0x00000000;
EXTI->FTENR = 0x00000000;
EXTI->INTFR = 0x000FFFFF;
}
/*********************************************************************
* @fn EXTI_Init
*
* @brief Initializes the EXTI peripheral according to the specified
* parameters in the EXTI_InitStruct.
*
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
*
* @return none.
*/
void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct)
{
uint32_t tmp = 0;
tmp = (uint32_t)EXTI_BASE;
if(EXTI_InitStruct->EXTI_LineCmd != DISABLE)
{
EXTI->INTENR &= ~EXTI_InitStruct->EXTI_Line;
EXTI->EVENR &= ~EXTI_InitStruct->EXTI_Line;
tmp += EXTI_InitStruct->EXTI_Mode;
*(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line;
EXTI->RTENR &= ~EXTI_InitStruct->EXTI_Line;
EXTI->FTENR &= ~EXTI_InitStruct->EXTI_Line;
if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
{
EXTI->RTENR |= EXTI_InitStruct->EXTI_Line;
EXTI->FTENR |= EXTI_InitStruct->EXTI_Line;
}
else
{
tmp = (uint32_t)EXTI_BASE;
tmp += EXTI_InitStruct->EXTI_Trigger;
*(__IO uint32_t *)tmp |= EXTI_InitStruct->EXTI_Line;
}
}
else
{
tmp += EXTI_InitStruct->EXTI_Mode;
*(__IO uint32_t *)tmp &= ~EXTI_InitStruct->EXTI_Line;
}
}
/*********************************************************************
* @fn EXTI_StructInit
*
* @brief Fills each EXTI_InitStruct member with its reset value.
*
* @param EXTI_InitStruct - pointer to a EXTI_InitTypeDef structure
*
* @return none.
*/
void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct)
{
EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
EXTI_InitStruct->EXTI_LineCmd = DISABLE;
}
/*********************************************************************
* @fn EXTI_GenerateSWInterrupt
*
* @brief Generates a Software interrupt.
*
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
*
* @return none.
*/
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
{
EXTI->SWIEVR |= EXTI_Line;
}
/*********************************************************************
* @fn EXTI_GetFlagStatus
*
* @brief Checks whether the specified EXTI line flag is set or not.
*
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
*
* @return The new state of EXTI_Line (SET or RESET).
*/
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
{
FlagStatus bitstatus = RESET;
if((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn EXTI_ClearFlag
*
* @brief Clears the EXTI's line pending flags.
*
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
*
* @return None
*/
void EXTI_ClearFlag(uint32_t EXTI_Line)
{
EXTI->INTFR = EXTI_Line;
}
/*********************************************************************
* @fn EXTI_GetITStatus
*
* @brief Checks whether the specified EXTI line is asserted or not.
*
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
*
* @return The new state of EXTI_Line (SET or RESET).
*/
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
{
ITStatus bitstatus = RESET;
uint32_t enablestatus = 0;
enablestatus = EXTI->INTENR & EXTI_Line;
if(((EXTI->INTFR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn EXTI_ClearITPendingBit
*
* @brief Clears the EXTI's line pending bits.
*
* @param EXTI_Line - specifies the EXTI lines to be enabled or disabled.
*
* @return none
*/
void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
{
EXTI->INTFR = EXTI_Line;
}

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_exti.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* EXTI firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_EXTI_H
#define __CH32V20x_EXTI_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v20x.h"
/* EXTI mode enumeration */
typedef enum
{
EXTI_Mode_Interrupt = 0x00,
EXTI_Mode_Event = 0x04
} EXTIMode_TypeDef;
/* EXTI Trigger enumeration */
typedef enum
{
EXTI_Trigger_Rising = 0x08,
EXTI_Trigger_Falling = 0x0C,
EXTI_Trigger_Rising_Falling = 0x10
} EXTITrigger_TypeDef;
/* EXTI Init Structure definition */
typedef struct
{
uint32_t EXTI_Line; /* Specifies the EXTI lines to be enabled or disabled.
This parameter can be any combination of @ref EXTI_Lines */
EXTIMode_TypeDef EXTI_Mode; /* Specifies the mode for the EXTI lines.
This parameter can be a value of @ref EXTIMode_TypeDef */
EXTITrigger_TypeDef EXTI_Trigger; /* Specifies the trigger signal active edge for the EXTI lines.
This parameter can be a value of @ref EXTIMode_TypeDef */
FunctionalState EXTI_LineCmd; /* Specifies the new state of the selected EXTI lines.
This parameter can be set either to ENABLE or DISABLE */
} EXTI_InitTypeDef;
/* EXTI_Lines */
#define EXTI_Line0 ((uint32_t)0x00001) /* External interrupt line 0 */
#define EXTI_Line1 ((uint32_t)0x00002) /* External interrupt line 1 */
#define EXTI_Line2 ((uint32_t)0x00004) /* External interrupt line 2 */
#define EXTI_Line3 ((uint32_t)0x00008) /* External interrupt line 3 */
#define EXTI_Line4 ((uint32_t)0x00010) /* External interrupt line 4 */
#define EXTI_Line5 ((uint32_t)0x00020) /* External interrupt line 5 */
#define EXTI_Line6 ((uint32_t)0x00040) /* External interrupt line 6 */
#define EXTI_Line7 ((uint32_t)0x00080) /* External interrupt line 7 */
#define EXTI_Line8 ((uint32_t)0x00100) /* External interrupt line 8 */
#define EXTI_Line9 ((uint32_t)0x00200) /* External interrupt line 9 */
#define EXTI_Line10 ((uint32_t)0x00400) /* External interrupt line 10 */
#define EXTI_Line11 ((uint32_t)0x00800) /* External interrupt line 11 */
#define EXTI_Line12 ((uint32_t)0x01000) /* External interrupt line 12 */
#define EXTI_Line13 ((uint32_t)0x02000) /* External interrupt line 13 */
#define EXTI_Line14 ((uint32_t)0x04000) /* External interrupt line 14 */
#define EXTI_Line15 ((uint32_t)0x08000) /* External interrupt line 15 */
#define EXTI_Line16 ((uint32_t)0x10000) /* External interrupt line 16 Connected to the PVD Output */
#define EXTI_Line17 ((uint32_t)0x20000) /* External interrupt line 17 Connected to the RTC Alarm event */
#define EXTI_Line18 ((uint32_t)0x40000) /* External interrupt line 18 Connected to the USBD Device \
Wakeup from suspend event */
#define EXTI_Line19 ((uint32_t)0x80000) /* External interrupt line 19 Connected to the Ethernet Wakeup event */
#define EXTI_Line20 ((uint32_t)0x100000) /* External interrupt line 20 Connected to the USBFS Wakeup event */
#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
#define EXTI_Line21 ((uint32_t)0x200000) /* External interrupt line 21 Connected to the OSCCAL Wakeup event */
#endif
void EXTI_DeInit(void);
void EXTI_Init(EXTI_InitTypeDef *EXTI_InitStruct);
void EXTI_StructInit(EXTI_InitTypeDef *EXTI_InitStruct);
void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
void EXTI_ClearFlag(uint32_t EXTI_Line);
ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_flash.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the FLASH
* firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_FLASH_H
#define __CH32V20x_FLASH_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v20x.h"
/* FLASH Status */
typedef enum
{
FLASH_BUSY = 1,
FLASH_ERROR_PG,
FLASH_ERROR_WRP,
FLASH_COMPLETE,
FLASH_TIMEOUT,
FLASH_OP_RANGE_ERROR = 0xFD,
FLASH_ALIGN_ERROR = 0xFE,
FLASH_ADR_RANGE_ERROR = 0xFF,
} FLASH_Status;
/* Write Protect */
#define FLASH_WRProt_Sectors0 ((uint32_t)0x00000001) /* Write protection of setor 0 ,4K bytes/sector */
#define FLASH_WRProt_Sectors1 ((uint32_t)0x00000002) /* Write protection of setor 1 ,4K bytes/sector */
#define FLASH_WRProt_Sectors2 ((uint32_t)0x00000004) /* Write protection of setor 2 ,4K bytes/sector */
#define FLASH_WRProt_Sectors3 ((uint32_t)0x00000008) /* Write protection of setor 3 ,4K bytes/sector */
#define FLASH_WRProt_Sectors4 ((uint32_t)0x00000010) /* Write protection of setor 4 ,4K bytes/sector */
#define FLASH_WRProt_Sectors5 ((uint32_t)0x00000020) /* Write protection of setor 5 ,4K bytes/sector */
#define FLASH_WRProt_Sectors6 ((uint32_t)0x00000040) /* Write protection of setor 6 ,4K bytes/sector */
#define FLASH_WRProt_Sectors7 ((uint32_t)0x00000080) /* Write protection of setor 7 ,4K bytes/sector */
#define FLASH_WRProt_Sectors8 ((uint32_t)0x00000100) /* Write protection of setor 8 ,4K bytes/sector */
#define FLASH_WRProt_Sectors9 ((uint32_t)0x00000200) /* Write protection of setor 9 ,4K bytes/sector */
#define FLASH_WRProt_Sectors10 ((uint32_t)0x00000400) /* Write protection of setor 10 ,4K bytes/sector */
#define FLASH_WRProt_Sectors11 ((uint32_t)0x00000800) /* Write protection of setor 11 ,4K bytes/sector */
#define FLASH_WRProt_Sectors12 ((uint32_t)0x00001000) /* Write protection of setor 12 ,4K bytes/sector */
#define FLASH_WRProt_Sectors13 ((uint32_t)0x00002000) /* Write protection of setor 13 ,4K bytes/sector */
#define FLASH_WRProt_Sectors14 ((uint32_t)0x00004000) /* Write protection of setor 14 ,4K bytes/sector */
#define FLASH_WRProt_Sectors15 ((uint32_t)0x00008000) /* Write protection of setor 15 ,4K bytes/sector */
#define FLASH_WRProt_Sectors16 ((uint32_t)0x00010000) /* Write protection of setor 16 ,4K bytes/sector */
#define FLASH_WRProt_Sectors17 ((uint32_t)0x00020000) /* Write protection of setor 17 ,4K bytes/sector */
#define FLASH_WRProt_Sectors18 ((uint32_t)0x00040000) /* Write protection of setor 18 ,4K bytes/sector */
#define FLASH_WRProt_Sectors19 ((uint32_t)0x00080000) /* Write protection of setor 19 ,4K bytes/sector */
#define FLASH_WRProt_Sectors20 ((uint32_t)0x00100000) /* Write protection of setor 20 ,4K bytes/sector */
#define FLASH_WRProt_Sectors21 ((uint32_t)0x00200000) /* Write protection of setor 21 ,4K bytes/sector */
#define FLASH_WRProt_Sectors22 ((uint32_t)0x00400000) /* Write protection of setor 22 ,4K bytes/sector */
#define FLASH_WRProt_Sectors23 ((uint32_t)0x00800000) /* Write protection of setor 23 ,4K bytes/sector */
#define FLASH_WRProt_Sectors24 ((uint32_t)0x01000000) /* Write protection of setor 24 ,4K bytes/sector */
#define FLASH_WRProt_Sectors25 ((uint32_t)0x02000000) /* Write protection of setor 25 ,4K bytes/sector */
#define FLASH_WRProt_Sectors26 ((uint32_t)0x04000000) /* Write protection of setor 26 ,4K bytes/sector */
#define FLASH_WRProt_Sectors27 ((uint32_t)0x08000000) /* Write protection of setor 27 ,4K bytes/sector */
#define FLASH_WRProt_Sectors28 ((uint32_t)0x10000000) /* Write protection of setor 28 ,4K bytes/sector */
#define FLASH_WRProt_Sectors29 ((uint32_t)0x20000000) /* Write protection of setor 29 ,4K bytes/sector */
#define FLASH_WRProt_Sectors30 ((uint32_t)0x40000000) /* Write protection of setor 30 ,4K bytes/sector */
#define FLASH_WRProt_Sectors31to127 ((uint32_t)0x80000000) /* Write protection of page 31 to 127 */
#define FLASH_WRProt_AllSectors ((uint32_t)0xFFFFFFFF) /* Write protection of all Sectors */
/* Option_Bytes_IWatchdog */
#define OB_IWDG_SW ((uint16_t)0x0001) /* Software IWDG selected */
#define OB_IWDG_HW ((uint16_t)0x0000) /* Hardware IWDG selected */
/* Option_Bytes_nRST_STOP */
#define OB_STOP_NoRST ((uint16_t)0x0002) /* No reset generated when entering in STOP */
#define OB_STOP_RST ((uint16_t)0x0000) /* Reset generated when entering in STOP */
/* Option_Bytes_nRST_STDBY */
#define OB_STDBY_NoRST ((uint16_t)0x0004) /* No reset generated when entering in STANDBY */
#define OB_STDBY_RST ((uint16_t)0x0000) /* Reset generated when entering in STANDBY */
/* FLASH_Interrupts */
#define FLASH_IT_ERROR ((uint32_t)0x00000400) /* FPEC error interrupt source */
#define FLASH_IT_EOP ((uint32_t)0x00001000) /* End of FLASH Operation Interrupt source */
#define FLASH_IT_BANK1_ERROR FLASH_IT_ERROR /* FPEC BANK1 error interrupt source */
#define FLASH_IT_BANK1_EOP FLASH_IT_EOP /* End of FLASH BANK1 Operation Interrupt source */
/* FLASH_Flags */
#define FLASH_FLAG_BSY ((uint32_t)0x00000001) /* FLASH Busy flag */
#define FLASH_FLAG_EOP ((uint32_t)0x00000020) /* FLASH End of Operation flag */
#define FLASH_FLAG_WRPRTERR ((uint32_t)0x00000010) /* FLASH Write protected error flag */
#define FLASH_FLAG_OPTERR ((uint32_t)0x00000001) /* FLASH Option Byte error flag */
#define FLASH_FLAG_BANK1_BSY FLASH_FLAG_BSY /* FLASH BANK1 Busy flag*/
#define FLASH_FLAG_BANK1_EOP FLASH_FLAG_EOP /* FLASH BANK1 End of Operation flag */
#define FLASH_FLAG_BANK1_WRPRTERR FLASH_FLAG_WRPRTERR /* FLASH BANK1 Write protected error flag */
/* FLASH_Access_CLK */
#define FLASH_Access_SYSTEM_HALF ((uint32_t)0x00000000) /* FLASH Enhance Clock = SYSTEM */
#define FLASH_Access_SYSTEM ((uint32_t)0x02000000) /* Enhance_CLK = SYSTEM/2 */
/*Functions used for all devices*/
void FLASH_Unlock(void);
void FLASH_Lock(void);
FLASH_Status FLASH_ErasePage(uint32_t Page_Address);
FLASH_Status FLASH_EraseAllPages(void);
FLASH_Status FLASH_EraseOptionBytes(void);
FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
FLASH_Status FLASH_ProgramOptionByteData(uint32_t Address, uint8_t Data);
FLASH_Status FLASH_EnableWriteProtection(uint32_t FLASH_Sectors);
FLASH_Status FLASH_ReadOutProtection(FunctionalState NewState);
FLASH_Status FLASH_UserOptionByteConfig(uint16_t OB_IWDG, uint16_t OB_STOP, uint16_t OB_STDBY);
uint32_t FLASH_GetUserOptionByte(void);
uint32_t FLASH_GetWriteProtectionOptionByte(void);
FlagStatus FLASH_GetReadOutProtectionStatus(void);
void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
void FLASH_ClearFlag(uint32_t FLASH_FLAG);
FLASH_Status FLASH_GetStatus(void);
FLASH_Status FLASH_WaitForLastOperation(uint32_t Timeout);
void FLASH_Unlock_Fast(void);
void FLASH_Lock_Fast(void);
void FLASH_ErasePage_Fast(uint32_t Page_Address);
void FLASH_EraseBlock_32K_Fast(uint32_t Block_Address);
void FLASH_ProgramPage_Fast(uint32_t Page_Address, uint32_t *pbuf);
void FLASH_Access_Clock_Cfg(uint32_t FLASH_Access_CLK);
void FLASH_Enhance_Mode(FunctionalState NewState);
#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
void FLASH_GetMACAddress(uint8_t *Buffer);
#endif
/* New function used for all devices */
void FLASH_UnlockBank1(void);
void FLASH_LockBank1(void);
FLASH_Status FLASH_EraseAllBank1Pages(void);
FLASH_Status FLASH_GetBank1Status(void);
FLASH_Status FLASH_WaitForLastBank1Operation(uint32_t Timeout);
FLASH_Status FLASH_ROM_ERASE(uint32_t StartAddr, uint32_t Length);
FLASH_Status FLASH_ROM_WRITE(uint32_t StartAddr, uint32_t *pbuf, uint32_t Length);
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_gpio.c
* Author : WCH
* Version : V1.0.0
* Date : 2024/05/06
* Description : This file provides all the GPIO firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include "ch32v20x_gpio.h"
#include "ch32v20x_rcc.h"
/* MASK */
#define ECR_PORTPINCONFIG_MASK ((uint16_t)0xFF80)
#define LSB_MASK ((uint16_t)0xFFFF)
#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000)
#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF)
#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000)
#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000)
#if defined (CH32V20x_D6)
uint8_t MCU_Version = 0;
#endif
/*********************************************************************
* @fn GPIO_DeInit
*
* @brief Deinitializes the GPIOx peripheral registers to their default
* reset values.
*
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
*
* @return none
*/
void GPIO_DeInit(GPIO_TypeDef *GPIOx)
{
if(GPIOx == GPIOA)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
}
else if(GPIOx == GPIOB)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
}
else if(GPIOx == GPIOC)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
}
else if(GPIOx == GPIOD)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
}
else if(GPIOx == GPIOE)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
}
}
/*********************************************************************
* @fn GPIO_AFIODeInit
*
* @brief Deinitializes the Alternate Functions (remap, event control
* and EXTI configuration) registers to their default reset values.
*
* @return none
*/
void GPIO_AFIODeInit(void)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
}
/*********************************************************************
* @fn GPIO_Init
*
* @brief GPIOx - where x can be (A..G) to select the GPIO peripheral.
*
* @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that
* contains the configuration information for the specified GPIO peripheral.
*
* @return none
*/
void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct)
{
uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
uint32_t tmpreg = 0x00, pinmask = 0x00;
currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
if((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)
{
currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;
}
#if defined (CH32V20x_D6)
if(((*(uint32_t *) 0x40022030) & 0x0F000000) == 0)
{
MCU_Version = 1;
}
if((GPIOx == GPIOC) && MCU_Version){
GPIO_InitStruct->GPIO_Pin = GPIO_InitStruct->GPIO_Pin >> 13;
}
#endif
if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00)
{
tmpreg = GPIOx->CFGLR;
for(pinpos = 0x00; pinpos < 0x08; pinpos++)
{
pos = ((uint32_t)0x01) << pinpos;
currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
if(currentpin == pos)
{
pos = pinpos << 2;
pinmask = ((uint32_t)0x0F) << pos;
tmpreg &= ~pinmask;
tmpreg |= (currentmode << pos);
if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
{
GPIOx->BCR = (((uint32_t)0x01) << pinpos);
}
else
{
if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
{
GPIOx->BSHR = (((uint32_t)0x01) << pinpos);
}
}
}
}
GPIOx->CFGLR = tmpreg;
}
if(GPIO_InitStruct->GPIO_Pin > 0x00FF)
{
tmpreg = GPIOx->CFGHR;
for(pinpos = 0x00; pinpos < 0x08; pinpos++)
{
pos = (((uint32_t)0x01) << (pinpos + 0x08));
currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
if(currentpin == pos)
{
pos = pinpos << 2;
pinmask = ((uint32_t)0x0F) << pos;
tmpreg &= ~pinmask;
tmpreg |= (currentmode << pos);
if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
{
GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x08));
}
if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
{
GPIOx->BSHR = (((uint32_t)0x01) << (pinpos + 0x08));
}
}
}
GPIOx->CFGHR = tmpreg;
}
}
/*********************************************************************
* @fn GPIO_StructInit
*
* @brief Fills each GPIO_InitStruct member with its default
*
* @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure
* which will be initialized.
*
* @return none
*/
void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct)
{
GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
}
/*********************************************************************
* @fn GPIO_ReadInputDataBit
*
* @brief GPIOx - where x can be (A..G) to select the GPIO peripheral.
*
* @param GPIO_Pin - specifies the port bit to read.
* This parameter can be GPIO_Pin_x where x can be (0..15).
*
* @return The input port pin value.
*/
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
uint8_t bitstatus = 0x00;
#if defined (CH32V20x_D6)
if((GPIOx == GPIOC) && MCU_Version){
GPIO_Pin = GPIO_Pin >> 13;
}
#endif
if((GPIOx->INDR & GPIO_Pin) != (uint32_t)Bit_RESET)
{
bitstatus = (uint8_t)Bit_SET;
}
else
{
bitstatus = (uint8_t)Bit_RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn GPIO_ReadInputData
*
* @brief Reads the specified GPIO input data port.
*
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
*
* @return The output port pin value.
*/
uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx)
{
uint16_t val;
#if defined (CH32V20x_D6)
if((GPIOx == GPIOC) && MCU_Version){
val = ( uint16_t )(GPIOx->INDR << 13);
}
else{
val = ( uint16_t )GPIOx->INDR;
}
#else
val = ( uint16_t )GPIOx->INDR;
#endif
return ( val );
}
/*********************************************************************
* @fn GPIO_ReadOutputDataBit
*
* @brief Reads the specified output data port bit.
*
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
* GPIO_Pin - specifies the port bit to read.
* This parameter can be GPIO_Pin_x where x can be (0..15).
*
* @return none
*/
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
uint8_t bitstatus = 0x00;
#if defined (CH32V20x_D6)
if((GPIOx == GPIOC) && MCU_Version){
GPIO_Pin = GPIO_Pin >> 13;
}
#endif
if((GPIOx->OUTDR & GPIO_Pin) != (uint32_t)Bit_RESET)
{
bitstatus = (uint8_t)Bit_SET;
}
else
{
bitstatus = (uint8_t)Bit_RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn GPIO_ReadOutputData
*
* @brief Reads the specified GPIO output data port.
*
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
*
* @return GPIO output port pin value.
*/
uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx)
{
uint16_t val;
#if defined (CH32V20x_D6)
if((GPIOx == GPIOC) && MCU_Version){
val = ( uint16_t )(GPIOx->OUTDR << 13);
}
else{
val = ( uint16_t )GPIOx->OUTDR;
}
#else
val = ( uint16_t )GPIOx->OUTDR;
#endif
return ( val );
}
/*********************************************************************
* @fn GPIO_SetBits
*
* @brief Sets the selected data port bits.
*
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
* GPIO_Pin - specifies the port bits to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
*
* @return none
*/
void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
#if defined (CH32V20x_D6)
if((GPIOx == GPIOC) && MCU_Version){
GPIO_Pin = GPIO_Pin >> 13;
}
#endif
GPIOx->BSHR = GPIO_Pin;
}
/*********************************************************************
* @fn GPIO_ResetBits
*
* @brief Clears the selected data port bits.
*
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
* GPIO_Pin - specifies the port bits to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
*
* @return none
*/
void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
#if defined (CH32V20x_D6)
if((GPIOx == GPIOC) && MCU_Version){
GPIO_Pin = GPIO_Pin >> 13;
}
#endif
GPIOx->BCR = GPIO_Pin;
}
/*********************************************************************
* @fn GPIO_WriteBit
*
* @brief Sets or clears the selected data port bit.
*
* @param GPIO_Pin - specifies the port bit to be written.
* This parameter can be one of GPIO_Pin_x where x can be (0..15).
* BitVal - specifies the value to be written to the selected bit.
* Bit_RESET - to clear the port pin.
* Bit_SET - to set the port pin.
*
* @return none
*/
void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
{
#if defined (CH32V20x_D6)
if((GPIOx == GPIOC) && MCU_Version){
GPIO_Pin = GPIO_Pin >> 13;
}
#endif
if(BitVal != Bit_RESET)
{
GPIOx->BSHR = GPIO_Pin;
}
else
{
GPIOx->BCR = GPIO_Pin;
}
}
/*********************************************************************
* @fn GPIO_Write
*
* @brief Writes data to the specified GPIO data port.
*
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
* PortVal - specifies the value to be written to the port output data register.
*
* @return none
*/
void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal)
{
#if defined (CH32V20x_D6)
if((GPIOx == GPIOC) && MCU_Version){
PortVal = PortVal >> 13;
}
#endif
GPIOx->OUTDR = PortVal;
}
/*********************************************************************
* @fn GPIO_PinLockConfig
*
* @brief Locks GPIO Pins configuration registers.
*
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
* GPIO_Pin - specifies the port bit to be written.
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
*
* @return none
*/
void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
{
uint32_t tmp = 0x00010000;
#if defined (CH32V20x_D6)
if((GPIOx == GPIOC) && MCU_Version){
GPIO_Pin = GPIO_Pin >> 13;
}
#endif
tmp |= GPIO_Pin;
GPIOx->LCKR = tmp;
GPIOx->LCKR = GPIO_Pin;
GPIOx->LCKR = tmp;
tmp = GPIOx->LCKR;
tmp = GPIOx->LCKR;
}
/*********************************************************************
* @fn GPIO_EventOutputConfig
*
* @brief Selects the GPIO pin used as Event output.
*
* @param GPIO_PortSource - selects the GPIO port to be used as source
* for Event output.
* This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).
* GPIO_PinSource - specifies the pin for the Event output.
* This parameter can be GPIO_PinSourcex where x can be (0..15).
*
* @return none
*/
void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
{
uint32_t tmpreg = 0x00;
tmpreg = AFIO->ECR;
tmpreg &= ECR_PORTPINCONFIG_MASK;
tmpreg |= (uint32_t)GPIO_PortSource << 0x04;
tmpreg |= GPIO_PinSource;
AFIO->ECR = tmpreg;
}
/*********************************************************************
* @fn GPIO_EventOutputCmd
*
* @brief Enables or disables the Event Output.
*
* @param NewState - ENABLE or DISABLE.
*
* @return none
*/
void GPIO_EventOutputCmd(FunctionalState NewState)
{
if(NewState)
{
AFIO->ECR |= (1 << 7);
}
else
{
AFIO->ECR &= ~(1 << 7);
}
}
/*********************************************************************
* @fn GPIO_PinRemapConfig
*
* @brief Changes the mapping of the specified pin.
*
* @param GPIO_Remap - selects the pin to remap.
* GPIO_Remap_SPI1 - SPI1 Alternate Function mapping
* GPIO_Remap_I2C1 - I2C1 Alternate Function mapping
* GPIO_Remap_USART1 - USART1 Alternate Function mapping
* GPIO_Remap_USART2 - USART2 Alternate Function mapping
* GPIO_PartialRemap_USART3 - USART3 Partial Alternate Function mapping
* GPIO_FullRemap_USART3 - USART3 Full Alternate Function mapping
* GPIO_PartialRemap_TIM1 - TIM1 Partial Alternate Function mapping
* GPIO_FullRemap_TIM1 - TIM1 Full Alternate Function mapping
* GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping
* GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping
* GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping
* GPIO_PartialRemap_TIM3 - TIM3 Partial Alternate Function mapping
* GPIO_FullRemap_TIM3 - TIM3 Full Alternate Function mapping
* GPIO_Remap_TIM4 - TIM4 Alternate Function mapping
* GPIO_Remap1_CAN1 - CAN1 Alternate Function mapping
* GPIO_Remap2_CAN1 - CAN1 Alternate Function mapping
* GPIO_Remap_PD0PD1 - PD0 and PD1 Alternate Function mapping
* GPIO_Remap_ADC1_ETRGINJ - ADC1 External Trigger Injected Conversion remapping
* GPIO_Remap_ADC1_ETRGREG - ADC1 External Trigger Regular Conversion remapping
* GPIO_Remap_ADC2_ETRGINJ - ADC2 External Trigger Injected Conversion remapping
* GPIO_Remap_ADC2_ETRGREG - ADC2 External Trigger Regular Conversion remapping
* GPIO_Remap_ETH - Ethernet remapping
* GPIO_Remap_CAN2 - CAN2 remapping
* GPIO_Remap_MII_RMII_SEL - MII or RMII selection
* GPIO_Remap_SWJ_Disable - Full SWJ Disabled
* GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame) connected
* to TIM2 Internal Trigger 1 for calibration
* GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame)
* GPIO_Remap_TIM8 - TIM8 Alternate Function mapping
* GPIO_PartialRemap_TIM9 - TIM9 Partial Alternate Function mapping
* GPIO_FullRemap_TIM9 - TIM9 Full Alternate Function mapping
* GPIO_PartialRemap_TIM10 - TIM10 Partial Alternate Function mapping
* GPIO_FullRemap_TIM10 - TIM10 Full Alternate Function mapping
* GPIO_Remap_FSMC_NADV - FSMC_NADV Alternate Function mapping
* GPIO_PartialRemap_USART4 - USART4 Partial Alternate Function mapping
* GPIO_FullRemap_USART4 - USART4 Full Alternate Function mapping
* GPIO_PartialRemap_USART5 - USART5 Partial Alternate Function mapping
* GPIO_FullRemap_USART5 - USART5 Full Alternate Function mapping
* GPIO_PartialRemap_USART6 - USART6 Partial Alternate Function mapping
* GPIO_FullRemap_USART6 - USART6 Full Alternate Function mapping
* GPIO_PartialRemap_USART7 - USART7 Partial Alternate Function mapping
* GPIO_FullRemap_USART7 - USART7 Full Alternate Function mapping
* GPIO_PartialRemap_USART8 - USART8 Partial Alternate Function mapping
* GPIO_FullRemap_USART8 - USART8 Full Alternate Function mapping
* GPIO_Remap_USART1_HighBit - USART1 Alternate Function mapping high bit
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)
{
uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
if((GPIO_Remap & 0x80000000) == 0x80000000)
{
tmpreg = AFIO->PCFR2;
}
else
{
tmpreg = AFIO->PCFR1;
if(((*(uint32_t *) 0x40022030) & 0x0F000000) == 0){
tmpreg = ((tmpreg>>1)&0xFFFFE000)|(tmpreg&0x00001FFF);
}
}
tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
tmp = GPIO_Remap & LSB_MASK;
/* Clear bit */
if((GPIO_Remap & 0x80000000) == 0x80000000)
{ /* PCFR2 */
if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [31:16] 2bit */
{
tmp1 = ((uint32_t)0x03) << (tmpmask + 0x10);
tmpreg &= ~tmp1;
}
else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */
{
tmp1 = ((uint32_t)0x03) << tmpmask;
tmpreg &= ~tmp1;
}
else /* [31:0] 1bit */
{
tmpreg &= ~(tmp << (((GPIO_Remap & 0x7FFFFFFF ) >> 0x15) * 0x10));
}
}
else
{ /* PCFR1 */
if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) /* [26:24] 3bit SWD_JTAG */
{
tmpreg &= DBGAFR_SWJCFG_MASK;
AFIO->PCFR1 &= DBGAFR_SWJCFG_MASK;
}
else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) /* [15:0] 2bit */
{
tmp1 = ((uint32_t)0x03) << tmpmask;
tmpreg &= ~tmp1;
tmpreg |= ~DBGAFR_SWJCFG_MASK;
}
else /* [31:0] 1bit */
{
tmpreg &= ~(tmp << ((GPIO_Remap >> 0x15) * 0x10));
tmpreg |= ~DBGAFR_SWJCFG_MASK;
}
}
/* Set bit */
if(NewState != DISABLE)
{
tmpreg |= (tmp << (((GPIO_Remap & 0x7FFFFFFF )>> 0x15) * 0x10));
}
if((GPIO_Remap & 0x80000000) == 0x80000000)
{
AFIO->PCFR2 = tmpreg;
}
else
{
AFIO->PCFR1 = tmpreg;
}
}
/*********************************************************************
* @fn GPIO_EXTILineConfig
*
* @brief Selects the GPIO pin used as EXTI Line.
*
* @param GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines.
* This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).
* GPIO_PinSource - specifies the EXTI line to be configured.
* This parameter can be GPIO_PinSourcex where x can be (0..15).
*
* @return none
*/
void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
{
uint32_t tmp = 0x00;
tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03));
AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;
AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)));
}
/*********************************************************************
* @fn GPIO_ETH_MediaInterfaceConfig
*
* @brief Selects the Ethernet media interface.
*
* @param GPIO_ETH_MediaInterface - specifies the Media Interface mode.
* GPIO_ETH_MediaInterface_MII - MII mode
* GPIO_ETH_MediaInterface_RMII - RMII mode
*
* @return none
*/
void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface)
{
if(GPIO_ETH_MediaInterface)
{
AFIO->PCFR1 |= (1 << 23);
}
else
{
AFIO->PCFR1 &= ~(1 << 23);
}
}
/*********************************************************************
* @fn GPIO_IPD_Unused
*
* @brief Configure unused GPIO as input pull-up.
*
* @param none
*
* @return none
*/
void GPIO_IPD_Unused(void)
{
GPIO_InitTypeDef GPIO_InitStructure = {0};
uint32_t chip = 0;
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB \
| RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD|RCC_APB2Periph_AFIO,ENABLE);
chip = *( uint32_t * )0x1FFFF704 & (~0x000000F0);
switch(chip)
{
#ifdef CH32V20x_D6
case 0x20370500: //CH32V203F6P6
{
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8|GPIO_Pin_9\
|GPIO_Pin_10|GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOA, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0\
|GPIO_Pin_3|GPIO_Pin_4\
|GPIO_Pin_5|GPIO_Pin_6\
|GPIO_Pin_7|GPIO_Pin_9\
|GPIO_Pin_10|GPIO_Pin_11\
|GPIO_Pin_12|GPIO_Pin_13\
|GPIO_Pin_14|GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOB, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6|GPIO_Pin_7\
|GPIO_Pin_8|GPIO_Pin_9\
|GPIO_Pin_10|GPIO_Pin_11\
|GPIO_Pin_12|GPIO_Pin_13\
|GPIO_Pin_14|GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOC, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOD, &GPIO_InitStructure);
break;
}
case 0x203A0500: //CH32V203F8P6
{
GPIO_PinRemapConfig(GPIO_Remap_PD01, ENABLE);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11|GPIO_Pin_12\
|GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOA, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
GPIO_Init(GPIOB, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1\
|GPIO_Pin_3|GPIO_Pin_4\
|GPIO_Pin_5|GPIO_Pin_8\
|GPIO_Pin_9|GPIO_Pin_10\
|GPIO_Pin_11|GPIO_Pin_12;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOB, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6|GPIO_Pin_7\
|GPIO_Pin_8|GPIO_Pin_9\
|GPIO_Pin_10|GPIO_Pin_11\
|GPIO_Pin_12|GPIO_Pin_13\
|GPIO_Pin_14|GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOC, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOD, &GPIO_InitStructure);
break;
}
case 0x203E0500: //CH32V203F8U6
{
GPIO_PinRemapConfig(GPIO_Remap_PD01, ENABLE);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOA, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
GPIO_Init(GPIOB, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6|GPIO_Pin_7\
|GPIO_Pin_8|GPIO_Pin_9\
|GPIO_Pin_12|GPIO_Pin_13;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOB, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6|GPIO_Pin_7\
|GPIO_Pin_8|GPIO_Pin_9\
|GPIO_Pin_10|GPIO_Pin_11\
|GPIO_Pin_12|GPIO_Pin_13\
|GPIO_Pin_14|GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOC, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOD, &GPIO_InitStructure);
break;
}
case 0x20360500: //CH32V203G6U6
{
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOA, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
GPIO_Init(GPIOB, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9\
|GPIO_Pin_10|GPIO_Pin_11\
|GPIO_Pin_12|GPIO_Pin_13\
|GPIO_Pin_14|GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOB, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6|GPIO_Pin_7\
|GPIO_Pin_8|GPIO_Pin_9\
|GPIO_Pin_10|GPIO_Pin_11\
|GPIO_Pin_12|GPIO_Pin_13\
|GPIO_Pin_14|GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOC, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOD, &GPIO_InitStructure);
break;
}
case 0x203B0500: //CH32V203G8R6
{
GPIO_PinRemapConfig(GPIO_Remap_PD01, ENABLE);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOA, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
GPIO_Init(GPIOB, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_9;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOB, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6|GPIO_Pin_7\
|GPIO_Pin_8|GPIO_Pin_9\
|GPIO_Pin_10|GPIO_Pin_11\
|GPIO_Pin_12|GPIO_Pin_13\
|GPIO_Pin_14|GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOC, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1|GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOD, &GPIO_InitStructure);
break;
}
case 0x20320500: //CH32V203K8T6
{
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
GPIO_Init(GPIOB, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9\
|GPIO_Pin_10|GPIO_Pin_11\
|GPIO_Pin_12|GPIO_Pin_13\
|GPIO_Pin_14|GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOB, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6|GPIO_Pin_7\
|GPIO_Pin_8|GPIO_Pin_9\
|GPIO_Pin_10|GPIO_Pin_11\
|GPIO_Pin_12|GPIO_Pin_13\
|GPIO_Pin_14|GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOC, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOD, &GPIO_InitStructure);
break;
}
case 0x20330500: //CH32V203C6T6
{
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6|GPIO_Pin_7\
|GPIO_Pin_8|GPIO_Pin_9\
|GPIO_Pin_10|GPIO_Pin_11\
|GPIO_Pin_12;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOC, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOD, &GPIO_InitStructure);
break;
}
case 0x20310500: //CH32V203C8T6
{
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6|GPIO_Pin_7\
|GPIO_Pin_8|GPIO_Pin_9\
|GPIO_Pin_10|GPIO_Pin_11\
|GPIO_Pin_12;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOC, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOD, &GPIO_InitStructure);
break;
}
case 0x20300500: //CH32V203C8U6
{
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6|GPIO_Pin_7\
|GPIO_Pin_8|GPIO_Pin_9\
|GPIO_Pin_10|GPIO_Pin_11\
|GPIO_Pin_12;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOC, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOD, &GPIO_InitStructure);
break;
}
#elif defined(CH32V20x_D8)
case 0x2034050C: //CH32V203RBT6
{
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3|GPIO_Pin_4\
|GPIO_Pin_5|GPIO_Pin_6;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOD, &GPIO_InitStructure);
break;
}
#elif defined(CH32V20x_D8W)
case 0x2083050C: //CH32V208GBU6
{
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8|GPIO_Pin_9\
|GPIO_Pin_10|GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOA, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPD;
GPIO_Init(GPIOB, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_9|GPIO_Pin_10\
|GPIO_Pin_11|GPIO_Pin_12\
|GPIO_Pin_13|GPIO_Pin_14\
|GPIO_Pin_15;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOB, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_10|GPIO_Pin_11\
|GPIO_Pin_12|GPIO_Pin_13;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOC, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOD, &GPIO_InitStructure);
break;
}
case 0x2082050C: //CH32V208CBU6
{
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6|GPIO_Pin_7\
|GPIO_Pin_8|GPIO_Pin_9\
|GPIO_Pin_10|GPIO_Pin_11\
|GPIO_Pin_12;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOC, &GPIO_InitStructure);
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2|GPIO_Pin_3\
|GPIO_Pin_4|GPIO_Pin_5\
|GPIO_Pin_6;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOD, &GPIO_InitStructure);
break;
}
case 0x2081050C: //CH32V208RBT6
{
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3|GPIO_Pin_4\
|GPIO_Pin_5|GPIO_Pin_6;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
GPIO_Init(GPIOD, &GPIO_InitStructure);
break;
}
#endif
default:
{
break;
}
}
}

191
ch32v203_ir_box/src/periph/ch32v20x_gpio.h Normal file
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@ -0,0 +1,191 @@
/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_gpio.h
* Author : WCH
* Version : V1.0.0
* Date : 2024/07/23
* Description : This file contains all the functions prototypes for the
* GPIO firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_GPIO_H
#define __CH32V20x_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v20x.h"
/* Output Maximum frequency selection */
typedef enum
{
GPIO_Speed_10MHz = 1,
GPIO_Speed_2MHz,
GPIO_Speed_50MHz
} GPIOSpeed_TypeDef;
/* Configuration Mode enumeration */
typedef enum
{
GPIO_Mode_AIN = 0x0,
GPIO_Mode_IN_FLOATING = 0x04,
GPIO_Mode_IPD = 0x28,
GPIO_Mode_IPU = 0x48,
GPIO_Mode_Out_OD = 0x14,
GPIO_Mode_Out_PP = 0x10,
GPIO_Mode_AF_OD = 0x1C,
GPIO_Mode_AF_PP = 0x18
} GPIOMode_TypeDef;
/* GPIO Init structure definition */
typedef struct
{
uint16_t GPIO_Pin; /* Specifies the GPIO pins to be configured.
This parameter can be any value of @ref GPIO_pins_define */
GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins.
This parameter can be a value of @ref GPIOSpeed_TypeDef */
GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins.
This parameter can be a value of @ref GPIOMode_TypeDef */
} GPIO_InitTypeDef;
/* Bit_SET and Bit_RESET enumeration */
typedef enum
{
Bit_RESET = 0,
Bit_SET
} BitAction;
/* GPIO_pins_define */
#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */
#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */
#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */
#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */
#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */
#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */
#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */
#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */
#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */
#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */
#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */
#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */
#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */
#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */
#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */
#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */
#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */
/* GPIO_Remap_define */
/* PCFR1 */
#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */
#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /* I2C1 Alternate Function mapping */
#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /* USART1 Alternate Function mapping low bit */
#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /* USART2 Alternate Function mapping */
#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /* USART3 Partial Alternate Function mapping */
#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /* USART3 Full Alternate Function mapping */
#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /* TIM1 Partial Alternate Function mapping */
#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */
#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */
#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */
#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */
#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /* TIM3 Partial Alternate Function mapping */
#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /* TIM3 Full Alternate Function mapping */
#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /* TIM4 Alternate Function mapping */
#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /* CAN1 Alternate Function mapping */
#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /* CAN1 Alternate Function mapping */
#define GPIO_Remap_PD0PD1 ((uint32_t)0x00008000) /* PD0 and PD1 Alternate Function mapping */
#define GPIO_Remap_TIM5CH4_LSI ((uint32_t)0x00200001) /* LSI connected to TIM5 Channel4 input capture for calibration */
#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */
#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */
#define GPIO_Remap_ADC2_ETRGINJ ((uint32_t)0x00200008) /* ADC2 External Trigger Injected Conversion remapping */
#define GPIO_Remap_ADC2_ETRGREG ((uint32_t)0x00200010) /* ADC2 External Trigger Regular Conversion remapping */
#define GPIO_Remap_ETH ((uint32_t)0x00200020) /* Ethernet remapping (only for Connectivity line devices) */
#define GPIO_Remap_CAN2 ((uint32_t)0x00200040) /* CAN2 remapping (only for Connectivity line devices) */
#define GPIO_Remap_MII_RMII_SEL ((uint32_t)0x00200080) /* MII or RMII selection */
#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* Full SWJ Disabled */
#define GPIO_Remap_SPI3 ((uint32_t)0x00201000) /* SPI3/I2S3 Alternate Function mapping (only for Connectivity line devices) */
#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /* Ethernet PTP output or USB OTG SOF (Start of Frame) connected \
to TIM2 Internal Trigger 1 for calibration \
(only for Connectivity line devices) */
#define GPIO_Remap_PTP_PPS ((uint32_t)0x00204000) /* Ethernet MAC PPS_PTS output on PB05 (only for Connectivity line devices) */
#define GPIO_Remap_PD01 GPIO_Remap_PD0PD1
/* PCFR2 */
#define GPIO_Remap_TIM8 ((uint32_t)0x80000004) /* TIM8 Alternate Function mapping */
#define GPIO_PartialRemap_TIM9 ((uint32_t)0x80130008) /* TIM9 Partial Alternate Function mapping */
#define GPIO_FullRemap_TIM9 ((uint32_t)0x80130010) /* TIM9 Full Alternate Function mapping */
#define GPIO_PartialRemap_TIM10 ((uint32_t)0x80150020) /* TIM10 Partial Alternate Function mapping */
#define GPIO_FullRemap_TIM10 ((uint32_t)0x80150040) /* TIM10 Full Alternate Function mapping */
#define GPIO_Remap_FSMC_NADV ((uint32_t)0x80000400) /* FSMC_NADV Alternate Function mapping */
#define GPIO_PartialRemap_USART4 ((uint32_t)0x80300001) /* USART4 Partial Alternate Function mapping */
#define GPIO_FullRemap_USART4 ((uint32_t)0x80300002) /* USART4 Full Alternate Function mapping */
#define GPIO_PartialRemap_USART5 ((uint32_t)0x80320004) /* USART5 Partial Alternate Function mapping */
#define GPIO_FullRemap_USART5 ((uint32_t)0x80320008) /* USART5 Full Alternate Function mapping */
#define GPIO_PartialRemap_USART6 ((uint32_t)0x80340010) /* USART6 Partial Alternate Function mapping */
#define GPIO_FullRemap_USART6 ((uint32_t)0x80340020) /* USART6 Full Alternate Function mapping */
#define GPIO_PartialRemap_USART7 ((uint32_t)0x80360040) /* USART7 Partial Alternate Function mapping */
#define GPIO_FullRemap_USART7 ((uint32_t)0x80360080) /* USART7 Full Alternate Function mapping */
#define GPIO_PartialRemap_USART8 ((uint32_t)0x80380100) /* USART8 Partial Alternate Function mapping */
#define GPIO_FullRemap_USART8 ((uint32_t)0x80380200) /* USART8 Full Alternate Function mapping */
#define GPIO_Remap_USART1_HighBit ((uint32_t)0x80200400) /* USART1 Alternate Function mapping high bit */
/* GPIO_Port_Sources */
#define GPIO_PortSourceGPIOA ((uint8_t)0x00)
#define GPIO_PortSourceGPIOB ((uint8_t)0x01)
#define GPIO_PortSourceGPIOC ((uint8_t)0x02)
#define GPIO_PortSourceGPIOD ((uint8_t)0x03)
#define GPIO_PortSourceGPIOE ((uint8_t)0x04)
#define GPIO_PortSourceGPIOF ((uint8_t)0x05)
#define GPIO_PortSourceGPIOG ((uint8_t)0x06)
/* GPIO_Pin_sources */
#define GPIO_PinSource0 ((uint8_t)0x00)
#define GPIO_PinSource1 ((uint8_t)0x01)
#define GPIO_PinSource2 ((uint8_t)0x02)
#define GPIO_PinSource3 ((uint8_t)0x03)
#define GPIO_PinSource4 ((uint8_t)0x04)
#define GPIO_PinSource5 ((uint8_t)0x05)
#define GPIO_PinSource6 ((uint8_t)0x06)
#define GPIO_PinSource7 ((uint8_t)0x07)
#define GPIO_PinSource8 ((uint8_t)0x08)
#define GPIO_PinSource9 ((uint8_t)0x09)
#define GPIO_PinSource10 ((uint8_t)0x0A)
#define GPIO_PinSource11 ((uint8_t)0x0B)
#define GPIO_PinSource12 ((uint8_t)0x0C)
#define GPIO_PinSource13 ((uint8_t)0x0D)
#define GPIO_PinSource14 ((uint8_t)0x0E)
#define GPIO_PinSource15 ((uint8_t)0x0F)
/* Ethernet_Media_Interface */
#define GPIO_ETH_MediaInterface_MII ((u32)0x00000000)
#define GPIO_ETH_MediaInterface_RMII ((u32)0x00000001)
void GPIO_DeInit(GPIO_TypeDef *GPIOx);
void GPIO_AFIODeInit(void);
void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct);
void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct);
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx);
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx);
void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal);
void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
void GPIO_EventOutputCmd(FunctionalState NewState);
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
void GPIO_ETH_MediaInterfaceConfig(uint32_t GPIO_ETH_MediaInterface);
void GPIO_IPD_Unused(void);
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_iwdg.c
* Author : WCH
* Version : V1.0.0
* Date : 2023/12/29
* Description : This file provides all the IWDG firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include "ch32v20x_iwdg.h"
/* CTLR register bit mask */
#define CTLR_KEY_Reload ((uint16_t)0xAAAA)
#define CTLR_KEY_Enable ((uint16_t)0xCCCC)
/*********************************************************************
* @fn IWDG_WriteAccessCmd
*
* @brief Enables or disables write access to IWDG_PSCR and IWDG_RLDR registers.
*
* @param WDG_WriteAccess - new state of write access to IWDG_PSCR and
* IWDG_RLDR registers.
* IWDG_WriteAccess_Enable - Enable write access to IWDG_PSCR and
* IWDG_RLDR registers.
* IWDG_WriteAccess_Disable - Disable write access to IWDG_PSCR
* and IWDG_RLDR registers.
*
* @return none
*/
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
{
IWDG->CTLR = IWDG_WriteAccess;
}
/*********************************************************************
* @fn IWDG_SetPrescaler
*
* @brief Sets IWDG Prescaler value.
*
* @param IWDG_Prescaler - specifies the IWDG Prescaler value.
* IWDG_Prescaler_4 - IWDG prescaler set to 4.
* IWDG_Prescaler_8 - IWDG prescaler set to 8.
* IWDG_Prescaler_16 - IWDG prescaler set to 16.
* IWDG_Prescaler_32 - IWDG prescaler set to 32.
* IWDG_Prescaler_64 - IWDG prescaler set to 64.
* IWDG_Prescaler_128 - IWDG prescaler set to 128.
* IWDG_Prescaler_256 - IWDG prescaler set to 256.
*
* @return none
*/
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
{
IWDG->PSCR = IWDG_Prescaler;
}
/*********************************************************************
* @fn IWDG_SetReload
*
* @brief Sets IWDG Reload value.
*
* @param Reload - specifies the IWDG Reload value.
* This parameter must be a number between 0 and 0x0FFF.
*
* @return none
*/
void IWDG_SetReload(uint16_t Reload)
{
IWDG->RLDR = Reload;
}
/*********************************************************************
* @fn IWDG_ReloadCounter
*
* @brief Reloads IWDG counter with value defined in the reload register.
*
* @return none
*/
void IWDG_ReloadCounter(void)
{
IWDG->CTLR = CTLR_KEY_Reload;
}
/*********************************************************************
* @fn IWDG_Enable
*
* @brief Enables IWDG (write access to IWDG_PSCR and IWDG_RLDR registers disabled).
*
* @return none
*/
void IWDG_Enable(void)
{
IWDG->CTLR = CTLR_KEY_Enable;
while((RCC->RSTSCKR & 0x2)==RESET);
}
/*********************************************************************
* @fn IWDG_GetFlagStatus
*
* @brief Checks whether the specified IWDG flag is set or not.
*
* @param IWDG_FLAG - specifies the flag to check.
* IWDG_FLAG_PVU - Prescaler Value Update on going.
* IWDG_FLAG_RVU - Reload Value Update on going.
*
* @return none
*/
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
{
FlagStatus bitstatus = RESET;
if((IWDG->STATR & IWDG_FLAG) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_iwdg.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* IWDG firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_IWDG_H
#define __CH32V20x_IWDG_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v20x.h"
/* IWDG_WriteAccess */
#define IWDG_WriteAccess_Enable ((uint16_t)0x5555)
#define IWDG_WriteAccess_Disable ((uint16_t)0x0000)
/* IWDG_prescaler */
#define IWDG_Prescaler_4 ((uint8_t)0x00)
#define IWDG_Prescaler_8 ((uint8_t)0x01)
#define IWDG_Prescaler_16 ((uint8_t)0x02)
#define IWDG_Prescaler_32 ((uint8_t)0x03)
#define IWDG_Prescaler_64 ((uint8_t)0x04)
#define IWDG_Prescaler_128 ((uint8_t)0x05)
#define IWDG_Prescaler_256 ((uint8_t)0x06)
/* IWDG_Flag */
#define IWDG_FLAG_PVU ((uint16_t)0x0001)
#define IWDG_FLAG_RVU ((uint16_t)0x0002)
void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
void IWDG_SetReload(uint16_t Reload);
void IWDG_ReloadCounter(void);
void IWDG_Enable(void);
FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_misc.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file provides all the miscellaneous firmware functions .
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include "ch32v20x_misc.h"
__IO uint32_t NVIC_Priority_Group = 0;
/*********************************************************************
* @fn NVIC_PriorityGroupConfig
*
* @brief Configures the priority grouping - pre-emption priority and subpriority.
*
* @param NVIC_PriorityGroup - specifies the priority grouping bits length.
* NVIC_PriorityGroup_0 - 0 bits for pre-emption priority
* 3 bits for subpriority
* NVIC_PriorityGroup_1 - 1 bits for pre-emption priority
* 2 bits for subpriority
*
* @return none
*/
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
{
NVIC_Priority_Group = NVIC_PriorityGroup;
}
/*********************************************************************
* @fn NVIC_Init
*
* @brief Initializes the NVIC peripheral according to the specified parameters in
* the NVIC_InitStruct.
*
* @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the
* configuration information for the specified NVIC peripheral.
* interrupt nesting enable(CSR-0x804 bit1 = 1)
* NVIC_IRQChannelPreemptionPriority - range from 0 to 1.
* NVIC_IRQChannelSubPriority - range from 0 to 3.
*
* interrupt nesting disable(CSR-0x804 bit1 = 0)
* NVIC_IRQChannelPreemptionPriority - range is 0.
* NVIC_IRQChannelSubPriority - range from 0 to 7.
*
* @return none
*/
void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct)
{
#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN)
if(NVIC_Priority_Group == NVIC_PriorityGroup_0)
{
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4);
}
#else
if(NVIC_Priority_Group == NVIC_PriorityGroup_1)
{
if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1)
{
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 5));
}
else if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 0)
{
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 5));
}
}
#endif
if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
{
NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel);
}
else
{
NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel);
}
}

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_misc.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* miscellaneous firmware library functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_MISC_H
#define __CH32V20x_MISC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v20x.h"
/* CSR_INTSYSCR_INEST_definition */
#define INTSYSCR_INEST_NoEN 0x00 /* interrupt nesting disable(CSR-0x804 bit1 = 0) */
#define INTSYSCR_INEST_EN 0x01 /* interrupt nesting enable(CSR-0x804 bit1 = 1) */
/* Check the configuration of CSR(0x804) in the startup file(.S)
* interrupt nesting enable(CSR-0x804 bit1 = 1)
* priority - bit[7] - Preemption Priority
* bit[6:5] - Sub priority
* bit[4:0] - Reserve
* interrupt nesting disable(CSR-0x804 bit1 = 0)
* priority - bit[7:5] - Sub priority
* bit[4:0] - Reserve
*/
#ifndef INTSYSCR_INEST
#define INTSYSCR_INEST INTSYSCR_INEST_EN
#endif
/* NVIC Init Structure definition
* interrupt nesting enable(CSR-0x804 bit1 = 1)
* NVIC_IRQChannelPreemptionPriority - range from 0 to 1.
* NVIC_IRQChannelSubPriority - range from 0 to 3.
*
* interrupt nesting disable(CSR-0x804 bit1 = 0)
* NVIC_IRQChannelPreemptionPriority - range is 0.
* NVIC_IRQChannelSubPriority - range from 0 to 7.
*
*/
typedef struct
{
uint8_t NVIC_IRQChannel;
uint8_t NVIC_IRQChannelPreemptionPriority;
uint8_t NVIC_IRQChannelSubPriority;
FunctionalState NVIC_IRQChannelCmd;
} NVIC_InitTypeDef;
/* Preemption_Priority_Group */
#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN)
#define NVIC_PriorityGroup_0 ((uint32_t)0x00) /* interrupt nesting disable(CSR-0x804 bit1 = 0) */
#else
#define NVIC_PriorityGroup_1 ((uint32_t)0x01) /* interrupt nesting enable(CSR-0x804 bit1 = 1) */
#endif
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct);
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_pwr.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file provides all the PWR firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include "ch32v20x_pwr.h"
#include "ch32v20x_rcc.h"
/* PWR registers bit mask */
/* CTLR register bit mask */
#define CTLR_DS_MASK ((uint32_t)0xFFFFFFFC)
#define CTLR_PLS_MASK ((uint32_t)0xFFFFFF1F)
/*********************************************************************
* @fn PWR_DeInit
*
* @brief Deinitializes the PWR peripheral registers to their default
* reset values.
*
* @return none
*/
void PWR_DeInit(void)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
}
/*********************************************************************
* @fn PWR_BackupAccessCmd
*
* @brief Enables or disables access to the RTC and backup registers.
*
* @param NewState - new state of the access to the RTC and backup registers,
* This parameter can be: ENABLE or DISABLE.
*
* @return none
*/
void PWR_BackupAccessCmd(FunctionalState NewState)
{
if(NewState)
{
PWR->CTLR |= (1 << 8);
}
else
{
PWR->CTLR &= ~(1 << 8);
}
}
/*********************************************************************
* @fn PWR_PVDCmd
*
* @brief Enables or disables the Power Voltage Detector(PVD).
*
* @param NewState - new state of the PVD(ENABLE or DISABLE).
*
* @return none
*/
void PWR_PVDCmd(FunctionalState NewState)
{
if(NewState)
{
PWR->CTLR |= (1 << 4);
}
else
{
PWR->CTLR &= ~(1 << 4);
}
}
/*********************************************************************
* @fn PWR_PVDLevelConfig
*
* @brief Configures the voltage threshold detected by the Power Voltage
* Detector(PVD).
*
* @param PWR_PVDLevel - specifies the PVD detection level
* PWR_PVDLevel_MODE0 - PVD detection level set to mode 0.
* PWR_PVDLevel_MODE1 - PVD detection level set to mode 1.
* PWR_PVDLevel_MODE2 - PVD detection level set to mode 2.
* PWR_PVDLevel_MODE3 - PVD detection level set to mode 3.
* PWR_PVDLevel_MODE4 - PVD detection level set to mode 4.
* PWR_PVDLevel_MODE5 - PVD detection level set to mode 5.
* PWR_PVDLevel_MODE6 - PVD detection level set to mode 6.
* PWR_PVDLevel_MODE7 - PVD detection level set to mode 7.
*
* @return none
*/
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
{
uint32_t tmpreg = 0;
tmpreg = PWR->CTLR;
tmpreg &= CTLR_PLS_MASK;
tmpreg |= PWR_PVDLevel;
PWR->CTLR = tmpreg;
}
/*********************************************************************
* @fn PWR_WakeUpPinCmd
*
* @brief Enables or disables the WakeUp Pin functionality.
*
* @param NewState - new state of the WakeUp Pin functionality
* (ENABLE or DISABLE).
*
* @return none
*/
void PWR_WakeUpPinCmd(FunctionalState NewState)
{
if(NewState)
{
PWR->CSR |= (1 << 8);
}
else
{
PWR->CSR &= ~(1 << 8);
}
}
/*********************************************************************
* @fn PWR_EnterSTOPMode
*
* @brief Enters STOP mode.
*
* @param PWR_Regulator - specifies the regulator state in STOP mode.
* PWR_Regulator_ON - STOP mode with regulator ON
* PWR_Regulator_LowPower - STOP mode with regulator in low power mode
* PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction.
* PWR_STOPEntry_WFI - enter STOP mode with WFI instruction
* PWR_STOPEntry_WFE - enter STOP mode with WFE instruction
*
* @return none
*/
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
{
uint32_t tmpreg = 0;
tmpreg = PWR->CTLR;
tmpreg &= CTLR_DS_MASK;
tmpreg |= PWR_Regulator;
PWR->CTLR = tmpreg;
NVIC->SCTLR |= (1 << 2);
if(PWR_STOPEntry == PWR_STOPEntry_WFI)
{
__WFI();
}
else
{
__WFE();
}
NVIC->SCTLR &= ~(1 << 2);
}
/*********************************************************************
* @fn PWR_EnterSTANDBYMode
*
* @brief Enters STANDBY mode.
*
* @return none
*/
void PWR_EnterSTANDBYMode(void)
{
PWR->CTLR |= PWR_CTLR_CWUF;
PWR->CTLR |= PWR_CTLR_PDDS;
NVIC->SCTLR |= (1 << 2);
__WFI();
}
/*********************************************************************
* @fn PWR_GetFlagStatus
*
* @brief Checks whether the specified PWR flag is set or not.
*
* @param PWR_FLAG - specifies the flag to check.
* PWR_FLAG_WU - Wake Up flag
* PWR_FLAG_SB - StandBy flag
* PWR_FLAG_PVDO - PVD Output
*
* @return The new state of PWR_FLAG (SET or RESET).
*/
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
{
FlagStatus bitstatus = RESET;
if((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn PWR_ClearFlag
*
* @brief Clears the PWR's pending flags.
*
* @param PWR_FLAG - specifies the flag to clear.
* PWR_FLAG_WU - Wake Up flag
* PWR_FLAG_SB - StandBy flag
*
* @return none
*/
void PWR_ClearFlag(uint32_t PWR_FLAG)
{
PWR->CTLR |= PWR_FLAG << 2;
}
/*********************************************************************
* @fn PWR_EnterSTANDBYMode_RAM
*
* @brief Enters STANDBY mode with RAM data retention function on.
*
* @return none
*/
void PWR_EnterSTANDBYMode_RAM(void)
{
uint32_t tmpreg = 0;
tmpreg = PWR->CTLR;
tmpreg |= PWR_CTLR_CWUF;
tmpreg |= PWR_CTLR_PDDS;
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
//2K+30K in standby w power.
tmpreg |= (0x1 << 16) | (0x1 << 17);
#else
//RAM in standby power.
tmpreg |= ( ( uint32_t )1 << 16 );
#endif
PWR->CTLR = tmpreg;
NVIC->SCTLR |= (1 << 2);
__WFI();
}
/*********************************************************************
* @fn PWR_EnterSTANDBYMode_RAM_LV
*
* @brief Enters STANDBY mode with RAM data retention function and LV mode on.
*
* @return none
*/
void PWR_EnterSTANDBYMode_RAM_LV(void)
{
uint32_t tmpreg = 0;
tmpreg = PWR->CTLR;
tmpreg |= PWR_CTLR_CWUF;
tmpreg |= PWR_CTLR_PDDS;
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
//2K+30K in standby power.
tmpreg |= (0x1 << 16) | (0x1 << 17);
//2K+30K in standby LV .
tmpreg |= (0x1 << 20);
#else
//RAM in standby power.
tmpreg |= ( ( uint32_t )1 << 16 );
//RAM in standby LV .
tmpreg |= ( ( uint32_t )1 << 20 );
#endif
PWR->CTLR = tmpreg;
NVIC->SCTLR |= (1 << 2);
__WFI();
}
/*********************************************************************
* @fn PWR_EnterSTANDBYMode_RAM_VBAT_EN
*
* @brief Enters STANDBY mode with RAM data retention function on (VBAT Enable).
*
* @return none
*/
void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void)
{
uint32_t tmpreg = 0;
tmpreg = PWR->CTLR;
tmpreg |= PWR_CTLR_CWUF;
tmpreg |= PWR_CTLR_PDDS;
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
//2K+30K in standby power (VBAT Enable).
tmpreg |= (0x1 << 18) | (0x1 << 19);
#else
//RAM in standby w power.
tmpreg |= ( ( uint32_t )1 << 18 );
#endif
PWR->CTLR = tmpreg;
NVIC->SCTLR |= (1 << 2);
__WFI();
}
/*********************************************************************
* @fn PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN
*
* @brief Enters STANDBY mode with RAM data retention function and LV mode on(VBAT Enable).
*
* @return none
*/
void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void)
{
uint32_t tmpreg = 0;
tmpreg = PWR->CTLR;
tmpreg |= PWR_CTLR_CWUF;
tmpreg |= PWR_CTLR_PDDS;
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
//2K+30K in standby power (VBAT Enable).
tmpreg |= (0x1 << 18) | (0x1 << 19);
//2K+30K in standby LV .
tmpreg |= (0x1 << 20);
#else
//RAM in standby w power.
tmpreg |= ( ( uint32_t )1 << 18 );
//RAM in standby LV .
tmpreg |= ( ( uint32_t )1 << 20 );
#endif
PWR->CTLR = tmpreg;
NVIC->SCTLR |= (1 << 2);
__WFI();
}
/*********************************************************************
* @fn PWR_EnterSTOPMode_RAM_LV
*
* @brief Enters STOP mode with RAM data retention function and LV mode on.
*
* @param PWR_Regulator - specifies the regulator state in STOP mode.
* PWR_Regulator_ON - STOP mode with regulator ON
* PWR_Regulator_LowPower - STOP mode with regulator in low power mode
* PWR_STOPEntry - specifies if STOP mode in entered with WFI or WFE instruction.
* PWR_STOPEntry_WFI - enter STOP mode with WFI instruction
* PWR_STOPEntry_WFE - enter STOP mode with WFE instruction
*
* @return none
*/
void PWR_EnterSTOPMode_RAM_LV(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
{
uint32_t tmpreg = 0;
tmpreg = PWR->CTLR;
tmpreg &= CTLR_DS_MASK;
tmpreg |= PWR_Regulator;
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
tmpreg |= (0x1 << 20);
#else
tmpreg |= ( ( uint32_t )1 << 20 );
#endif
PWR->CTLR = tmpreg;
NVIC->SCTLR |= (1 << 2);
if(PWR_STOPEntry == PWR_STOPEntry_WFI)
{
__WFI();
}
else
{
__WFE();
}
NVIC->SCTLR &= ~(1 << 2);
}

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_pwr.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the PWR
* firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_PWR_H
#define __CH32V20x_PWR_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v20x.h"
/* PVD_detection_level */
#define PWR_PVDLevel_MODE0 ((uint32_t)0x00000000)
#define PWR_PVDLevel_MODE1 ((uint32_t)0x00000020)
#define PWR_PVDLevel_MODE2 ((uint32_t)0x00000040)
#define PWR_PVDLevel_MODE3 ((uint32_t)0x00000060)
#define PWR_PVDLevel_MODE4 ((uint32_t)0x00000080)
#define PWR_PVDLevel_MODE5 ((uint32_t)0x000000A0)
#define PWR_PVDLevel_MODE6 ((uint32_t)0x000000C0)
#define PWR_PVDLevel_MODE7 ((uint32_t)0x000000E0)
#define PWR_PVDLevel_2V2 PWR_PVDLevel_MODE0
#define PWR_PVDLevel_2V3 PWR_PVDLevel_MODE1
#define PWR_PVDLevel_2V4 PWR_PVDLevel_MODE2
#define PWR_PVDLevel_2V5 PWR_PVDLevel_MODE3
#define PWR_PVDLevel_2V6 PWR_PVDLevel_MODE4
#define PWR_PVDLevel_2V7 PWR_PVDLevel_MODE5
#define PWR_PVDLevel_2V8 PWR_PVDLevel_MODE6
#define PWR_PVDLevel_2V9 PWR_PVDLevel_MODE7
/* Regulator_state_is_STOP_mode */
#define PWR_Regulator_ON ((uint32_t)0x00000000)
#define PWR_Regulator_LowPower ((uint32_t)0x00000001)
/* STOP_mode_entry */
#define PWR_STOPEntry_WFI ((uint8_t)0x01)
#define PWR_STOPEntry_WFE ((uint8_t)0x02)
/* PWR_Flag */
#define PWR_FLAG_WU ((uint32_t)0x00000001)
#define PWR_FLAG_SB ((uint32_t)0x00000002)
#define PWR_FLAG_PVDO ((uint32_t)0x00000004)
void PWR_DeInit(void);
void PWR_BackupAccessCmd(FunctionalState NewState);
void PWR_PVDCmd(FunctionalState NewState);
void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
void PWR_WakeUpPinCmd(FunctionalState NewState);
void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
void PWR_EnterSTANDBYMode(void);
FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
void PWR_ClearFlag(uint32_t PWR_FLAG);
void PWR_EnterSTANDBYMode_RAM(void);
void PWR_EnterSTANDBYMode_RAM_LV(void);
void PWR_EnterSTANDBYMode_RAM_VBAT_EN(void);
void PWR_EnterSTANDBYMode_RAM_LV_VBAT_EN(void);
void PWR_EnterSTOPMode_RAM_LV(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_rcc.h
* Author : WCH
* Version : V1.0.0
* Date : 2024/02/21
* Description : This file provides all the RCC firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_RCC_H
#define __CH32V20x_RCC_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v20x.h"
/* RCC_Exported_Types */
typedef struct
{
uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */
uint32_t HCLK_Frequency; /* returns HCLK clock frequency expressed in Hz */
uint32_t PCLK1_Frequency; /* returns PCLK1 clock frequency expressed in Hz */
uint32_t PCLK2_Frequency; /* returns PCLK2 clock frequency expressed in Hz */
uint32_t ADCCLK_Frequency; /* returns ADCCLK clock frequency expressed in Hz */
} RCC_ClocksTypeDef;
/* HSE_configuration */
#define RCC_HSE_OFF ((uint32_t)0x00000000)
#define RCC_HSE_ON ((uint32_t)0x00010000)
#define RCC_HSE_Bypass ((uint32_t)0x00040000)
/* PLL_entry_clock_source */
#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000)
#define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000)
#define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000)
/* PLL_multiplication_factor for other CH32V20x */
#define RCC_PLLMul_2 ((uint32_t)0x00000000)
#define RCC_PLLMul_3 ((uint32_t)0x00040000)
#define RCC_PLLMul_4 ((uint32_t)0x00080000)
#define RCC_PLLMul_5 ((uint32_t)0x000C0000)
#define RCC_PLLMul_6 ((uint32_t)0x00100000)
#define RCC_PLLMul_7 ((uint32_t)0x00140000)
#define RCC_PLLMul_8 ((uint32_t)0x00180000)
#define RCC_PLLMul_9 ((uint32_t)0x001C0000)
#define RCC_PLLMul_10 ((uint32_t)0x00200000)
#define RCC_PLLMul_11 ((uint32_t)0x00240000)
#define RCC_PLLMul_12 ((uint32_t)0x00280000)
#define RCC_PLLMul_13 ((uint32_t)0x002C0000)
#define RCC_PLLMul_14 ((uint32_t)0x00300000)
#define RCC_PLLMul_15 ((uint32_t)0x00340000)
#define RCC_PLLMul_16 ((uint32_t)0x00380000)
#define RCC_PLLMul_18 ((uint32_t)0x003C0000)
/* System_clock_source */
#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
/* AHB_clock_source */
#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
/* APB1_APB2_clock_source */
#define RCC_HCLK_Div1 ((uint32_t)0x00000000)
#define RCC_HCLK_Div2 ((uint32_t)0x00000400)
#define RCC_HCLK_Div4 ((uint32_t)0x00000500)
#define RCC_HCLK_Div8 ((uint32_t)0x00000600)
#define RCC_HCLK_Div16 ((uint32_t)0x00000700)
/* RCC_Interrupt_source */
#define RCC_IT_LSIRDY ((uint8_t)0x01)
#define RCC_IT_LSERDY ((uint8_t)0x02)
#define RCC_IT_HSIRDY ((uint8_t)0x04)
#define RCC_IT_HSERDY ((uint8_t)0x08)
#define RCC_IT_PLLRDY ((uint8_t)0x10)
#define RCC_IT_CSS ((uint8_t)0x80)
/* USB_Device_clock_source */
#define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x00)
#define RCC_USBCLKSource_PLLCLK_Div2 ((uint8_t)0x01)
#define RCC_USBCLKSource_PLLCLK_Div3 ((uint8_t)0x02)
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
#define RCC_USBCLKSource_PLLCLK_Div5 ((uint8_t)0x03)
#endif
/* ADC_clock_source */
#define RCC_PCLK2_Div2 ((uint32_t)0x00000000)
#define RCC_PCLK2_Div4 ((uint32_t)0x00004000)
#define RCC_PCLK2_Div6 ((uint32_t)0x00008000)
#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000)
/* LSE_configuration */
#define RCC_LSE_OFF ((uint8_t)0x00)
#define RCC_LSE_ON ((uint8_t)0x01)
#define RCC_LSE_Bypass ((uint8_t)0x04)
/* RTC_clock_source */
#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
#define RCC_RTCCLKSource_HSE_Div512 ((uint32_t)0x00000300)
#else
#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300)
#endif
/* AHB_peripheral */
#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002)
#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040)
#define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100)
#define RCC_AHBPeriph_RNG ((uint32_t)0x00000200)
#define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)
#define RCC_AHBPeriph_USBHS ((uint32_t)0x00000800)
#define RCC_AHBPeriph_USBFS ((uint32_t)0x00001000)
#define RCC_AHBPeriph_OTG_FS RCC_AHBPeriph_USBFS
#ifdef CH32V20x_D8W
#define RCC_AHBPeriph_BLE_CRC ((uint32_t)0x00030040)
#endif
/* APB2_peripheral */
#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)
#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)
#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040)
#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400)
#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)
#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000)
#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000)
/* APB1_peripheral */
#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
#define RCC_APB1Periph_UART6 ((uint32_t)0x00000040)
#define RCC_APB1Periph_UART7 ((uint32_t)0x00000080)
#define RCC_APB1Periph_UART8 ((uint32_t)0x00000100)
#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
#define RCC_APB1Periph_SPI3 ((uint32_t)0x00008000)
#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
#define RCC_APB1Periph_USB ((uint32_t)0x00800000)
#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
#define RCC_APB1Periph_BKP ((uint32_t)0x08000000)
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
/* Clock_source_to_output_on_MCO_pin */
#define RCC_MCO_NoClock ((uint8_t)0x00)
#define RCC_MCO_SYSCLK ((uint8_t)0x04)
#define RCC_MCO_HSI ((uint8_t)0x05)
#define RCC_MCO_HSE ((uint8_t)0x06)
#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07)
/* RCC_Flag */
#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
#define RCC_FLAG_HSERDY ((uint8_t)0x31)
#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
#define RCC_FLAG_LSERDY ((uint8_t)0x41)
#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
#define RCC_FLAG_PINRST ((uint8_t)0x7A)
#define RCC_FLAG_PORRST ((uint8_t)0x7B)
#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
/* SysTick_clock_source */
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
/* USBFS_clock_source */
#define RCC_USBPLL_Div1 ((uint32_t)0x00)
#define RCC_USBPLL_Div2 ((uint32_t)0x01)
#define RCC_USBPLL_Div3 ((uint32_t)0x02)
#define RCC_USBPLL_Div4 ((uint32_t)0x03)
#define RCC_USBPLL_Div5 ((uint32_t)0x04)
#define RCC_USBPLL_Div6 ((uint32_t)0x05)
#define RCC_USBPLL_Div7 ((uint32_t)0x06)
#define RCC_USBPLL_Div8 ((uint32_t)0x07)
/* ETH_clock_source */
#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
#define RCC_ETHCLK_Div1 ((uint32_t)0x00)
#define RCC_ETHCLK_Div2 ((uint32_t)0x01)
#endif
void RCC_DeInit(void);
void RCC_HSEConfig(uint32_t RCC_HSE);
ErrorStatus RCC_WaitForHSEStartUp(void);
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
void RCC_HSICmd(FunctionalState NewState);
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
void RCC_PLLCmd(FunctionalState NewState);
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
uint8_t RCC_GetSYSCLKSource(void);
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
void RCC_PCLK1Config(uint32_t RCC_HCLK);
void RCC_PCLK2Config(uint32_t RCC_HCLK);
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
void RCC_LSEConfig(uint8_t RCC_LSE);
void RCC_LSICmd(FunctionalState NewState);
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
void RCC_RTCCLKCmd(FunctionalState NewState);
void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks);
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
void RCC_BackupResetCmd(FunctionalState NewState);
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
void RCC_MCOConfig(uint8_t RCC_MCO);
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
void RCC_ClearFlag(void);
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
void RCC_ClearITPendingBit(uint8_t RCC_IT);
void RCC_ADCCLKADJcmd(FunctionalState NewState);
FlagStatus RCC_USB5PRE_JUDGE();
#if defined(CH32V20x_D8) || defined(CH32V20x_D8W)
void RCC_ETHDIVConfig(uint32_t RCC_ETHPRE_Div);
#endif
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_spi.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file provides all the SPI firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include "ch32v20x_spi.h"
#include "ch32v20x_rcc.h"
/* SPI SPE mask */
#define CTLR1_SPE_Set ((uint16_t)0x0040)
#define CTLR1_SPE_Reset ((uint16_t)0xFFBF)
/* I2S I2SE mask */
#define I2SCFGR_I2SE_Set ((uint16_t)0x0400)
#define I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF)
/* SPI CRCNext mask */
#define CTLR1_CRCNext_Set ((uint16_t)0x1000)
/* SPI CRCEN mask */
#define CTLR1_CRCEN_Set ((uint16_t)0x2000)
#define CTLR1_CRCEN_Reset ((uint16_t)0xDFFF)
/* SPI SSOE mask */
#define CTLR2_SSOE_Set ((uint16_t)0x0004)
#define CTLR2_SSOE_Reset ((uint16_t)0xFFFB)
/* SPI registers Masks */
#define CTLR1_CLEAR_Mask ((uint16_t)0x3040)
#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040)
/* SPI or I2S mode selection masks */
#define SPI_Mode_Select ((uint16_t)0xF7FF)
#define I2S_Mode_Select ((uint16_t)0x0800)
/* I2S clock source selection masks */
#define I2S2_CLOCK_SRC ((uint32_t)(0x00020000))
#define I2S3_CLOCK_SRC ((uint32_t)(0x00040000))
#define I2S_MUL_MASK ((uint32_t)(0x0000F000))
#define I2S_DIV_MASK ((uint32_t)(0x000000F0))
/*********************************************************************
* @fn SPI_I2S_DeInit
*
* @brief Deinitializes the SPIx peripheral registers to their default
* reset values (Affects also the I2Ss).
*
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
*
* @return none
*/
void SPI_I2S_DeInit(SPI_TypeDef *SPIx)
{
if(SPIx == SPI1)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
}
else if(SPIx == SPI2)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
}
}
/*********************************************************************
* @fn SPI_Init
*
* @brief Initializes the SPIx peripheral according to the specified
* parameters in the SPI_InitStruct.
*
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
* SPI_InitStruct - pointer to a SPI_InitTypeDef structure that
* contains the configuration information for the specified SPI peripheral.
*
* @return none
*/
void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct)
{
uint16_t tmpreg = 0;
tmpreg = SPIx->CTLR1;
tmpreg &= CTLR1_CLEAR_Mask;
tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |
SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |
SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
SPIx->CTLR1 = tmpreg;
SPIx->I2SCFGR &= SPI_Mode_Select;
SPIx->CRCR = SPI_InitStruct->SPI_CRCPolynomial;
}
/*********************************************************************
* @fn I2S_Init
*
* @brief Initializes the SPIx peripheral according to the specified
* parameters in the I2S_InitStruct.
*
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
* (configured in I2S mode).
* I2S_InitStruct - pointer to an I2S_InitTypeDef structure that
* contains the configuration information for the specified SPI peripheral
* configured in I2S mode.
*
* @return none
*/
void I2S_Init(SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct)
{
uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
uint32_t tmp = 0;
RCC_ClocksTypeDef RCC_Clocks;
uint32_t sourceclock = 0;
SPIx->I2SCFGR &= I2SCFGR_CLEAR_Mask;
SPIx->I2SPR = 0x0002;
tmpreg = SPIx->I2SCFGR;
if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
{
i2sodd = (uint16_t)0;
i2sdiv = (uint16_t)2;
}
else
{
if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
{
packetlength = 1;
}
else
{
packetlength = 2;
}
if(((uint32_t)SPIx) == SPI2_BASE)
{
tmp = I2S2_CLOCK_SRC;
}
else
{
tmp = I2S3_CLOCK_SRC;
}
RCC_GetClocksFreq(&RCC_Clocks);
sourceclock = RCC_Clocks.SYSCLK_Frequency;
if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
{
tmp = (uint16_t)(((((sourceclock / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
}
else
{
tmp = (uint16_t)(((((sourceclock / (32 * packetlength)) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
}
tmp = tmp / 10;
i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
i2sodd = (uint16_t)(i2sodd << 8);
}
if((i2sdiv < 2) || (i2sdiv > 0xFF))
{
i2sdiv = 2;
i2sodd = 0;
}
SPIx->I2SPR = (uint16_t)(i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
tmpreg |= (uint16_t)(I2S_Mode_Select | (uint16_t)(I2S_InitStruct->I2S_Mode |
(uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat |
(uint16_t)I2S_InitStruct->I2S_CPOL))));
SPIx->I2SCFGR = tmpreg;
}
/*********************************************************************
* @fn SPI_StructInit
*
* @brief Fills each SPI_InitStruct member with its default value.
*
* @param SPI_InitStruct - pointer to a SPI_InitTypeDef structure which
* will be initialized.
*
* @return none
*/
void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct)
{
SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
SPI_InitStruct->SPI_CRCPolynomial = 7;
}
/*********************************************************************
* @fn I2S_StructInit
*
* @brief Fills each I2S_InitStruct member with its default value.
*
* @param I2S_InitStruct - pointer to a I2S_InitTypeDef structure which
* will be initialized.
*
* @return none
*/
void I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct)
{
I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
}
/*********************************************************************
* @fn SPI_Cmd
*
* @brief Enables or disables the specified SPI peripheral.
*
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
SPIx->CTLR1 |= CTLR1_SPE_Set;
}
else
{
SPIx->CTLR1 &= CTLR1_SPE_Reset;
}
}
/*********************************************************************
* @fn I2S_Cmd
*
* @brief Enables or disables the specified SPI peripheral (in I2S mode).
*
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void I2S_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
SPIx->I2SCFGR |= I2SCFGR_I2SE_Set;
}
else
{
SPIx->I2SCFGR &= I2SCFGR_I2SE_Reset;
}
}
/*********************************************************************
* @fn SPI_I2S_ITConfig
*
* @brief Enables or disables the specified SPI/I2S interrupts.
*
* @param SPIx - where x can be
* - 1, 2 or 3 in SPI mode.
* - 2 or 3 in I2S mode.
* SPI_I2S_IT - specifies the SPI/I2S interrupt source to be
* enabled or disabled.
* SPI_I2S_IT_TXE - Tx buffer empty interrupt mask.
* SPI_I2S_IT_RXNE - Rx buffer not empty interrupt mask.
* SPI_I2S_IT_ERR - Error interrupt mask.
* NewState: ENABLE or DISABLE.
* @return none
*/
void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
{
uint16_t itpos = 0, itmask = 0;
itpos = SPI_I2S_IT >> 4;
itmask = (uint16_t)1 << (uint16_t)itpos;
if(NewState != DISABLE)
{
SPIx->CTLR2 |= itmask;
}
else
{
SPIx->CTLR2 &= (uint16_t)~itmask;
}
}
/*********************************************************************
* @fn SPI_I2S_DMACmd
*
* @brief Enables or disables the SPIx/I2Sx DMA interface.
*
* @param SPIx - where x can be
* - 1, 2 or 3 in SPI mode.
* - 2 or 3 in I2S mode.
* SPI_I2S_DMAReq - specifies the SPI/I2S DMA transfer request to
* be enabled or disabled.
* SPI_I2S_DMAReq_Tx - Tx buffer DMA transfer request.
* SPI_I2S_DMAReq_Rx - Rx buffer DMA transfer request.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
{
if(NewState != DISABLE)
{
SPIx->CTLR2 |= SPI_I2S_DMAReq;
}
else
{
SPIx->CTLR2 &= (uint16_t)~SPI_I2S_DMAReq;
}
}
/*********************************************************************
* @fn SPI_I2S_SendData
*
* @brief Transmits a Data through the SPIx/I2Sx peripheral.
*
* @param SPIx - where x can be
* - 1, 2 or 3 in SPI mode.
* - 2 or 3 in I2S mode.
* Data - Data to be transmitted.
*
* @return none
*/
void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data)
{
SPIx->DATAR = Data;
}
/*********************************************************************
* @fn SPI_I2S_ReceiveData
*
* @brief Returns the most recent received data by the SPIx/I2Sx peripheral.
*
* @param SPIx - where x can be
* - 1, 2 or 3 in SPI mode.
* - 2 or 3 in I2S mode.
* Data - Data to be transmitted.
*
* @return SPIx->DATAR - The value of the received data.
*/
uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx)
{
return SPIx->DATAR;
}
/*********************************************************************
* @fn SPI_NSSInternalSoftwareConfig
*
* @brief Configures internally by software the NSS pin for the selected SPI.
*
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
* SPI_NSSInternalSoft -
* SPI_NSSInternalSoft_Set - Set NSS pin internally.
* SPI_NSSInternalSoft_Reset - Reset NSS pin internally.
*
* @return none
*/
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft)
{
if(SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
{
SPIx->CTLR1 |= SPI_NSSInternalSoft_Set;
}
else
{
SPIx->CTLR1 &= SPI_NSSInternalSoft_Reset;
}
}
/*********************************************************************
* @fn SPI_SSOutputCmd
*
* @brief Enables or disables the SS output for the selected SPI.
*
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
* NewState - new state of the SPIx SS output.
*
* @return none
*/
void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
SPIx->CTLR2 |= CTLR2_SSOE_Set;
}
else
{
SPIx->CTLR2 &= CTLR2_SSOE_Reset;
}
}
/*********************************************************************
* @fn SPI_DataSizeConfig
*
* @brief Configures the data size for the selected SPI.
*
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
* SPI_DataSize - specifies the SPI data size.
* SPI_DataSize_16b - Set data frame format to 16bit.
* SPI_DataSize_8b - Set data frame format to 8bit.
*
* @return none
*/
void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize)
{
SPIx->CTLR1 &= (uint16_t)~SPI_DataSize_16b;
SPIx->CTLR1 |= SPI_DataSize;
}
/*********************************************************************
* @fn SPI_TransmitCRC
*
* @brief Transmit the SPIx CRC value.
*
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
*
* @return none
*/
void SPI_TransmitCRC(SPI_TypeDef *SPIx)
{
SPIx->CTLR1 |= CTLR1_CRCNext_Set;
}
/*********************************************************************
* @fn SPI_CalculateCRC
*
* @brief Enables or disables the CRC value calculation of the transferred bytes.
*
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
* NewState - new state of the SPIx CRC value calculation.
*
* @return none
*/
void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
SPIx->CTLR1 |= CTLR1_CRCEN_Set;
}
else
{
SPIx->CTLR1 &= CTLR1_CRCEN_Reset;
}
}
/*********************************************************************
* @fn SPI_GetCRC
*
* @brief Returns the transmit or the receive CRC register value for the specified SPI.
*
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
* SPI_CRC - specifies the CRC register to be read.
* SPI_CRC_Tx - Selects Tx CRC register.
* SPI_CRC_Rx - Selects Rx CRC register.
*
* @return crcreg: The selected CRC register value.
*/
uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC)
{
uint16_t crcreg = 0;
if(SPI_CRC != SPI_CRC_Rx)
{
crcreg = SPIx->TCRCR;
}
else
{
crcreg = SPIx->RCRCR;
}
return crcreg;
}
/*********************************************************************
* @fn SPI_GetCRCPolynomial
*
* @brief Returns the CRC Polynomial register value for the specified SPI.
*
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
*
* @return SPIx->CRCR - The CRC Polynomial register value.
*/
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx)
{
return SPIx->CRCR;
}
/*********************************************************************
* @fn SPI_BiDirectionalLineConfig
*
* @brief Selects the data transfer direction in bi-directional mode
* for the specified SPI.
*
* @param SPIx - where x can be 1, 2 or 3 to select the SPI peripheral.
* SPI_Direction - specifies the data transfer direction in
* bi-directional mode.
* SPI_Direction_Tx - Selects Tx transmission direction.
* SPI_Direction_Rx - Selects Rx receive direction.
*
* @return none
*/
void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction)
{
if(SPI_Direction == SPI_Direction_Tx)
{
SPIx->CTLR1 |= SPI_Direction_Tx;
}
else
{
SPIx->CTLR1 &= SPI_Direction_Rx;
}
}
/*********************************************************************
* @fn SPI_I2S_GetFlagStatus
*
* @brief Checks whether the specified SPI/I2S flag is set or not.
*
* @param SPIx - where x can be
* - 1, 2 or 3 in SPI mode.
* - 2 or 3 in I2S mode.
* SPI_I2S_FLAG - specifies the SPI/I2S flag to check.
* SPI_I2S_FLAG_TXE - Transmit buffer empty flag.
* SPI_I2S_FLAG_RXNE - Receive buffer not empty flag.
* SPI_I2S_FLAG_BSY - Busy flag.
* SPI_I2S_FLAG_OVR - Overrun flag.
* SPI_FLAG_MODF - Mode Fault flag.
* SPI_FLAG_CRCERR - CRC Error flag.
* I2S_FLAG_UDR - Underrun Error flag.
* I2S_FLAG_CHSIDE - Channel Side flag.
*
* @return FlagStatus: SET or RESET.
*/
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
{
FlagStatus bitstatus = RESET;
if((SPIx->STATR & SPI_I2S_FLAG) != (uint16_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn SPI_I2S_ClearFlag
*
* @brief Clears the SPIx CRC Error (CRCERR) flag.
*
* @param SPIx - where x can be
* - 1, 2 or 3 in SPI mode.
* - 2 or 3 in I2S mode.
* SPI_I2S_FLAG - specifies the SPI flag to clear.
* SPI_FLAG_CRCERR - CRC Error flag.
* Note-
* - OVR (OverRun error) flag is cleared by software sequence: a read
* operation to SPI_DATAR register (SPI_I2S_ReceiveData()) followed by a read
* operation to SPI_STATR register (SPI_I2S_GetFlagStatus()).
* - UDR (UnderRun error) flag is cleared by a read operation to
* SPI_STATR register (SPI_I2S_GetFlagStatus()).
* - MODF (Mode Fault) flag is cleared by software sequence: a read/write
* operation to SPI_STATR register (SPI_I2S_GetFlagStatus()) followed by a
* write operation to SPI_CTLR1 register (SPI_Cmd() to enable the SPI).
* @return FlagStatus: SET or RESET.
*/
void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG)
{
SPIx->STATR = (uint16_t)~SPI_I2S_FLAG;
}
/*********************************************************************
* @fn SPI_I2S_GetITStatus
*
* @brief Checks whether the specified SPI/I2S interrupt has occurred or not.
*
* @param SPIx - where x can be
* - 1, 2 or 3 in SPI mode.
* - 2 or 3 in I2S mode.
* SPI_I2S_IT - specifies the SPI/I2S interrupt source to check..
* SPI_I2S_IT_TXE - Transmit buffer empty interrupt.
* SPI_I2S_IT_RXNE - Receive buffer not empty interrupt.
* SPI_I2S_IT_OVR - Overrun interrupt.
* SPI_IT_MODF - Mode Fault interrupt.
* SPI_IT_CRCERR - CRC Error interrupt.
* I2S_IT_UDR - Underrun Error interrupt.
*
* @return FlagStatus: SET or RESET.
*/
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
{
ITStatus bitstatus = RESET;
uint16_t itpos = 0, itmask = 0, enablestatus = 0;
itpos = 0x01 << (SPI_I2S_IT & 0x0F);
itmask = SPI_I2S_IT >> 4;
itmask = 0x01 << itmask;
enablestatus = (SPIx->CTLR2 & itmask);
if(((SPIx->STATR & itpos) != (uint16_t)RESET) && enablestatus)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn SPI_I2S_ClearITPendingBit
*
* @brief Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
*
* @param SPIx - where x can be
* - 1, 2 or 3 in SPI mode.
* SPI_I2S_IT - specifies the SPI interrupt pending bit to clear.
* SPI_IT_CRCERR - CRC Error interrupt.
* Note-
* - OVR (OverRun Error) interrupt pending bit is cleared by software
* sequence: a read operation to SPI_DATAR register (SPI_I2S_ReceiveData())
* followed by a read operation to SPI_STATR register (SPI_I2S_GetITStatus()).
* - UDR (UnderRun Error) interrupt pending bit is cleared by a read
* operation to SPI_STATR register (SPI_I2S_GetITStatus()).
* - MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
* a read/write operation to SPI_STATR register (SPI_I2S_GetITStatus())
* followed by a write operation to SPI_CTLR1 register (SPI_Cmd() to enable
* the SPI).
* @return none
*/
void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT)
{
uint16_t itpos = 0;
itpos = 0x01 << (SPI_I2S_IT & 0x0F);
SPIx->STATR = (uint16_t)~itpos;
}

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_spi.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* SPI firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_SPI_H
#define __CH32V20x_SPI_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v20x.h"
/* SPI Init structure definition */
typedef struct
{
uint16_t SPI_Direction; /* Specifies the SPI unidirectional or bidirectional data mode.
This parameter can be a value of @ref SPI_data_direction */
uint16_t SPI_Mode; /* Specifies the SPI operating mode.
This parameter can be a value of @ref SPI_mode */
uint16_t SPI_DataSize; /* Specifies the SPI data size.
This parameter can be a value of @ref SPI_data_size */
uint16_t SPI_CPOL; /* Specifies the serial clock steady state.
This parameter can be a value of @ref SPI_Clock_Polarity */
uint16_t SPI_CPHA; /* Specifies the clock active edge for the bit capture.
This parameter can be a value of @ref SPI_Clock_Phase */
uint16_t SPI_NSS; /* Specifies whether the NSS signal is managed by
hardware (NSS pin) or by software using the SSI bit.
This parameter can be a value of @ref SPI_Slave_Select_management */
uint16_t SPI_BaudRatePrescaler; /* Specifies the Baud Rate prescaler value which will be
used to configure the transmit and receive SCK clock.
This parameter can be a value of @ref SPI_BaudRate_Prescaler.
@note The communication clock is derived from the master
clock. The slave clock does not need to be set. */
uint16_t SPI_FirstBit; /* Specifies whether data transfers start from MSB or LSB bit.
This parameter can be a value of @ref SPI_MSB_LSB_transmission */
uint16_t SPI_CRCPolynomial; /* Specifies the polynomial used for the CRC calculation. */
} SPI_InitTypeDef;
/* I2S Init structure definition */
typedef struct
{
uint16_t I2S_Mode; /* Specifies the I2S operating mode.
This parameter can be a value of @ref I2S_Mode */
uint16_t I2S_Standard; /* Specifies the standard used for the I2S communication.
This parameter can be a value of @ref I2S_Standard */
uint16_t I2S_DataFormat; /* Specifies the data format for the I2S communication.
This parameter can be a value of @ref I2S_Data_Format */
uint16_t I2S_MCLKOutput; /* Specifies whether the I2S MCLK output is enabled or not.
This parameter can be a value of @ref I2S_MCLK_Output */
uint32_t I2S_AudioFreq; /* Specifies the frequency selected for the I2S communication.
This parameter can be a value of @ref I2S_Audio_Frequency */
uint16_t I2S_CPOL; /* Specifies the idle state of the I2S clock.
This parameter can be a value of @ref I2S_Clock_Polarity */
} I2S_InitTypeDef;
/* SPI_data_direction */
#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
#define SPI_Direction_2Lines_RxOnly ((uint16_t)0x0400)
#define SPI_Direction_1Line_Rx ((uint16_t)0x8000)
#define SPI_Direction_1Line_Tx ((uint16_t)0xC000)
/* SPI_mode */
#define SPI_Mode_Master ((uint16_t)0x0104)
#define SPI_Mode_Slave ((uint16_t)0x0000)
/* SPI_data_size */
#define SPI_DataSize_16b ((uint16_t)0x0800)
#define SPI_DataSize_8b ((uint16_t)0x0000)
/* SPI_Clock_Polarity */
#define SPI_CPOL_Low ((uint16_t)0x0000)
#define SPI_CPOL_High ((uint16_t)0x0002)
/* SPI_Clock_Phase */
#define SPI_CPHA_1Edge ((uint16_t)0x0000)
#define SPI_CPHA_2Edge ((uint16_t)0x0001)
/* SPI_Slave_Select_management */
#define SPI_NSS_Soft ((uint16_t)0x0200)
#define SPI_NSS_Hard ((uint16_t)0x0000)
/* SPI_BaudRate_Prescaler */
#define SPI_BaudRatePrescaler_2 ((uint16_t)0x0000)
#define SPI_BaudRatePrescaler_4 ((uint16_t)0x0008)
#define SPI_BaudRatePrescaler_8 ((uint16_t)0x0010)
#define SPI_BaudRatePrescaler_16 ((uint16_t)0x0018)
#define SPI_BaudRatePrescaler_32 ((uint16_t)0x0020)
#define SPI_BaudRatePrescaler_64 ((uint16_t)0x0028)
#define SPI_BaudRatePrescaler_128 ((uint16_t)0x0030)
#define SPI_BaudRatePrescaler_256 ((uint16_t)0x0038)
/* SPI_MSB_LSB_transmission */
#define SPI_FirstBit_MSB ((uint16_t)0x0000)
#define SPI_FirstBit_LSB ((uint16_t)0x0080)
/* I2S_Mode */
#define I2S_Mode_SlaveTx ((uint16_t)0x0000)
#define I2S_Mode_SlaveRx ((uint16_t)0x0100)
#define I2S_Mode_MasterTx ((uint16_t)0x0200)
#define I2S_Mode_MasterRx ((uint16_t)0x0300)
/* I2S_Standard */
#define I2S_Standard_Phillips ((uint16_t)0x0000)
#define I2S_Standard_MSB ((uint16_t)0x0010)
#define I2S_Standard_LSB ((uint16_t)0x0020)
#define I2S_Standard_PCMShort ((uint16_t)0x0030)
#define I2S_Standard_PCMLong ((uint16_t)0x00B0)
/* I2S_Data_Format */
#define I2S_DataFormat_16b ((uint16_t)0x0000)
#define I2S_DataFormat_16bextended ((uint16_t)0x0001)
#define I2S_DataFormat_24b ((uint16_t)0x0003)
#define I2S_DataFormat_32b ((uint16_t)0x0005)
/* I2S_MCLK_Output */
#define I2S_MCLKOutput_Enable ((uint16_t)0x0200)
#define I2S_MCLKOutput_Disable ((uint16_t)0x0000)
/* I2S_Audio_Frequency */
#define I2S_AudioFreq_192k ((uint32_t)192000)
#define I2S_AudioFreq_96k ((uint32_t)96000)
#define I2S_AudioFreq_48k ((uint32_t)48000)
#define I2S_AudioFreq_44k ((uint32_t)44100)
#define I2S_AudioFreq_32k ((uint32_t)32000)
#define I2S_AudioFreq_22k ((uint32_t)22050)
#define I2S_AudioFreq_16k ((uint32_t)16000)
#define I2S_AudioFreq_11k ((uint32_t)11025)
#define I2S_AudioFreq_8k ((uint32_t)8000)
#define I2S_AudioFreq_Default ((uint32_t)2)
/* I2S_Clock_Polarity */
#define I2S_CPOL_Low ((uint16_t)0x0000)
#define I2S_CPOL_High ((uint16_t)0x0008)
/* SPI_I2S_DMA_transfer_requests */
#define SPI_I2S_DMAReq_Tx ((uint16_t)0x0002)
#define SPI_I2S_DMAReq_Rx ((uint16_t)0x0001)
/* SPI_NSS_internal_software_management */
#define SPI_NSSInternalSoft_Set ((uint16_t)0x0100)
#define SPI_NSSInternalSoft_Reset ((uint16_t)0xFEFF)
/* SPI_CRC_Transmit_Receive */
#define SPI_CRC_Tx ((uint8_t)0x00)
#define SPI_CRC_Rx ((uint8_t)0x01)
/* SPI_direction_transmit_receive */
#define SPI_Direction_Rx ((uint16_t)0xBFFF)
#define SPI_Direction_Tx ((uint16_t)0x4000)
/* SPI_I2S_interrupts_definition */
#define SPI_I2S_IT_TXE ((uint8_t)0x71)
#define SPI_I2S_IT_RXNE ((uint8_t)0x60)
#define SPI_I2S_IT_ERR ((uint8_t)0x50)
#define SPI_I2S_IT_OVR ((uint8_t)0x56)
#define SPI_IT_MODF ((uint8_t)0x55)
#define SPI_IT_CRCERR ((uint8_t)0x54)
#define I2S_IT_UDR ((uint8_t)0x53)
/* SPI_I2S_flags_definition */
#define SPI_I2S_FLAG_RXNE ((uint16_t)0x0001)
#define SPI_I2S_FLAG_TXE ((uint16_t)0x0002)
#define I2S_FLAG_CHSIDE ((uint16_t)0x0004)
#define I2S_FLAG_UDR ((uint16_t)0x0008)
#define SPI_FLAG_CRCERR ((uint16_t)0x0010)
#define SPI_FLAG_MODF ((uint16_t)0x0020)
#define SPI_I2S_FLAG_OVR ((uint16_t)0x0040)
#define SPI_I2S_FLAG_BSY ((uint16_t)0x0080)
void SPI_I2S_DeInit(SPI_TypeDef *SPIx);
void SPI_Init(SPI_TypeDef *SPIx, SPI_InitTypeDef *SPI_InitStruct);
void I2S_Init(SPI_TypeDef *SPIx, I2S_InitTypeDef *I2S_InitStruct);
void SPI_StructInit(SPI_InitTypeDef *SPI_InitStruct);
void I2S_StructInit(I2S_InitTypeDef *I2S_InitStruct);
void SPI_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState);
void I2S_Cmd(SPI_TypeDef *SPIx, FunctionalState NewState);
void SPI_I2S_ITConfig(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
void SPI_I2S_DMACmd(SPI_TypeDef *SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
void SPI_I2S_SendData(SPI_TypeDef *SPIx, uint16_t Data);
uint16_t SPI_I2S_ReceiveData(SPI_TypeDef *SPIx);
void SPI_NSSInternalSoftwareConfig(SPI_TypeDef *SPIx, uint16_t SPI_NSSInternalSoft);
void SPI_SSOutputCmd(SPI_TypeDef *SPIx, FunctionalState NewState);
void SPI_DataSizeConfig(SPI_TypeDef *SPIx, uint16_t SPI_DataSize);
void SPI_TransmitCRC(SPI_TypeDef *SPIx);
void SPI_CalculateCRC(SPI_TypeDef *SPIx, FunctionalState NewState);
uint16_t SPI_GetCRC(SPI_TypeDef *SPIx, uint8_t SPI_CRC);
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef *SPIx);
void SPI_BiDirectionalLineConfig(SPI_TypeDef *SPIx, uint16_t SPI_Direction);
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG);
void SPI_I2S_ClearFlag(SPI_TypeDef *SPIx, uint16_t SPI_I2S_FLAG);
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT);
void SPI_I2S_ClearITPendingBit(SPI_TypeDef *SPIx, uint8_t SPI_I2S_IT);
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_tim.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : This file contains all the functions prototypes for the
* TIM firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_TIM_H
#define __CH32V20x_TIM_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v20x.h"
/* TIM Time Base Init structure definition */
typedef struct
{
uint16_t TIM_Prescaler; /* Specifies the prescaler value used to divide the TIM clock.
This parameter can be a number between 0x0000 and 0xFFFF */
uint16_t TIM_CounterMode; /* Specifies the counter mode.
This parameter can be a value of @ref TIM_Counter_Mode */
uint16_t TIM_Period; /* Specifies the period value to be loaded into the active
Auto-Reload Register at the next update event.
This parameter must be a number between 0x0000 and 0xFFFF. */
uint16_t TIM_ClockDivision; /* Specifies the clock division.
This parameter can be a value of @ref TIM_Clock_Division_CKD */
uint8_t TIM_RepetitionCounter; /* Specifies the repetition counter value. Each time the RCR downcounter
reaches zero, an update event is generated and counting restarts
from the RCR value (N).
This means in PWM mode that (N+1) corresponds to:
- the number of PWM periods in edge-aligned mode
- the number of half PWM period in center-aligned mode
This parameter must be a number between 0x00 and 0xFF.
@note This parameter is valid only for TIM1 and TIM8. */
} TIM_TimeBaseInitTypeDef;
/* TIM Output Compare Init structure definition */
typedef struct
{
uint16_t TIM_OCMode; /* Specifies the TIM mode.
This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
uint16_t TIM_OutputState; /* Specifies the TIM Output Compare state.
This parameter can be a value of @ref TIM_Output_Compare_state */
uint16_t TIM_OutputNState; /* Specifies the TIM complementary Output Compare state.
This parameter can be a value of @ref TIM_Output_Compare_N_state
@note This parameter is valid only for TIM1 and TIM8. */
uint16_t TIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register.
This parameter can be a number between 0x0000 and 0xFFFF */
uint16_t TIM_OCPolarity; /* Specifies the output polarity.
This parameter can be a value of @ref TIM_Output_Compare_Polarity */
uint16_t TIM_OCNPolarity; /* Specifies the complementary output polarity.
This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
@note This parameter is valid only for TIM1 and TIM8. */
uint16_t TIM_OCIdleState; /* Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_Output_Compare_Idle_State
@note This parameter is valid only for TIM1 and TIM8. */
uint16_t TIM_OCNIdleState; /* Specifies the TIM Output Compare pin state during Idle state.
This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
@note This parameter is valid only for TIM1 and TIM8. */
} TIM_OCInitTypeDef;
/* TIM Input Capture Init structure definition */
typedef struct
{
uint16_t TIM_Channel; /* Specifies the TIM channel.
This parameter can be a value of @ref TIM_Channel */
uint16_t TIM_ICPolarity; /* Specifies the active edge of the input signal.
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
uint16_t TIM_ICSelection; /* Specifies the input.
This parameter can be a value of @ref TIM_Input_Capture_Selection */
uint16_t TIM_ICPrescaler; /* Specifies the Input Capture Prescaler.
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
uint16_t TIM_ICFilter; /* Specifies the input capture filter.
This parameter can be a number between 0x0 and 0xF */
} TIM_ICInitTypeDef;
/* BDTR structure definition */
typedef struct
{
uint16_t TIM_OSSRState; /* Specifies the Off-State selection used in Run mode.
This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */
uint16_t TIM_OSSIState; /* Specifies the Off-State used in Idle state.
This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */
uint16_t TIM_LOCKLevel; /* Specifies the LOCK level parameters.
This parameter can be a value of @ref Lock_level */
uint16_t TIM_DeadTime; /* Specifies the delay time between the switching-off and the
switching-on of the outputs.
This parameter can be a number between 0x00 and 0xFF */
uint16_t TIM_Break; /* Specifies whether the TIM Break input is enabled or not.
This parameter can be a value of @ref Break_Input_enable_disable */
uint16_t TIM_BreakPolarity; /* Specifies the TIM Break Input pin polarity.
This parameter can be a value of @ref Break_Polarity */
uint16_t TIM_AutomaticOutput; /* Specifies whether the TIM Automatic Output feature is enabled or not.
This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
} TIM_BDTRInitTypeDef;
/* TIM_Output_Compare_and_PWM_modes */
#define TIM_OCMode_Timing ((uint16_t)0x0000)
#define TIM_OCMode_Active ((uint16_t)0x0010)
#define TIM_OCMode_Inactive ((uint16_t)0x0020)
#define TIM_OCMode_Toggle ((uint16_t)0x0030)
#define TIM_OCMode_PWM1 ((uint16_t)0x0060)
#define TIM_OCMode_PWM2 ((uint16_t)0x0070)
/* TIM_One_Pulse_Mode */
#define TIM_OPMode_Single ((uint16_t)0x0008)
#define TIM_OPMode_Repetitive ((uint16_t)0x0000)
/* TIM_Channel */
#define TIM_Channel_1 ((uint16_t)0x0000)
#define TIM_Channel_2 ((uint16_t)0x0004)
#define TIM_Channel_3 ((uint16_t)0x0008)
#define TIM_Channel_4 ((uint16_t)0x000C)
/* TIM_Clock_Division_CKD */
#define TIM_CKD_DIV1 ((uint16_t)0x0000)
#define TIM_CKD_DIV2 ((uint16_t)0x0100)
#define TIM_CKD_DIV4 ((uint16_t)0x0200)
/* TIM_Counter_Mode */
#define TIM_CounterMode_Up ((uint16_t)0x0000)
#define TIM_CounterMode_Down ((uint16_t)0x0010)
#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
/* TIM_Output_Compare_Polarity */
#define TIM_OCPolarity_High ((uint16_t)0x0000)
#define TIM_OCPolarity_Low ((uint16_t)0x0002)
/* TIM_Output_Compare_N_Polarity */
#define TIM_OCNPolarity_High ((uint16_t)0x0000)
#define TIM_OCNPolarity_Low ((uint16_t)0x0008)
/* TIM_Output_Compare_state */
#define TIM_OutputState_Disable ((uint16_t)0x0000)
#define TIM_OutputState_Enable ((uint16_t)0x0001)
/* TIM_Output_Compare_N_state */
#define TIM_OutputNState_Disable ((uint16_t)0x0000)
#define TIM_OutputNState_Enable ((uint16_t)0x0004)
/* TIM_Capture_Compare_state */
#define TIM_CCx_Enable ((uint16_t)0x0001)
#define TIM_CCx_Disable ((uint16_t)0x0000)
/* TIM_Capture_Compare_N_state */
#define TIM_CCxN_Enable ((uint16_t)0x0004)
#define TIM_CCxN_Disable ((uint16_t)0x0000)
/* Break_Input_enable_disable */
#define TIM_Break_Enable ((uint16_t)0x1000)
#define TIM_Break_Disable ((uint16_t)0x0000)
/* Break_Polarity */
#define TIM_BreakPolarity_Low ((uint16_t)0x0000)
#define TIM_BreakPolarity_High ((uint16_t)0x2000)
/* TIM_AOE_Bit_Set_Reset */
#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
/* Lock_level */
#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
#define TIM_LOCKLevel_1 ((uint16_t)0x0100)
#define TIM_LOCKLevel_2 ((uint16_t)0x0200)
#define TIM_LOCKLevel_3 ((uint16_t)0x0300)
/* OSSI_Off_State_Selection_for_Idle_mode_state */
#define TIM_OSSIState_Enable ((uint16_t)0x0400)
#define TIM_OSSIState_Disable ((uint16_t)0x0000)
/* OSSR_Off_State_Selection_for_Run_mode_state */
#define TIM_OSSRState_Enable ((uint16_t)0x0800)
#define TIM_OSSRState_Disable ((uint16_t)0x0000)
/* TIM_Output_Compare_Idle_State */
#define TIM_OCIdleState_Set ((uint16_t)0x0100)
#define TIM_OCIdleState_Reset ((uint16_t)0x0000)
/* TIM_Output_Compare_N_Idle_State */
#define TIM_OCNIdleState_Set ((uint16_t)0x0200)
#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
/* TIM_Input_Capture_Polarity */
#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
#define TIM_ICPolarity_Falling ((uint16_t)0x0002)
#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
/* TIM_Input_Capture_Selection */
#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be \
connected to IC1, IC2, IC3 or IC4, respectively */
#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be \
connected to IC2, IC1, IC4 or IC3, respectively. */
#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
/* TIM_Input_Capture_Prescaler */
#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */
#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */
#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */
#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */
/* TIM_interrupt_sources */
#define TIM_IT_Update ((uint16_t)0x0001)
#define TIM_IT_CC1 ((uint16_t)0x0002)
#define TIM_IT_CC2 ((uint16_t)0x0004)
#define TIM_IT_CC3 ((uint16_t)0x0008)
#define TIM_IT_CC4 ((uint16_t)0x0010)
#define TIM_IT_COM ((uint16_t)0x0020)
#define TIM_IT_Trigger ((uint16_t)0x0040)
#define TIM_IT_Break ((uint16_t)0x0080)
/* TIM_DMA_Base_address */
#define TIM_DMABase_CR1 ((uint16_t)0x0000)
#define TIM_DMABase_CR2 ((uint16_t)0x0001)
#define TIM_DMABase_SMCR ((uint16_t)0x0002)
#define TIM_DMABase_DIER ((uint16_t)0x0003)
#define TIM_DMABase_SR ((uint16_t)0x0004)
#define TIM_DMABase_EGR ((uint16_t)0x0005)
#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
#define TIM_DMABase_CCER ((uint16_t)0x0008)
#define TIM_DMABase_CNT ((uint16_t)0x0009)
#define TIM_DMABase_PSC ((uint16_t)0x000A)
#define TIM_DMABase_ARR ((uint16_t)0x000B)
#define TIM_DMABase_RCR ((uint16_t)0x000C)
#define TIM_DMABase_CCR1 ((uint16_t)0x000D)
#define TIM_DMABase_CCR2 ((uint16_t)0x000E)
#define TIM_DMABase_CCR3 ((uint16_t)0x000F)
#define TIM_DMABase_CCR4 ((uint16_t)0x0010)
#define TIM_DMABase_BDTR ((uint16_t)0x0011)
#define TIM_DMABase_DCR ((uint16_t)0x0012)
/* TIM_DMA_Burst_Length */
#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
/* TIM_DMA_sources */
#define TIM_DMA_Update ((uint16_t)0x0100)
#define TIM_DMA_CC1 ((uint16_t)0x0200)
#define TIM_DMA_CC2 ((uint16_t)0x0400)
#define TIM_DMA_CC3 ((uint16_t)0x0800)
#define TIM_DMA_CC4 ((uint16_t)0x1000)
#define TIM_DMA_COM ((uint16_t)0x2000)
#define TIM_DMA_Trigger ((uint16_t)0x4000)
/* TIM_External_Trigger_Prescaler */
#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
/* TIM_Internal_Trigger_Selection */
#define TIM_TS_ITR0 ((uint16_t)0x0000)
#define TIM_TS_ITR1 ((uint16_t)0x0010)
#define TIM_TS_ITR2 ((uint16_t)0x0020)
#define TIM_TS_ITR3 ((uint16_t)0x0030)
#define TIM_TS_TI1F_ED ((uint16_t)0x0040)
#define TIM_TS_TI1FP1 ((uint16_t)0x0050)
#define TIM_TS_TI2FP2 ((uint16_t)0x0060)
#define TIM_TS_ETRF ((uint16_t)0x0070)
/* TIM_TIx_External_Clock_Source */
#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
/* TIM_External_Trigger_Polarity */
#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
/* TIM_Prescaler_Reload_Mode */
#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
/* TIM_Forced_Action */
#define TIM_ForcedAction_Active ((uint16_t)0x0050)
#define TIM_ForcedAction_InActive ((uint16_t)0x0040)
/* TIM_Encoder_Mode */
#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
/* TIM_Event_Source */
#define TIM_EventSource_Update ((uint16_t)0x0001)
#define TIM_EventSource_CC1 ((uint16_t)0x0002)
#define TIM_EventSource_CC2 ((uint16_t)0x0004)
#define TIM_EventSource_CC3 ((uint16_t)0x0008)
#define TIM_EventSource_CC4 ((uint16_t)0x0010)
#define TIM_EventSource_COM ((uint16_t)0x0020)
#define TIM_EventSource_Trigger ((uint16_t)0x0040)
#define TIM_EventSource_Break ((uint16_t)0x0080)
/* TIM_Update_Source */
#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow \
or the setting of UG bit, or an update generation \
through the slave mode controller. */
#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */
/* TIM_Output_Compare_Preload_State */
#define TIM_OCPreload_Enable ((uint16_t)0x0008)
#define TIM_OCPreload_Disable ((uint16_t)0x0000)
/* TIM_Output_Compare_Fast_State */
#define TIM_OCFast_Enable ((uint16_t)0x0004)
#define TIM_OCFast_Disable ((uint16_t)0x0000)
/* TIM_Output_Compare_Clear_State */
#define TIM_OCClear_Enable ((uint16_t)0x0080)
#define TIM_OCClear_Disable ((uint16_t)0x0000)
/* TIM_Trigger_Output_Source */
#define TIM_TRGOSource_Reset ((uint16_t)0x0000)
#define TIM_TRGOSource_Enable ((uint16_t)0x0010)
#define TIM_TRGOSource_Update ((uint16_t)0x0020)
#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
/* TIM_Slave_Mode */
#define TIM_SlaveMode_Reset ((uint16_t)0x0004)
#define TIM_SlaveMode_Gated ((uint16_t)0x0005)
#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
#define TIM_SlaveMode_External1 ((uint16_t)0x0007)
/* TIM_Master_Slave_Mode */
#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
/* TIM_Flags */
#define TIM_FLAG_Update ((uint16_t)0x0001)
#define TIM_FLAG_CC1 ((uint16_t)0x0002)
#define TIM_FLAG_CC2 ((uint16_t)0x0004)
#define TIM_FLAG_CC3 ((uint16_t)0x0008)
#define TIM_FLAG_CC4 ((uint16_t)0x0010)
#define TIM_FLAG_COM ((uint16_t)0x0020)
#define TIM_FLAG_Trigger ((uint16_t)0x0040)
#define TIM_FLAG_Break ((uint16_t)0x0080)
#define TIM_FLAG_CC1OF ((uint16_t)0x0200)
#define TIM_FLAG_CC2OF ((uint16_t)0x0400)
#define TIM_FLAG_CC3OF ((uint16_t)0x0800)
#define TIM_FLAG_CC4OF ((uint16_t)0x1000)
/* TIM_Legacy */
#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
void TIM_DeInit(TIM_TypeDef *TIMx);
void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct);
void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct);
void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct);
void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct);
void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct);
void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct);
void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct);
void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct);
void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct);
void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct);
void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState);
void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState);
void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState);
void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource);
void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
void TIM_InternalClockConfig(TIM_TypeDef *TIMx);
void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource);
void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource,
uint16_t TIM_ICPolarity, uint16_t ICFilter);
void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
uint16_t ExtTRGFilter);
void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler,
uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
uint16_t ExtTRGFilter);
void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode);
void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource);
void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode,
uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction);
void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction);
void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction);
void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction);
void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState);
void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState);
void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState);
void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState);
void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload);
void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload);
void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload);
void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload);
void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast);
void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast);
void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast);
void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast);
void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear);
void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear);
void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear);
void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear);
void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity);
void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity);
void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity);
void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity);
void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity);
void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity);
void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity);
void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState);
void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource);
void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState);
void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode);
void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource);
void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode);
void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode);
void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter);
void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload);
void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1);
void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2);
void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3);
void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4);
void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC);
void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC);
void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC);
void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC);
void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD);
uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx);
uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx);
uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx);
uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx);
uint16_t TIM_GetCounter(TIM_TypeDef *TIMx);
uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx);
FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG);
void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG);
ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT);
void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT);
#ifdef __cplusplus
}
#endif
#endif

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_usart.c
* Author : WCH
* Version : V1.0.0
* Date : 2024/01/06
* Description : This file provides all the USART firmware functions.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include "ch32v20x_usart.h"
#include "ch32v20x_rcc.h"
/* USART_Private_Defines */
#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */
#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */
#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */
#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */
#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */
#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */
#define CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CTLR1 Mask */
#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */
#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */
#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */
#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */
#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CTLR2 STOP Bits Mask */
#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CTLR2 Clock Mask */
#define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */
#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */
#define CTLR3_NACK_Set ((uint16_t)0x0010) /* USART SC NACK Enable Mask */
#define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */
#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */
#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */
#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */
#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CTLR3 Mask */
#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */
#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */
#define GPR_LSB_Mask ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */
#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */
#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */
/*********************************************************************
* @fn USART_DeInit
*
* @brief Deinitializes the USARTx peripheral registers to their default
* reset values.
*
* @param USARTx - where x can be 1, 2 or 3 to select the UART peripheral.
*
* @return none
*/
void USART_DeInit(USART_TypeDef *USARTx)
{
if(USARTx == USART1)
{
RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
}
else if(USARTx == USART2)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
}
else if(USARTx == USART3)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
}
else if(USARTx == UART4)
{
RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
}
}
/*********************************************************************
* @fn USART_Init
*
* @brief Initializes the USARTx peripheral according to the specified
* parameters in the USART_InitStruct.
*
* @param USARTx - where x can be 1, 2 or 3 to select the UART peripheral.
* USART_InitStruct - pointer to a USART_InitTypeDef structure
* that contains the configuration information for the specified
* USART peripheral.
*
* @return none
*/
void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct)
{
uint32_t tmpreg = 0x00, apbclock = 0x00;
uint32_t integerdivider = 0x00;
uint32_t fractionaldivider = 0x00;
uint32_t usartxbase = 0;
RCC_ClocksTypeDef RCC_ClocksStatus;
if(USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)
{
}
usartxbase = (uint32_t)USARTx;
tmpreg = USARTx->CTLR2;
tmpreg &= CTLR2_STOP_CLEAR_Mask;
tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
USARTx->CTLR2 = (uint16_t)tmpreg;
tmpreg = USARTx->CTLR1;
tmpreg &= CTLR1_CLEAR_Mask;
tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
USART_InitStruct->USART_Mode;
USARTx->CTLR1 = (uint16_t)tmpreg;
tmpreg = USARTx->CTLR3;
tmpreg &= CTLR3_CLEAR_Mask;
tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
USARTx->CTLR3 = (uint16_t)tmpreg;
RCC_GetClocksFreq(&RCC_ClocksStatus);
if(usartxbase == USART1_BASE)
{
apbclock = RCC_ClocksStatus.PCLK2_Frequency;
}
else
{
apbclock = RCC_ClocksStatus.PCLK1_Frequency;
}
integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));
tmpreg = (integerdivider / 100) << 4;
fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
USARTx->BRR = (uint16_t)tmpreg;
}
/*********************************************************************
* @fn USART_StructInit
*
* @brief Fills each USART_InitStruct member with its default value.
*
* @param USART_InitStruct: pointer to a USART_InitTypeDef structure
* which will be initialized.
*
* @return none
*/
void USART_StructInit(USART_InitTypeDef *USART_InitStruct)
{
USART_InitStruct->USART_BaudRate = 9600;
USART_InitStruct->USART_WordLength = USART_WordLength_8b;
USART_InitStruct->USART_StopBits = USART_StopBits_1;
USART_InitStruct->USART_Parity = USART_Parity_No;
USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;
}
/*********************************************************************
* @fn USART_ClockInit
*
* @brief Initializes the USARTx peripheral Clock according to the
* specified parameters in the USART_ClockInitStruct .
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef
* structure that contains the configuration information for the specified
* USART peripheral.
*
* @return none
*/
void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct)
{
uint32_t tmpreg = 0x00;
tmpreg = USARTx->CTLR2;
tmpreg &= CTLR2_CLOCK_CLEAR_Mask;
tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL |
USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;
USARTx->CTLR2 = (uint16_t)tmpreg;
}
/*********************************************************************
* @fn USART_ClockStructInit
*
* @brief Fills each USART_ClockStructInit member with its default value.
*
* @param USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef
* structure which will be initialized.
*
* @return none
*/
void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct)
{
USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
}
/*********************************************************************
* @fn USART_Cmd
*
* @brief Enables or disables the specified USART peripheral.
* reset values (Affects also the I2Ss).
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* NewState: ENABLE or DISABLE.
*
* @return none
*/
void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
USARTx->CTLR1 |= CTLR1_UE_Set;
}
else
{
USARTx->CTLR1 &= CTLR1_UE_Reset;
}
}
/*********************************************************************
* @fn USART_ITConfig
*
* @brief Enables or disables the specified USART interrupts.
* reset values (Affects also the I2Ss).
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* USART_IT - specifies the USART interrupt sources to be enabled or disabled.
* USART_IT_LBD - LIN Break detection interrupt.
* USART_IT_TXE - Transmit Data Register empty interrupt.
* USART_IT_TC - Transmission complete interrupt.
* USART_IT_RXNE - Receive Data register not empty interrupt.
* USART_IT_IDLE - Idle line detection interrupt.
* USART_IT_PE - Parity Error interrupt.
* USART_IT_ERR - Error interrupt.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState)
{
uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
uint32_t usartxbase = 0x00;
usartxbase = (uint32_t)USARTx;
usartreg = (((uint8_t)USART_IT) >> 0x05);
itpos = USART_IT & IT_Mask;
itmask = (((uint32_t)0x01) << itpos);
if(usartreg == 0x01)
{
usartxbase += 0x0C;
}
else if(usartreg == 0x02)
{
usartxbase += 0x10;
}
else
{
usartxbase += 0x14;
}
if(NewState != DISABLE)
{
*(__IO uint32_t *)usartxbase |= itmask;
}
else
{
*(__IO uint32_t *)usartxbase &= ~itmask;
}
}
/*********************************************************************
* @fn USART_DMACmd
*
* @brief Enables or disables the USART DMA interface.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* USART_DMAReq - specifies the DMA request.
* USART_DMAReq_Tx - USART DMA transmit request.
* USART_DMAReq_Rx - USART DMA receive request.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
{
if(NewState != DISABLE)
{
USARTx->CTLR3 |= USART_DMAReq;
}
else
{
USARTx->CTLR3 &= (uint16_t)~USART_DMAReq;
}
}
/*********************************************************************
* @fn USART_SetAddress
*
* @brief Sets the address of the USART node.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* USART_Address - Indicates the address of the USART node.
*
* @return none
*/
void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address)
{
USARTx->CTLR2 &= CTLR2_Address_Mask;
USARTx->CTLR2 |= USART_Address;
}
/*********************************************************************
* @fn USART_WakeUpConfig
*
* @brief Selects the USART WakeUp method.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* USART_WakeUp - specifies the USART wakeup method.
* USART_WakeUp_IdleLine - WakeUp by an idle line detection.
* USART_WakeUp_AddressMark - WakeUp by an address mark.
*
* @return none
*/
void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp)
{
USARTx->CTLR1 &= CTLR1_WAKE_Mask;
USARTx->CTLR1 |= USART_WakeUp;
}
/*********************************************************************
* @fn USART_ReceiverWakeUpCmd
*
* @brief Determines if the USART is in mute mode or not.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
USARTx->CTLR1 |= CTLR1_RWU_Set;
}
else
{
USARTx->CTLR1 &= CTLR1_RWU_Reset;
}
}
/*********************************************************************
* @fn USART_LINBreakDetectLengthConfig
*
* @brief Sets the USART LIN Break detection length.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* USART_LINBreakDetectLength - specifies the LIN break detection length.
* USART_LINBreakDetectLength_10b - 10-bit break detection.
* USART_LINBreakDetectLength_11b - 11-bit break detection.
*
* @return none
*/
void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength)
{
USARTx->CTLR2 &= CTLR2_LBDL_Mask;
USARTx->CTLR2 |= USART_LINBreakDetectLength;
}
/*********************************************************************
* @fn USART_LINCmd
*
* @brief Enables or disables the USART LIN mode.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
USARTx->CTLR2 |= CTLR2_LINEN_Set;
}
else
{
USARTx->CTLR2 &= CTLR2_LINEN_Reset;
}
}
/*********************************************************************
* @fn USART_SendData
*
* @brief Transmits single data through the USARTx peripheral.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* Data - the data to transmit.
*
* @return none
*/
void USART_SendData(USART_TypeDef *USARTx, uint16_t Data)
{
USARTx->DATAR = (Data & (uint16_t)0x01FF);
}
/*********************************************************************
* @fn USART_ReceiveData
*
* @brief Returns the most recent received data by the USARTx peripheral.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
*
* @return The received data.
*/
uint16_t USART_ReceiveData(USART_TypeDef *USARTx)
{
return (uint16_t)(USARTx->DATAR & (uint16_t)0x01FF);
}
/*********************************************************************
* @fn USART_SendBreak
*
* @brief Transmits break characters.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
*
* @return none
*/
void USART_SendBreak(USART_TypeDef *USARTx)
{
USARTx->CTLR1 |= CTLR1_SBK_Set;
}
/*********************************************************************
* @fn USART_SetGuardTime
*
* @brief Sets the specified USART guard time.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* USART_GuardTime - specifies the guard time.
*
* @return none
*/
void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime)
{
USARTx->GPR &= GPR_LSB_Mask;
USARTx->GPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
}
/*********************************************************************
* @fn USART_SetPrescaler
*
* @brief Sets the system clock prescaler.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* USART_Prescaler - specifies the prescaler clock.
*
* @return none
*/
void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler)
{
USARTx->GPR &= GPR_MSB_Mask;
USARTx->GPR |= USART_Prescaler;
}
/*********************************************************************
* @fn USART_SmartCardCmd
*
* @brief Enables or disables the USART Smart Card mode.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
USARTx->CTLR3 |= CTLR3_SCEN_Set;
}
else
{
USARTx->CTLR3 &= CTLR3_SCEN_Reset;
}
}
/*********************************************************************
* @fn USART_SmartCardNACKCmd
*
* @brief Enables or disables NACK transmission.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
USARTx->CTLR3 |= CTLR3_NACK_Set;
}
else
{
USARTx->CTLR3 &= CTLR3_NACK_Reset;
}
}
/*********************************************************************
* @fn USART_HalfDuplexCmd
*
* @brief Enables or disables the USART Half Duplex communication.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
USARTx->CTLR3 |= CTLR3_HDSEL_Set;
}
else
{
USARTx->CTLR3 &= CTLR3_HDSEL_Reset;
}
}
/*********************************************************************
* @fn USART_IrDAConfig
*
* @brief Configures the USART's IrDA interface.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* USART_IrDAMode - specifies the IrDA mode.
* USART_IrDAMode_LowPower.
* USART_IrDAMode_Normal.
*
* @return none
*/
void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode)
{
USARTx->CTLR3 &= CTLR3_IRLP_Mask;
USARTx->CTLR3 |= USART_IrDAMode;
}
/*********************************************************************
* @fn USART_IrDACmd
*
* @brief Enables or disables the USART's IrDA interface.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* NewState - ENABLE or DISABLE.
*
* @return none
*/
void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState)
{
if(NewState != DISABLE)
{
USARTx->CTLR3 |= CTLR3_IREN_Set;
}
else
{
USARTx->CTLR3 &= CTLR3_IREN_Reset;
}
}
/*********************************************************************
* @fn USART_GetFlagStatus
*
* @brief Checks whether the specified USART flag is set or not.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* USART_FLAG - specifies the flag to check.
* USART_FLAG_LBD - LIN Break detection flag.
* USART_FLAG_TXE - Transmit data register empty flag.
* USART_FLAG_TC - Transmission Complete flag.
* USART_FLAG_RXNE - Receive data register not empty flag.
* USART_FLAG_IDLE - Idle Line detection flag.
* USART_FLAG_ORE - OverRun Error flag.
* USART_FLAG_NE - Noise Error flag.
* USART_FLAG_FE - Framing Error flag.
* USART_FLAG_PE - Parity Error flag.
*
* @return bitstatus: SET or RESET
*/
FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG)
{
FlagStatus bitstatus = RESET;
if((USARTx->STATR & USART_FLAG) != (uint16_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn USART_ClearFlag
*
* @brief Clears the USARTx's pending flags.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* USART_FLAG - specifies the flag to clear.
* USART_FLAG_LBD - LIN Break detection flag.
* USART_FLAG_TC - Transmission Complete flag.
* USART_FLAG_RXNE - Receive data register not empty flag.
* Note-
* - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
* error) and IDLE (Idle line detected) flags are cleared by software
* sequence: a read operation to USART_STATR register (USART_GetFlagStatus())
* followed by a read operation to USART_DATAR register (USART_ReceiveData()).
* - RXNE flag can be also cleared by a read to the USART_DATAR register
* (USART_ReceiveData()).
* - TC flag can be also cleared by software sequence: a read operation to
* USART_STATR register (USART_GetFlagStatus()) followed by a write operation
* to USART_DATAR register (USART_SendData()).
* - TXE flag is cleared only by a write to the USART_DATAR register
* (USART_SendData()).
* @return none
*/
void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG)
{
USARTx->STATR = (uint16_t)~USART_FLAG;
}
/*********************************************************************
* @fn USART_GetITStatus
*
* @brief Checks whether the specified USART interrupt has occurred or not.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* USART_IT - specifies the USART interrupt source to check.
* USART_IT_LBD - LIN Break detection interrupt.
* USART_IT_TXE - Tansmit Data Register empty interrupt.
* USART_IT_TC - Transmission complete interrupt.
* USART_IT_RXNE - Receive Data register not empty interrupt.
* USART_IT_IDLE - Idle line detection interrupt.
* USART_IT_ORE_RX - OverRun Error interrupt if the RXNEIE bit is set.
* USART_IT_ORE_ER - OverRun Error interrupt if the EIE bit is set.
* USART_IT_NE - Noise Error interrupt.
* USART_IT_FE - Framing Error interrupt.
* USART_IT_PE - Parity Error interrupt.
*
* @return bitstatus: SET or RESET.
*/
ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT)
{
uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
ITStatus bitstatus = RESET;
usartreg = (((uint8_t)USART_IT) >> 0x05);
itmask = USART_IT & IT_Mask;
itmask = (uint32_t)0x01 << itmask;
if(usartreg == 0x01)
{
itmask &= USARTx->CTLR1;
}
else if(usartreg == 0x02)
{
itmask &= USARTx->CTLR2;
}
else
{
itmask &= USARTx->CTLR3;
}
bitpos = USART_IT >> 0x08;
bitpos = (uint32_t)0x01 << bitpos;
bitpos &= USARTx->STATR;
if((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET))
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*********************************************************************
* @fn USART_ClearITPendingBit
*
* @brief Clears the USARTx's interrupt pending bits.
*
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
* USART_IT - specifies the interrupt pending bit to clear.
* USART_IT_LBD - LIN Break detection interrupt.
* USART_IT_TC - Transmission complete interrupt.
* USART_IT_RXNE - Receive Data register not empty interrupt.
* Note-
* - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
* error) and IDLE (Idle line detected) pending bits are cleared by
* software sequence: a read operation to USART_STATR register
* (USART_GetITStatus()) followed by a read operation to USART_DATAR register
* (USART_ReceiveData()).
* - RXNE pending bit can be also cleared by a read to the USART_DATAR register
* (USART_ReceiveData()).
* - TC pending bit can be also cleared by software sequence: a read
* operation to USART_STATR register (USART_GetITStatus()) followed by a write
* operation to USART_DATAR register (USART_SendData()).
* - TXE pending bit is cleared only by a write to the USART_DATAR register
* (USART_SendData()).
* @return none
*/
void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT)
{
uint16_t bitpos = 0x00, itmask = 0x00;
bitpos = USART_IT >> 0x08;
itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
USARTx->STATR = (uint16_t)~itmask;
}

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/********************************** (C) COPYRIGHT *******************************
* File Name : ch32v20x_usart.h
* Author : WCH
* Version : V1.0.0
* Date : 2024/01/06
* Description : This file contains all the functions prototypes for the
* USART firmware library.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __CH32V20x_USART_H
#define __CH32V20x_USART_H
#ifdef __cplusplus
extern "C" {
#endif
#include "ch32v20x.h"
/* USART Init Structure definition */
typedef struct
{
uint32_t USART_BaudRate; /* This member configures the USART communication baud rate.
The baud rate is computed using the following formula:
- IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
- FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame.
This parameter can be a value of @ref USART_Word_Length */
uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted.
This parameter can be a value of @ref USART_Stop_Bits */
uint16_t USART_Parity; /* Specifies the parity mode.
This parameter can be a value of @ref USART_Parity
@note When parity is enabled, the computed parity is inserted
at the MSB position of the transmitted data (9th bit when
the word length is set to 9 data bits; 8th bit when the
word length is set to 8 data bits). */
uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled.
This parameter can be a value of @ref USART_Mode */
uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled
or disabled.
This parameter can be a value of @ref USART_Hardware_Flow_Control */
} USART_InitTypeDef;
/* USART Clock Init Structure definition */
typedef struct
{
uint16_t USART_Clock; /* Specifies whether the USART clock is enabled or disabled.
This parameter can be a value of @ref USART_Clock */
uint16_t USART_CPOL; /* Specifies the steady state value of the serial clock.
This parameter can be a value of @ref USART_Clock_Polarity */
uint16_t USART_CPHA; /* Specifies the clock transition on which the bit capture is made.
This parameter can be a value of @ref USART_Clock_Phase */
uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
This parameter can be a value of @ref USART_Last_Bit */
} USART_ClockInitTypeDef;
/* USART_Word_Length */
#define USART_WordLength_8b ((uint16_t)0x0000)
#define USART_WordLength_9b ((uint16_t)0x1000)
/* USART_Stop_Bits */
#define USART_StopBits_1 ((uint16_t)0x0000)
#define USART_StopBits_0_5 ((uint16_t)0x1000)
#define USART_StopBits_2 ((uint16_t)0x2000)
#define USART_StopBits_1_5 ((uint16_t)0x3000)
/* USART_Parity */
#define USART_Parity_No ((uint16_t)0x0000)
#define USART_Parity_Even ((uint16_t)0x0400)
#define USART_Parity_Odd ((uint16_t)0x0600)
/* USART_Mode */
#define USART_Mode_Rx ((uint16_t)0x0004)
#define USART_Mode_Tx ((uint16_t)0x0008)
/* USART_Hardware_Flow_Control */
#define USART_HardwareFlowControl_None ((uint16_t)0x0000)
#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)
/* USART_Clock */
#define USART_Clock_Disable ((uint16_t)0x0000)
#define USART_Clock_Enable ((uint16_t)0x0800)
/* USART_Clock_Polarity */
#define USART_CPOL_Low ((uint16_t)0x0000)
#define USART_CPOL_High ((uint16_t)0x0400)
/* USART_Clock_Phase */
#define USART_CPHA_1Edge ((uint16_t)0x0000)
#define USART_CPHA_2Edge ((uint16_t)0x0200)
/* USART_Last_Bit */
#define USART_LastBit_Disable ((uint16_t)0x0000)
#define USART_LastBit_Enable ((uint16_t)0x0100)
/* USART_Interrupt_definition */
#define USART_IT_PE ((uint16_t)0x0028)
#define USART_IT_TXE ((uint16_t)0x0727)
#define USART_IT_TC ((uint16_t)0x0626)
#define USART_IT_RXNE ((uint16_t)0x0525)
#define USART_IT_ORE_RX ((uint16_t)0x0325)
#define USART_IT_IDLE ((uint16_t)0x0424)
#define USART_IT_LBD ((uint16_t)0x0846)
#define USART_IT_CTS ((uint16_t)0x096A)
#define USART_IT_ERR ((uint16_t)0x0060)
#define USART_IT_ORE_ER ((uint16_t)0x0360)
#define USART_IT_NE ((uint16_t)0x0260)
#define USART_IT_FE ((uint16_t)0x0160)
#define USART_IT_ORE USART_IT_ORE_ER
/* USART_DMA_Requests */
#define USART_DMAReq_Tx ((uint16_t)0x0080)
#define USART_DMAReq_Rx ((uint16_t)0x0040)
/* USART_WakeUp_methods */
#define USART_WakeUp_IdleLine ((uint16_t)0x0000)
#define USART_WakeUp_AddressMark ((uint16_t)0x0800)
/* USART_LIN_Break_Detection_Length */
#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)
/* USART_IrDA_Low_Power */
#define USART_IrDAMode_LowPower ((uint16_t)0x0004)
#define USART_IrDAMode_Normal ((uint16_t)0x0000)
/* USART_Flags */
#define USART_FLAG_CTS ((uint16_t)0x0200)
#define USART_FLAG_LBD ((uint16_t)0x0100)
#define USART_FLAG_TXE ((uint16_t)0x0080)
#define USART_FLAG_TC ((uint16_t)0x0040)
#define USART_FLAG_RXNE ((uint16_t)0x0020)
#define USART_FLAG_IDLE ((uint16_t)0x0010)
#define USART_FLAG_ORE ((uint16_t)0x0008)
#define USART_FLAG_NE ((uint16_t)0x0004)
#define USART_FLAG_FE ((uint16_t)0x0002)
#define USART_FLAG_PE ((uint16_t)0x0001)
void USART_DeInit(USART_TypeDef *USARTx);
void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct);
void USART_StructInit(USART_InitTypeDef *USART_InitStruct);
void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct);
void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct);
void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState);
void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address);
void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp);
void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength);
void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_SendData(USART_TypeDef *USARTx, uint16_t Data);
uint16_t USART_ReceiveData(USART_TypeDef *USARTx);
void USART_SendBreak(USART_TypeDef *USARTx);
void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime);
void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler);
void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState);
void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode);
void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState);
FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG);
void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG);
ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT);
void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT);
#ifdef __cplusplus
}
#endif
#endif

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#include "bsp_ir_receiver.h"
void TIM4_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
void ir_receiver_on_timeout_cb(void);
void ir_receiver_on_capture_rising_cb(uint32_t capture_time_us);
void ir_receiver_on_capture_falling_cb(uint32_t capture_time_us);
void bsp_ir_receiver_init(void)
{
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
GPIO_InitTypeDef GPIO_InitStructure;
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; //上拉输入
GPIO_Init(GPIOB, &GPIO_InitStructure); //PB6 TIM4_CH1
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE);
TIM_TimeBaseInitTypeDef TIM_TimeBaseInitStructure;
TIM_TimeBaseInitStructure.TIM_Period = 60000 - 1; //定时器在120ms后溢出
TIM_TimeBaseInitStructure.TIM_Prescaler = SystemCoreClock / 1000000 * 2 - 1; //每个捕获计数器的单位为2us
TIM_TimeBaseInitStructure.TIM_ClockDivision = TIM_CKD_DIV1;
TIM_TimeBaseInitStructure.TIM_CounterMode = TIM_CounterMode_Up;
TIM_TimeBaseInit(TIM4, &TIM_TimeBaseInitStructure);
TIM_ICInitTypeDef TIM_ICInitStructure;
TIM_ICInitStructure.TIM_Channel = TIM_Channel_1; //定时器4通道1
TIM_ICInitStructure.TIM_ICPolarity = TIM_ICPolarity_Falling;
TIM_ICInitStructure.TIM_ICSelection = TIM_ICSelection_DirectTI;
TIM_ICInitStructure.TIM_ICPrescaler = TIM_ICPSC_DIV1;
TIM_ICInitStructure.TIM_ICFilter = 0x03; //输入滤波器3个定时器时钟
TIM_ICInit(TIM4, &TIM_ICInitStructure);
TIM_Cmd(TIM4, ENABLE);
NVIC_InitTypeDef NVIC_InitStructure;
NVIC_InitStructure.NVIC_IRQChannel = TIM4_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
TIM_ITConfig(TIM4, TIM_IT_Update | TIM_IT_CC1, ENABLE); //允许定时器更新中断与捕获中断
}
void TIM4_IRQHandler(void)
{
if (TIM_GetITStatus(TIM4, TIM_IT_Update)) { //超时溢出
ir_receiver_on_timeout_cb();
}
if (TIM_GetITStatus(TIM4, TIM_IT_CC1)) { //通道1捕获中断
uint16_t capture_value = TIM_GetCapture1(TIM4); //获取通道1捕获值
if (GPIO_ReadInputDataBit(GPIOB, GPIO_Pin_6) == Bit_SET) { //上升沿捕获
TIM_OC1PolarityConfig(TIM4, TIM_ICPolarity_Falling);//通道1设置为下降沿捕获
TIM_SetCounter(TIM4, 0); //清空定时器计数值防止超时
ir_receiver_on_capture_rising_cb(capture_value * 2);
} else { //下降沿捕获
TIM_OC1PolarityConfig(TIM4, TIM_ICPolarity_Rising);//通道1设置为上升沿捕获
TIM_SetCounter(TIM4, 0); //清空定时器计数值防止超时
ir_receiver_on_capture_falling_cb(capture_value * 2);
}
}
TIM_ClearITPendingBit(TIM4, TIM_IT_Update | TIM_IT_CC1); //清除中断标志位
}
typedef enum {
ir_receiver_state_idle = 0, //空闲状态
ir_receiver_state_receive, //正在接收数据码
ir_receiver_state_repeat, //数据码接收完成，接收重复码
} ir_receiver_state_t;
static volatile struct {
ir_receiver_state_t state;
uint32_t receiving_code; //接收到的红外数据码
uint32_t received_code; //上次成功接收到的红外数据码
uint8_t received_rising_edge; //已经接收到有效的上升沿
uint8_t received_bit_count; //已经接收到红外码的位数
uint32_t received_repeat_count; //已经接收到重复按键码的数量。成功接收红外码后变为1，随着重复码数量增加
} ir_receiver = {
.state = ir_receiver_state_idle,
.received_code = 0x00000000,
.received_rising_edge = 0,
.received_bit_count = 0,
.received_repeat_count = 0
};
/**
* @brief 定时器超时回调函数
*
*/
void ir_receiver_on_timeout_cb(void)
{
if (ir_receiver.state == ir_receiver_state_receive) { //如果目前仍处于接收状态
ir_receiver.received_code = 0x00000000;
ir_receiver.received_bit_count = 0;
ir_receiver.received_rising_edge = 0; //接收失败，恢复初始状态
}
ir_receiver.state = ir_receiver_state_idle; //[repeat->idle]接收超时，恢复空闲状态
}
/**
* @brief 上升沿捕获回调函数，即38kHz载波从有到无的边沿，测量有载波的时长
*
* @param capture_time_us 低电平持续的时间[us]
*/
void ir_receiver_on_capture_rising_cb(uint32_t capture_time_us)
{
if (ir_receiver.state == ir_receiver_state_receive) { //当前处于接收数据码状态
if (capture_time_us > 0.9 * 560 && capture_time_us < 1.1 * 560) { //接收到560us低电平
ir_receiver.received_rising_edge = 1; //标记收到有效上升沿
}
} else { //当前处于空闲或接收重复码状态
if (capture_time_us > 0.9 * 9000 && capture_time_us < 1.1 * 9000) { //接收到9000us低电平
ir_receiver.received_rising_edge = 1; //标记收到有效上升沿
}
}
}
/**
* @brief 下降沿捕获回调函数，即38kHz载波从无到有的边沿，测量无载波的时长
*
* @param capture_time_us 高电平持续的时间[us]
*/
void ir_receiver_on_capture_falling_cb(uint32_t capture_time_us)
{
if (ir_receiver.received_rising_edge) { //如果接收到了有效的上升沿
if (ir_receiver.state == ir_receiver_state_receive) { //当前是接收状态
if (capture_time_us > 0.9 * 560 && capture_time_us < 1.1 * 560) { //接收到560us高电平
ir_receiver.receiving_code <<= 1; //左移一位
ir_receiver.received_bit_count ++; //累加接收到的数据位数
} else if (capture_time_us > 0.9 * 1680 && capture_time_us < 1.1 * 1680) { //接收到1680us高电平
ir_receiver.receiving_code <<= 1; //左移一位
ir_receiver.receiving_code |= 0x01; //最低位置1
ir_receiver.received_bit_count ++; //累加接收到的数据位数
}
if (ir_receiver.received_bit_count == 32) { //接收到了32位数据码
ir_receiver.state = ir_receiver_state_repeat; //[receive->repeat]数据码接收完成
ir_receiver.received_repeat_count = 1;
ir_receiver.received_code = ir_receiver.receiving_code; //记录成功的接收
}
} else {
if (capture_time_us > 0.9 * 2250 && capture_time_us < 1.1 * 2250) { //接收到2250us高电平
if (ir_receiver.state == ir_receiver_state_repeat) { //当前是数据码接收完成状态
ir_receiver.received_repeat_count ++; //重复码数量加1
}
} else if (capture_time_us > 0.9 * 4500 && capture_time_us < 1.1 * 4500) { //接收到4500us引导码
ir_receiver.state = ir_receiver_state_receive; //[idle/repeat->receive]开始接收数据码
ir_receiver.receiving_code = 0x0000000; //清除接收到的红外码
ir_receiver.received_repeat_count = 0; //清零重复码数量
ir_receiver.received_bit_count = 0; //清除接收到的数据位数
}
}
}
ir_receiver.received_rising_edge = 0; //清除有效上升沿标志位
}
uint32_t bsp_ir_receiver_get_key(uint32_t *received_code)
{
uint32_t repeat_count = ir_receiver.received_repeat_count;
if (received_code) {
*received_code = ir_receiver.received_code;
}
if (ir_receiver.state == ir_receiver_state_idle) { //已经接收完的状态
ir_receiver.received_repeat_count = 0;
ir_receiver.received_code = 0x00000000; //读取后复原初始状态
}
return repeat_count;
}

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#ifndef __BSP_IR_RECEIVER_H
#define __BSP_IR_RECEIVER_H
#include "ch32v20x.h"
void bsp_ir_receiver_init(void);
uint32_t bsp_ir_receiver_get_key(uint32_t *received_code);
#endif

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#ifndef __CH32V20x_CONF_H
#define __CH32V20x_CONF_H
//#include "ch32v20x_adc.h"
//#include "ch32v20x_dma.h"
//#include "ch32v20x_exti.h"
#include "ch32v20x_flash.h"
#include "ch32v20x_gpio.h"
#include "ch32v20x_misc.h"
//#include "ch32v20x_iwdg.h"
//#include "ch32v20x_pwr.h"
#include "ch32v20x_rcc.h"
//#include "ch32v20x_spi.h"
#include "ch32v20x_tim.h"
#include "ch32v20x_usart.h"
#endif /* __CH32V20x_CONF_H */

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#include "ch32v20x.h"
void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
void USB_LP_CAN1_RX0_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
void USBD_IRQHandler(uint8_t busid);
void NMI_Handler(void)
{
while (1);
}
void HardFault_Handler(void)
{
while (1);
}
void USB_LP_CAN1_RX0_IRQHandler(void)
{
USBD_IRQHandler(0);
}

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#include "ch32v20x.h"
#include "usb_hid_km.h"
#include "bsp_ir_receiver.h"
void usb_dc_low_level_init(void)
{
NVIC_InitTypeDef NVIC_InitStructure;
NVIC_InitStructure.NVIC_IRQChannel = USB_LP_CAN1_RX0_IRQn;
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
NVIC_Init(&NVIC_InitStructure);
RCC_USBCLKConfig(RCC_USBCLKSource_PLLCLK_Div1);
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, ENABLE); //初始化USB时钟
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); //开启GPIOA时钟
EXTEN->EXTEN_CTR |= EXTEN_USBD_PU_EN; //开启USB上拉电阻
}
void usb_dc_low_level_deinit(void)
{
EXTEN->EXTEN_CTR &= ~EXTEN_USBD_PU_EN; //关闭USB上拉电阻
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USB, DISABLE); //关闭USB时钟
NVIC_DisableIRQ(USB_LP_CAN1_RX0_IRQn); //关闭USB中断
}
void bsp_led_init(void)
{
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
GPIO_InitTypeDef GPIO_InitStructure;
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
GPIO_Init(GPIOB, &GPIO_InitStructure);
}
typedef enum {
ir_remote_key_power = 0xB24D,
ir_remote_key_mute = 0xC23D,
ir_remote_key_volume_down = 0xE817,
ir_remote_key_volume_up = 0x18E7,
ir_remote_key_arrow_up = 0xD02F,
ir_remote_key_arrow_down = 0x708F,
ir_remote_key_arrow_left = 0x08F7,
ir_remote_key_arrow_right = 0x8877,
ir_remote_key_ok = 0xB04F,
ir_remote_key_home = 0x58A7,
ir_remote_key_menu = 0xA25D,
ir_remote_key_back = 0x42BD,
ir_remote_key_num_1 = 0x807F,
ir_remote_key_num_2 = 0x40BF,
ir_remote_key_num_3 = 0xC03F,
ir_remote_key_num_4 = 0x20DF,
ir_remote_key_num_5 = 0xA05F,
ir_remote_key_num_6 = 0x609F,
ir_remote_key_num_7 = 0xE01F,
ir_remote_key_num_8 = 0x10EF,
ir_remote_key_num_9 = 0x906F,
ir_remote_key_num_0 = 0x00FF,
ir_remote_key_mouse = 0xE21D,
ir_remote_key_backspace = 0x30CF
} ir_remote_keycode_t;
void keyboard_press_by_ir_code(ir_remote_keycode_t keycode)
{
switch (keycode) {
case ir_remote_key_power:
hid_system_control_key_send(0, HID_SYSTEM_USAGE_POWER);
break;
case ir_remote_key_mute:
hid_consumer_control_key_send(0, HID_CONSUMER_USAGE_MUTE);
break;
case ir_remote_key_volume_down:
hid_consumer_control_key_send(0, HID_CONSUMER_USAGE_VOLUMEDEC);
break;
case ir_remote_key_volume_up:
hid_consumer_control_key_send(0, HID_CONSUMER_USAGE_VOLUMEINC);
break;
case ir_remote_key_home:
hid_consumer_control_key_send(0, HID_CONSUMER_USAGE_WEBHOME);
break;
case ir_remote_key_back:
hid_consumer_control_key_send(0, HID_CONSUMER_USAGE_WWWBACK);
break;
case ir_remote_key_menu:
hid_keyboard_key_send(0, 0, HID_KBD_USAGE_APPLICATION);
break;
case ir_remote_key_arrow_up:
hid_keyboard_key_send(0, 0, HID_KBD_USAGE_UP);
break;
case ir_remote_key_arrow_down:
hid_keyboard_key_send(0, 0, HID_KBD_USAGE_DOWN);
break;
case ir_remote_key_arrow_left:
hid_keyboard_key_send(0, 0, HID_KBD_USAGE_LEFT);
break;
case ir_remote_key_arrow_right:
hid_keyboard_key_send(0, 0, HID_KBD_USAGE_RIGHT);
break;
case ir_remote_key_ok:
hid_keyboard_key_send(0, 0, HID_KBD_USAGE_ENTER);
break;
case ir_remote_key_num_1:
hid_keyboard_key_send(0, 0, HID_KBD_USAGE_1 + 0);
break;
case ir_remote_key_num_2:
hid_keyboard_key_send(0, 0, HID_KBD_USAGE_1 + 1);
break;
case ir_remote_key_num_3:
hid_keyboard_key_send(0, 0, HID_KBD_USAGE_1 + 2);
break;
case ir_remote_key_num_4:
hid_keyboard_key_send(0, 0, HID_KBD_USAGE_1 + 3);
break;
case ir_remote_key_num_5:
hid_keyboard_key_send(0, 0, HID_KBD_USAGE_1 + 4);
break;
case ir_remote_key_num_6:
hid_keyboard_key_send(0, 0, HID_KBD_USAGE_1 + 5);
break;
case ir_remote_key_num_7:
hid_keyboard_key_send(0, 0, HID_KBD_USAGE_1 + 6);
break;
case ir_remote_key_num_8:
hid_keyboard_key_send(0, 0, HID_KBD_USAGE_1 + 7);
break;
case ir_remote_key_num_9:
hid_keyboard_key_send(0, 0, HID_KBD_USAGE_1 + 8);
break;
case ir_remote_key_num_0:
hid_keyboard_key_send(0, 0, HID_KBD_USAGE_1 + 9);
break;
case ir_remote_key_backspace:
hid_keyboard_key_send(0, 0, HID_KBD_USAGE_DELETE);
break;
default:
break;
}
}
void keyboard_release_by_ir_code(ir_remote_keycode_t keycode)
{
switch (keycode) {
case ir_remote_key_power:
hid_system_control_key_send(0, 0);
break;
case ir_remote_key_mute:
case ir_remote_key_volume_down:
case ir_remote_key_volume_up:
case ir_remote_key_home:
case ir_remote_key_back:
hid_consumer_control_key_send(0, 0);
break;
case ir_remote_key_menu:
case ir_remote_key_arrow_up:
case ir_remote_key_arrow_down:
case ir_remote_key_arrow_left:
case ir_remote_key_arrow_right:
case ir_remote_key_ok:
case ir_remote_key_num_1:
case ir_remote_key_num_2:
case ir_remote_key_num_3:
case ir_remote_key_num_4:
case ir_remote_key_num_5:
case ir_remote_key_num_6:
case ir_remote_key_num_7:
case ir_remote_key_num_8:
case ir_remote_key_num_9:
case ir_remote_key_num_0:
case ir_remote_key_backspace:
hid_keyboard_key_send(0, 0, 0);
break;
default:
break;
}
}
void main(void)
{
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
SystemCoreClockUpdate();
bsp_led_init();
bsp_ir_receiver_init();
hid_keyboard_mouse_init(0, 0x40005C00);
while(1) {
uint32_t ir_code, ir_count;
ir_count = bsp_ir_receiver_get_key(&ir_code);
if (ir_count > 0) {
keyboard_press_by_ir_code(ir_code & 0xFFFF);
GPIO_WriteBit(GPIOB, GPIO_Pin_8, Bit_SET);
do {
ir_count = bsp_ir_receiver_get_key(NULL);
} while (ir_count != 0);
GPIO_WriteBit(GPIOB, GPIO_Pin_8, Bit_RESET);
keyboard_release_by_ir_code(ir_code & 0xFFFF);
}
}
}

987
ch32v203_ir_box/src/user/system_ch32v20x.c Normal file
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/********************************** (C) COPYRIGHT *******************************
* File Name : system_ch32v20x.c
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Source File.
* For HSE = 32Mhz (CH32V208x/CH32V203RBT6)
* For HSE = 8Mhz (other CH32V203x)
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#include "ch32v20x.h"
/*
* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
* reset the HSI is used as SYSCLK source).
* If none of the define below is enabled, the HSI is used as System clock source.
*/
//#define SYSCLK_FREQ_HSE HSE_VALUE
//#define SYSCLK_FREQ_48MHz_HSE 48000000
//#define SYSCLK_FREQ_56MHz_HSE 56000000
//#define SYSCLK_FREQ_72MHz_HSE 72000000
//#define SYSCLK_FREQ_96MHz_HSE 96000000
//#define SYSCLK_FREQ_120MHz_HSE 120000000
//#define SYSCLK_FREQ_144MHz_HSE 144000000
//#define SYSCLK_FREQ_HSI HSI_VALUE
#define SYSCLK_FREQ_48MHz_HSI 48000000
//#define SYSCLK_FREQ_56MHz_HSI 56000000
//#define SYSCLK_FREQ_72MHz_HSI 72000000
//#define SYSCLK_FREQ_96MHz_HSI 96000000
//#define SYSCLK_FREQ_120MHz_HSI 120000000
//#define SYSCLK_FREQ_144MHz_HSI 144000000
/* Clock Definitions */
#ifdef SYSCLK_FREQ_HSE
uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /* System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_48MHz_HSE
uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSE; /* System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_56MHz_HSE
uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSE; /* System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_72MHz_HSE
uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSE; /* System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_96MHz_HSE
uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSE; /* System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_120MHz_HSE
uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSE; /* System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_144MHz_HSE
uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSE; /* System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_48MHz_HSI
uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /* System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_56MHz_HSI
uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSI; /* System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_72MHz_HSI
uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSI; /* System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_96MHz_HSI
uint32_t SystemCoreClock = SYSCLK_FREQ_96MHz_HSI; /* System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_120MHz_HSI
uint32_t SystemCoreClock = SYSCLK_FREQ_120MHz_HSI; /* System Clock Frequency (Core Clock) */
#elif defined SYSCLK_FREQ_144MHz_HSI
uint32_t SystemCoreClock = SYSCLK_FREQ_144MHz_HSI; /* System Clock Frequency (Core Clock) */
#else
uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */
#endif
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
/* system_private_function_proto_types */
static void SetSysClock(void);
#ifdef SYSCLK_FREQ_HSE
static void SetSysClockToHSE( void );
#elif defined SYSCLK_FREQ_48MHz_HSE
static void SetSysClockTo48_HSE( void );
#elif defined SYSCLK_FREQ_56MHz_HSE
static void SetSysClockTo56_HSE( void );
#elif defined SYSCLK_FREQ_72MHz_HSE
static void SetSysClockTo72_HSE( void );
#elif defined SYSCLK_FREQ_96MHz_HSE
static void SetSysClockTo96_HSE( void );
#elif defined SYSCLK_FREQ_120MHz_HSE
static void SetSysClockTo120_HSE( void );
#elif defined SYSCLK_FREQ_144MHz_HSE
static void SetSysClockTo144_HSE( void );
#elif defined SYSCLK_FREQ_48MHz_HSI
static void SetSysClockTo48_HSI( void );
#elif defined SYSCLK_FREQ_56MHz_HSI
static void SetSysClockTo56_HSI( void );
#elif defined SYSCLK_FREQ_72MHz_HSI
static void SetSysClockTo72_HSI( void );
#elif defined SYSCLK_FREQ_96MHz_HSI
static void SetSysClockTo96_HSI( void );
#elif defined SYSCLK_FREQ_120MHz_HSI
static void SetSysClockTo120_HSI( void );
#elif defined SYSCLK_FREQ_144MHz_HSI
static void SetSysClockTo144_HSI( void );
#endif
/*********************************************************************
* @fn SystemInit
*
* @brief Setup the microcontroller system Initialize the Embedded Flash Interface,
* the PLL and update the SystemCoreClock variable.
*
* @return none
*/
void SystemInit (void)
{
RCC->CTLR |= (uint32_t)0x00000001;
RCC->CFGR0 &= (uint32_t)0xF0FF0000;
RCC->CTLR &= (uint32_t)0xFEF6FFFF;
RCC->CTLR &= (uint32_t)0xFFFBFFFF;
RCC->CFGR0 &= (uint32_t)0xFF00FFFF;
RCC->INTR = 0x009F0000;
SetSysClock();
}
/*********************************************************************
* @fn SystemCoreClockUpdate
*
* @brief Update SystemCoreClock variable according to Clock Register Values.
*
* @return none
*/
void SystemCoreClockUpdate (void)
{
uint32_t tmp = 0, pllmull = 0, pllsource = 0, Pll_6_5 = 0;
tmp = RCC->CFGR0 & RCC_SWS;
switch (tmp)
{
case 0x00:
SystemCoreClock = HSI_VALUE;
break;
case 0x04:
SystemCoreClock = HSE_VALUE;
break;
case 0x08:
pllmull = RCC->CFGR0 & RCC_PLLMULL;
pllsource = RCC->CFGR0 & RCC_PLLSRC;
pllmull = ( pllmull >> 18) + 2;
if(pllmull == 17) pllmull = 18;
if (pllsource == 0x00)
{
if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE){
SystemCoreClock = HSI_VALUE * pllmull;
}
else{
SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
}
}
else
{
#if defined (CH32V20x_D8W) || defined (CH32V20x_D8)
if(((RCC->CFGR0 & (3<<22)) == (3<<22)) && (RCC_USB5PRE_JUDGE()== SET))
{
SystemCoreClock = ((HSE_VALUE>>1)) * pllmull;
}
else
#endif
if ((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
{
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
SystemCoreClock = ((HSE_VALUE>>2) >> 1) * pllmull;
#else
SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
#endif
}
else
{
#if defined (CH32V20x_D8) || defined (CH32V20x_D8W)
SystemCoreClock = (HSE_VALUE>>2) * pllmull;
#else
SystemCoreClock = HSE_VALUE * pllmull;
#endif
}
}
if(Pll_6_5 == 1) SystemCoreClock = (SystemCoreClock / 2);
break;
default:
SystemCoreClock = HSI_VALUE;
break;
}
tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
SystemCoreClock >>= tmp;
}
/*********************************************************************
* @fn SetSysClock
*
* @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
*
* @return none
*/
static void SetSysClock(void)
{
//GPIO_IPD_Unused();
#ifdef SYSCLK_FREQ_HSE
SetSysClockToHSE();
#elif defined SYSCLK_FREQ_48MHz_HSE
SetSysClockTo48_HSE();
#elif defined SYSCLK_FREQ_56MHz_HSE
SetSysClockTo56_HSE();
#elif defined SYSCLK_FREQ_72MHz_HSE
SetSysClockTo72_HSE();
#elif defined SYSCLK_FREQ_96MHz_HSE
SetSysClockTo96_HSE();
#elif defined SYSCLK_FREQ_120MHz_HSE
SetSysClockTo120_HSE();
#elif defined SYSCLK_FREQ_144MHz_HSE
SetSysClockTo144_HSE();
#elif defined SYSCLK_FREQ_48MHz_HSI
SetSysClockTo48_HSI();
#elif defined SYSCLK_FREQ_56MHz_HSI
SetSysClockTo56_HSI();
#elif defined SYSCLK_FREQ_72MHz_HSI
SetSysClockTo72_HSI();
#elif defined SYSCLK_FREQ_96MHz_HSI
SetSysClockTo96_HSI();
#elif defined SYSCLK_FREQ_120MHz_HSI
SetSysClockTo120_HSI();
#elif defined SYSCLK_FREQ_144MHz_HSI
SetSysClockTo144_HSI();
#endif
/* If none of the define above is enabled, the HSI is used as System clock
* source (default after reset)
*/
}
#ifdef SYSCLK_FREQ_HSE
/*********************************************************************
* @fn SetSysClockToHSE
*
* @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
*
* @return none
*/
static void SetSysClockToHSE(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
RCC->CTLR |= ((uint32_t)RCC_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CTLR & RCC_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CTLR & RCC_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
/* Select HSE as system clock source
* CH32V20x_D6 (HSE=8MHZ)
* CH32V20x_D8 (HSE=32MHZ)
* CH32V20x_D8W (HSE=32MHZ)
*/
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;
/* Wait till HSE is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
{
}
}
else
{
/* If HSE fails to start-up, the application will have wrong clock
* configuration. User can add here some code to deal with this error
*/
}
}
#elif defined SYSCLK_FREQ_48MHz_HSE
/*********************************************************************
* @fn SetSysClockTo48_HSE
*
* @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
*
* @return none
*/
static void SetSysClockTo48_HSE(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
RCC->CTLR |= ((uint32_t)RCC_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CTLR & RCC_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CTLR & RCC_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 6 = 48 MHz (HSE=8MHZ)
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 6 = 48 MHz (HSE=32MHZ)
*/
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL6);
/* Enable PLL */
RCC->CTLR |= RCC_PLLON;
/* Wait till PLL is ready */
while((RCC->CTLR & RCC_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
else
{
/*
* If HSE fails to start-up, the application will have wrong clock
* configuration. User can add here some code to deal with this error
*/
}
}
#elif defined SYSCLK_FREQ_56MHz_HSE
/*********************************************************************
* @fn SetSysClockTo56_HSE
*
* @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
*
* @return none
*/
static void SetSysClockTo56_HSE(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
RCC->CTLR |= ((uint32_t)RCC_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CTLR & RCC_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CTLR & RCC_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 7 = 56 MHz (HSE=8MHZ)
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 7 = 56 MHz (HSE=32MHZ)
*/
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL7);
/* Enable PLL */
RCC->CTLR |= RCC_PLLON;
/* Wait till PLL is ready */
while((RCC->CTLR & RCC_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
else
{
/*
* If HSE fails to start-up, the application will have wrong clock
* configuration. User can add here some code to deal with this error
*/
}
}
#elif defined SYSCLK_FREQ_72MHz_HSE
/*********************************************************************
* @fn SetSysClockTo72_HSE
*
* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
*
* @return none
*/
static void SetSysClockTo72_HSE(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
RCC->CTLR |= ((uint32_t)RCC_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CTLR & RCC_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CTLR & RCC_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 9 = 72 MHz (HSE=8MHZ)
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 9 = 72 MHz (HSE=32MHZ)
*/
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
RCC_PLLMULL));
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL9);
/* Enable PLL */
RCC->CTLR |= RCC_PLLON;
/* Wait till PLL is ready */
while((RCC->CTLR & RCC_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
else
{
/*
* If HSE fails to start-up, the application will have wrong clock
* configuration. User can add here some code to deal with this error
*/
}
}
#elif defined SYSCLK_FREQ_96MHz_HSE
/*********************************************************************
* @fn SetSysClockTo96_HSE
*
* @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
*
* @return none
*/
static void SetSysClockTo96_HSE(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
RCC->CTLR |= ((uint32_t)RCC_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CTLR & RCC_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CTLR & RCC_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 12 = 96 MHz (HSE=8MHZ)
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 12 = 96 MHz (HSE=32MHZ)
*/
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
RCC_PLLMULL));
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL12);
/* Enable PLL */
RCC->CTLR |= RCC_PLLON;
/* Wait till PLL is ready */
while((RCC->CTLR & RCC_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
else
{
/*
* If HSE fails to start-up, the application will have wrong clock
* configuration. User can add here some code to deal with this error
*/
}
}
#elif defined SYSCLK_FREQ_120MHz_HSE
/*********************************************************************
* @fn SetSysClockTo120_HSE
*
* @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
*
* @return none
*/
static void SetSysClockTo120_HSE(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
RCC->CTLR |= ((uint32_t)RCC_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CTLR & RCC_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if((RCC->CTLR & RCC_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if(HSEStatus == (uint32_t)0x01)
{
#if defined (CH32V20x_D8W)
RCC->CFGR0 |= (uint32_t)(3<<22);
/* HCLK = SYSCLK/2 */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV2;
#else
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
#endif
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 15 = 120 MHz (HSE=8MHZ)
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 15 = 120 MHz (HSE=32MHZ)
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/2 * 15 = 240 MHz (HSE=32MHZ)
*/
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
RCC_PLLMULL));
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL15);
/* Enable PLL */
RCC->CTLR |= RCC_PLLON;
/* Wait till PLL is ready */
while((RCC->CTLR & RCC_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
else
{
/*
* If HSE fails to start-up, the application will have wrong clock
* configuration. User can add here some code to deal with this error
*/
}
}
#elif defined SYSCLK_FREQ_144MHz_HSE
/*********************************************************************
* @fn SetSysClockTo144_HSE
*
* @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
*
* @return none
*/
static void SetSysClockTo144_HSE(void)
{
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
RCC->CTLR |= ((uint32_t)RCC_HSEON);
/* Wait till HSE is ready and if Time out is reached exit */
do
{
HSEStatus = RCC->CTLR & RCC_HSERDY;
StartUpCounter++;
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
if ((RCC->CTLR & RCC_HSERDY) != RESET)
{
HSEStatus = (uint32_t)0x01;
}
else
{
HSEStatus = (uint32_t)0x00;
}
if (HSEStatus == (uint32_t)0x01)
{
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* CH32V20x_D6-PLL configuration: PLLCLK = HSE * 18 = 144 MHz (HSE=8MHZ)
* CH32V20x_D8-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
* CH32V20x_D8W-PLL configuration: PLLCLK = HSE/4 * 18 = 144 MHz (HSE=32MHZ)
*/
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE |
RCC_PLLMULL));
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLXTPRE_HSE | RCC_PLLMULL18);
/* Enable PLL */
RCC->CTLR |= RCC_PLLON;
/* Wait till PLL is ready */
while((RCC->CTLR & RCC_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
else
{
/*
* If HSE fails to start-up, the application will have wrong clock
* configuration. User can add here some code to deal with this error
*/
}
}
#elif defined SYSCLK_FREQ_48MHz_HSI
/*********************************************************************
* @fn SetSysClockTo48_HSI
*
* @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
*
* @return none
*/
static void SetSysClockTo48_HSI(void)
{
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* PLL configuration: PLLCLK = HSI * 6 = 48 MHz */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6);
/* Enable PLL */
RCC->CTLR |= RCC_PLLON;
/* Wait till PLL is ready */
while((RCC->CTLR & RCC_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
#elif defined SYSCLK_FREQ_56MHz_HSI
/*********************************************************************
* @fn SetSysClockTo56_HSI
*
* @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
*
* @return none
*/
static void SetSysClockTo56_HSI(void)
{
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* PLL configuration: PLLCLK = HSI * 7 = 48 MHz */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7);
/* Enable PLL */
RCC->CTLR |= RCC_PLLON;
/* Wait till PLL is ready */
while((RCC->CTLR & RCC_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
#elif defined SYSCLK_FREQ_72MHz_HSI
/*********************************************************************
* @fn SetSysClockTo72_HSI
*
* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
*
* @return none
*/
static void SetSysClockTo72_HSI(void)
{
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* PLL configuration: PLLCLK = HSI * 9 = 72 MHz */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9);
/* Enable PLL */
RCC->CTLR |= RCC_PLLON;
/* Wait till PLL is ready */
while((RCC->CTLR & RCC_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
#elif defined SYSCLK_FREQ_96MHz_HSI
/*********************************************************************
* @fn SetSysClockTo96_HSI
*
* @brief Sets System clock frequency to 96MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
*
* @return none
*/
static void SetSysClockTo96_HSI(void)
{
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* PLL configuration: PLLCLK = HSI * 12 = 96 MHz */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL12);
/* Enable PLL */
RCC->CTLR |= RCC_PLLON;
/* Wait till PLL is ready */
while((RCC->CTLR & RCC_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
#elif defined SYSCLK_FREQ_120MHz_HSI
/*********************************************************************
* @fn SetSysClockTo120_HSI
*
* @brief Sets System clock frequency to 120MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
*
* @return none
*/
static void SetSysClockTo120_HSI(void)
{
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* PLL configuration: PLLCLK = HSI * 15 = 120 MHz */
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
RCC_PLLMULL));
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL15);
/* Enable PLL */
RCC->CTLR |= RCC_PLLON;
/* Wait till PLL is ready */
while((RCC->CTLR & RCC_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
#elif defined SYSCLK_FREQ_144MHz_HSI
/*********************************************************************
* @fn SetSysClockTo144_HSI
*
* @brief Sets System clock frequency to 144MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
*
* @return none
*/
static void SetSysClockTo144_HSI(void)
{
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
/* HCLK = SYSCLK */
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
/* PCLK2 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
/* PCLK1 = HCLK */
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
/* PLL configuration: PLLCLK = HSI * 18 = 144 MHz */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL18);
/* Enable PLL */
RCC->CTLR |= RCC_PLLON;
/* Wait till PLL is ready */
while((RCC->CTLR & RCC_PLLRDY) == 0)
{
}
/* Select PLL as system clock source */
RCC->CFGR0 &= (uint32_t)((uint32_t)~(RCC_SW));
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
/* Wait till PLL is used as system clock source */
while ((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
{
}
}
#endif

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ch32v203_ir_box/src/user/system_ch32v20x.h Normal file
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/********************************** (C) COPYRIGHT *******************************
* File Name : system_ch32v20x.h
* Author : WCH
* Version : V1.0.0
* Date : 2021/06/06
* Description : CH32V20x Device Peripheral Access Layer System Header File.
*********************************************************************************
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
* Attention: This software (modified or not) and binary are used for
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
*******************************************************************************/
#ifndef __SYSTEM_ch32v20x_H
#define __SYSTEM_ch32v20x_H
#ifdef __cplusplus
extern "C" {
#endif
extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
/* System_Exported_Functions */
extern void SystemInit(void);
extern void SystemCoreClockUpdate(void);
#ifdef __cplusplus
}
#endif
#endif /*__CH32V20x_SYSTEM_H */

26
ch32v203_ir_box/src/user/usb_config.h Normal file
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#ifndef __USB_CONFIG_H
#define __USB_CONFIG_H
/* ==================== USB common Configuration =================== */
#define CONFIG_USB_PRINTF(...)
#define CONFIG_USB_DBG_LEVEL USB_DBG_INFO
#define CONFIG_USB_PRINTF_COLOR_ENABLE
#define CONFIG_USB_ALIGN_SIZE 4
#define USB_NOCACHE_RAM_SECTION
/* ================= USB Device Stack Configuration ================ */
#define CONFIG_USBDEV_REQUEST_BUFFER_LEN 256
/* ================== USB Device Port Configuration =================*/
#define CONFIG_USBDEV_MAX_BUS 1
#define CONFIG_USBDEV_EP_NUM 8
/* ---------------------- FSDEV Configuration ---------------------- */
#define CONFIG_USBDEV_FSDEV_PMA_ACCESS 2
#endif

417
ch32v203_ir_box/src/user/usb_hid_km.c Normal file
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#include "usb_hid_km.h"
#include <string.h>
#include "usbd_core.h"
#include "usbd_hid.h"
#define HID_STATE_IDLE 0
#define HID_STATE_BUSY 1
#define USBD_VID 0x1A86
#define USBD_PID 0xFE07
#define USBD_MAX_POWER_MA 100
#define USBD_LANGID_STRING 1033
#define HID_KM_IN_EP 0x81
#define HID_KM_IN_EP_SIZE 9
#define HID_KM_IN_EP_INTERVAL 1
#define HID_KM_OUT_EP 0x02
#define HID_KM_OUT_EP_SIZE 2
#define HID_KM_OUT_EP_INTERVAL 1
#define HID_KM_CONF_DESC_SIZE 41
#define HID_KM_REPORT_DESC_SIZE 185
static uint8_t hid_km_descriptor[] = {
/* 设备(Device)描述符 所有设备有且只有一个 */
USB_DEVICE_DESCRIPTOR_INIT(USB_1_1, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0002, 0x01),
/* 配置(Configuration)描述符 所有设备至少有一个 */
USB_CONFIG_DESCRIPTOR_INIT(HID_KM_CONF_DESC_SIZE, 0x01, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER_MA),
/* 截至此处的配置描述符长度 = 09 */
/* 接口(Interface)描述符 键盘 */
0x09, /* bLength: Descriptor size */
USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType: Descriptor type */
0x00, /* bInterfaceNumber: Number of Interface */
0x00, /* bAlternateSetting: Alternate setting */
0x02, /* bNumEndpoints: 2 */
0x03, /* bInterfaceClass: HID */
0x01, /* bInterfaceSubClass : 1=BOOT, 0=no boot */
0x01, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */
0, /* iInterface: Index of string descriptor */
/* 截至此处的配置描述符长度 = 18 */
/* HID描述符 键盘 */
0x09, /* bLength: HID Descriptor size */
HID_DESCRIPTOR_TYPE_HID, /* bDescriptorType: HID */
0x11, 0x01, /* bcdHID: HID Class Spec release number: HID1.11 */
0x00, /* bCountryCode: Hardware target country */
0x01, /* bNumDescriptors: Number of HID class descriptors to follow */
0x22, /* bDescriptorType */
WBVAL(HID_KM_REPORT_DESC_SIZE), /* wItemLength: Total length of Report descriptor */
/* 截至此处的配置描述符长度 = 27 */
/* 端点(Endpoint)描述符 键盘IN */
0x07, /* bLength: Endpoint Descriptor size */
USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */
HID_KM_IN_EP, /* bEndpointAddress: Endpoint Address (IN) */
0x03, /* bmAttributes: Interrupt endpoint */
WBVAL(HID_KM_IN_EP_SIZE), /* wMaxPacketSize: 9 Bytes maximum */
HID_KM_IN_EP_INTERVAL, /* bInterval: Polling Interval */
/* 截至此处的配置描述符长度 = 34 */
/* 端点(Endpoint)描述符 键盘OUT */
0x07, /* bLength: Endpoint Descriptor size */
USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: Endpoint */
HID_KM_OUT_EP, /* bEndpointAddress: Endpoint Address (IN) */
0x03, /* bmAttributes: Interrupt endpoint */
WBVAL(HID_KM_OUT_EP_SIZE), /* wMaxPacketSize: 9 Bytes maximum */
HID_KM_OUT_EP_INTERVAL, /* bInterval: Polling Interval */
/* 截至此处的配置描述符长度 = 41 */
/* 字符串(String)描述符 设备支持的语言描述符 */
USB_LANGID_INIT(USBD_LANGID_STRING),
/* 字符串(String)描述符 制造商字符串 */
0x02, /* bLength */
USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */
/* 字符串(String)描述符 产品字符串 */
0x1C, /* bLength */
USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */
'I', 0x00,
'R', 0x00,
' ', 0x00,
'R', 0x00,
'e', 0x00,
'm', 0x00,
'o', 0x00,
't', 0x00,
'e', 0x00,
' ', 0x00,
'B', 0x00,
'o', 0x00,
'x', 0x00, /* 共13字符 */
/* 字符串(String)描述符 序列号字符串 */
0x32, /* bLength */
USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */
'0', 0x00,
'0', 0x00,
'0', 0x00,
'0', 0x00,
'0', 0x00,
'0', 0x00,
'0', 0x00,
'0', 0x00,
'0', 0x00,
'0', 0x00,
'0', 0x00,
'0', 0x00,
'0', 0x00,
'0', 0x00,
'0', 0x00,
'0', 0x00,
'0', 0x00,
'0', 0x00,
'0', 0x00,
'0', 0x00,
'0', 0x00,
'0', 0x00,
'0', 0x00,
'0', 0x00, /* 24字符 */
#ifdef CONFIG_USB_HS
/* 设备限定(Device Qualifier)描述符 同时支持全速与高速的设备必须有 */
0x0A,
USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER,
0x00,
0x02,
0x00,
0x00,
0x00,
0x40,
0x01,
0x00,
#endif
/* 空描述符 */
0x00
};
static const uint8_t hid_km_report_desc[HID_KM_REPORT_DESC_SIZE] = {
0x05, 0x01, // Usage Page (Generic Desktop Ctrls)
0x09, 0x06, // Usage (Keyboard)
0xA1, 0x01, // Collection (Application)
0x85, 0x01, // Report ID (1)
0x05, 0x07, // Usage Page (Kbrd/Keypad)
0x19, 0xE0, // Usage Minimum (0xE0)
0x29, 0xE7, // Usage Maximum (0xE7)
0x15, 0x00, // Logical Minimum (0)
0x25, 0x01, // Logical Maximum (1)
0x75, 0x01, // Report Size (1)
0x95, 0x08, // Report Count (8)
0x81, 0x02, // Input (Data,Var,Abs,No Wrap,Linear,Preferred State,No Null Position)
0x75, 0x08, // Report Size (8)
0x95, 0x01, // Report Count (1)
0x81, 0x01, // Input (Const,Array,Abs,No Wrap,Linear,Preferred State,No Null Position)
0x19, 0x00, // Usage Minimum (0x00)
0x29, 0x65, // Usage Maximum (0x65)
0x15, 0x00, // Logical Minimum (0)
0x25, 0x65, // Logical Maximum (101)
0x75, 0x08, // Report Size (8)
0x95, 0x06, // Report Count (6)
0x81, 0x00, // Input (Data,Array,Abs,No Wrap,Linear,Preferred State,No Null Position)
0x05, 0x08, // Usage Page (LEDs)
0x19, 0x01, // Usage Minimum (Num Lock)
0x29, 0x03, // Usage Maximum (Scroll Lock)
0x15, 0x00, // Logical Minimum (0)
0x25, 0x01, // Logical Maximum (1)
0x75, 0x01, // Report Size (1)
0x95, 0x03, // Report Count (3)
0x91, 0x02, // Output (Data,Var,Abs,No Wrap,Linear,Preferred State,No Null Position,Non-volatile)
0x75, 0x05, // Report Size (5)
0x95, 0x01, // Report Count (1)
0x91, 0x01, // Output (Const,Array,Abs,No Wrap,Linear,Preferred State,No Null Position,Non-volatile)
0xC0, // End Collection
0x05, 0x0C, // Usage Page (Consumer)
0x09, 0x01, // Usage (Consumer Control)
0xA1, 0x01, // Collection (Application)
0x85, 0x02, // Report ID (2)
0x19, 0x00, // Usage Minimum (Unassigned)
0x2A, 0x3C, 0x02, // Usage Maximum (AC Format)
0x15, 0x00, // Logical Minimum (0)
0x26, 0x3C, 0x02, // Logical Maximum (572)
0x95, 0x01, // Report Count (1)
0x75, 0x10, // Report Size (16)
0x81, 0x00, // Input (Data,Array,Abs,No Wrap,Linear,Preferred State,No Null Position)
0x75, 0x08, // Report Size (8)
0x95, 0x06, // Report Count (6)
0x81, 0x01, // Input (Const,Array,Abs,No Wrap,Linear,Preferred State,No Null Position)
0xC0, // End Collection
0x05, 0x01, // Usage Page (Generic Desktop Ctrls)
0x09, 0x80, // Usage (Sys Control)
0xA1, 0x01, // Collection (Application)
0x85, 0x03, // Report ID (3)
0x19, 0x81, // Usage Minimum (Sys Power Down)
0x29, 0x83, // Usage Maximum (Sys Wake Up)
0x15, 0x00, // Logical Minimum (0)
0x25, 0x01, // Logical Maximum (1)
0x75, 0x01, // Report Size (1)
0x95, 0x03, // Report Count (3)
0x81, 0x02, // Input (Data,Var,Abs,No Wrap,Linear,Preferred State,No Null Position)
0x95, 0x05, // Report Count (5)
0x81, 0x01, // Input (Const,Array,Abs,No Wrap,Linear,Preferred State,No Null Position)
0x75, 0x08, // Report Size (8)
0x95, 0x07, // Report Count (7)
0x81, 0x01, // Input (Const,Array,Abs,No Wrap,Linear,Preferred State,No Null Position)
0xC0, // End Collection
0x05, 0x01, // Usage Page (Generic Desktop Ctrls)
0x09, 0x02, // Usage (Mouse)
0xA1, 0x01, // Collection (Application)
0x85, 0x04, // Report ID (4)
0x09, 0x01, // Usage (Pointer)
0xA1, 0x00, // Collection (Physical)
0x05, 0x09, // Usage Page (Button)
0x19, 0x01, // Usage Minimum (0x01)
0x29, 0x03, // Usage Maximum (0x03)
0x15, 0x00, // Logical Minimum (0)
0x25, 0x01, // Logical Maximum (1)
0x75, 0x01, // Report Size (1)
0x95, 0x03, // Report Count (3)
0x81, 0x02, // Input (Data,Var,Abs,No Wrap,Linear,Preferred State,No Null Position)
0x75, 0x05, // Report Size (5)
0x95, 0x01, // Report Count (1)
0x81, 0x01, // Input (Const,Array,Abs,No Wrap,Linear,Preferred State,No Null Position)
0x05, 0x01, // Usage Page (Generic Desktop Ctrls)
0x09, 0x30, // Usage (X)
0x09, 0x31, // Usage (Y)
0x09, 0x38, // Usage (Wheel)
0x15, 0x81, // Logical Minimum (-127)
0x25, 0x7F, // Logical Maximum (127)
0x75, 0x08, // Report Size (8)
0x95, 0x03, // Report Count (3)
0x81, 0x06, // Input (Data,Var,Rel,No Wrap,Linear,Preferred State,No Null Position)
0xC0, // End Collection
0xC0, // End Collection
};
static volatile uint8_t hid_km_state = HID_STATE_BUSY;
USB_MEM_ALIGNX uint8_t read_buffer[HID_KM_OUT_EP_SIZE];
static void usbd_hid_keyboard_in_callback(uint8_t busid, uint8_t ep, uint32_t nbytes)
{
hid_km_state = HID_STATE_IDLE;
}
static void usbd_hid_keyboard_out_callback(uint8_t busid, uint8_t ep, uint32_t nbytes)
{
usbd_ep_start_read(busid, ep, read_buffer, HID_KM_OUT_EP_SIZE);
if (read_buffer[0] == 1) {
GPIO_WriteBit(GPIOB, GPIO_Pin_8, read_buffer[1] & 0x02);
}
}
static void usbd_event_handler(uint8_t busid, uint8_t event)
{
switch (event) {
case USBD_EVENT_RESET:
break;
case USBD_EVENT_CONNECTED:
break;
case USBD_EVENT_DISCONNECTED:
break;
case USBD_EVENT_RESUME:
break;
case USBD_EVENT_SUSPEND:
break;
case USBD_EVENT_CONFIGURED:
hid_km_state = HID_STATE_IDLE;
usbd_ep_start_read(busid, HID_KM_OUT_EP, read_buffer, sizeof(read_buffer));
break;
case USBD_EVENT_SET_REMOTE_WAKEUP:
break;
case USBD_EVENT_CLR_REMOTE_WAKEUP:
break;
default:
break;
}
}
static void fill_usb_descriptor_serial_number(void)
{
char serial_string[25];
sprintf(serial_string, "%08X%08X%08X", *(volatile uint32_t*)(0x1FFFF7E8),
*(volatile uint32_t*)(0x1FFFF7EC), *(volatile uint32_t*)(0x1FFFF7F0));
uint16_t serial_number_offset = 0;
for (uint16_t i = 0; i < sizeof(hid_km_descriptor) - 3; i ++) { //查找USB描述符中序列号字符描述符的偏移
if (hid_km_descriptor[i + 0] == '0' && hid_km_descriptor[i + 1] == 0x00 &&
hid_km_descriptor[i + 2] == '0' && hid_km_descriptor[i + 3] == 0x00) {
serial_number_offset = i;
break;
}
}
if (serial_number_offset == 0) { //未找到
return;
}
for (uint8_t i = 0; i < 24; i ++) { //共24位
hid_km_descriptor[serial_number_offset + i * 2] = serial_string[i];
}
}
void hid_keyboard_mouse_init(uint8_t busid, uint32_t reg_base)
{
static struct usbd_interface intf0;
static struct usbd_endpoint hid_keyboard_in_ep = {
.ep_cb = usbd_hid_keyboard_in_callback,
.ep_addr = HID_KM_IN_EP
};
static struct usbd_endpoint hid_keyboard_out_ep = {
.ep_cb = usbd_hid_keyboard_out_callback,
.ep_addr = HID_KM_OUT_EP
};
fill_usb_descriptor_serial_number();
usbd_desc_register(busid, hid_km_descriptor);
usbd_add_interface(busid, usbd_hid_init_intf(busid, &intf0, hid_km_report_desc, HID_KM_REPORT_DESC_SIZE));
usbd_add_endpoint(busid, &hid_keyboard_in_ep); //添加键盘鼠标INT IN端点
usbd_add_endpoint(busid, &hid_keyboard_out_ep); //添加键盘鼠标INT OUT端点
usbd_initialize(busid, reg_base, usbd_event_handler);
}
void hid_keyboard_key_send(uint8_t busid, uint8_t modifier_keys, uint8_t key)
{
static USB_MEM_ALIGNX uint8_t report[HID_KM_IN_EP_SIZE];
memset(report, 0, sizeof(report));
report[0] = 1; //ID
report[1] = modifier_keys; //修饰键
report[3] = key; //第一个按键
// report[4] = ...; //第二个按键
// ...
// report[7] = ...; //第五个按键
int ret = usbd_ep_start_write(busid, HID_KM_IN_EP, report, sizeof(report));
if (ret < 0) {
return;
}
hid_km_state = HID_STATE_BUSY;
while (hid_km_state == HID_STATE_BUSY) {
// __WFI();
}
}
void hid_consumer_control_key_send(uint8_t busid, uint16_t consumer_control_key)
{
static USB_MEM_ALIGNX uint8_t report[HID_KM_IN_EP_SIZE];
memset(report, 0, sizeof(report));
report[0] = 2; //ID
report[1] = consumer_control_key & 0xFF; //键码低字节
report[2] = consumer_control_key >> 8; //键码高字节
int ret = usbd_ep_start_write(busid, HID_KM_IN_EP, report, sizeof(report));
if (ret < 0) {
return;
}
hid_km_state = HID_STATE_BUSY;
while (hid_km_state == HID_STATE_BUSY) {
// __WFI();
}
}
void hid_system_control_key_send(uint8_t busid, uint16_t system_control_key)
{
static USB_MEM_ALIGNX uint8_t report[HID_KM_IN_EP_SIZE];
memset(report, 0, sizeof(report));
report[0] = 3; //ID
report[1] = system_control_key; //键码
int ret = usbd_ep_start_write(busid, HID_KM_IN_EP, report, sizeof(report));
if (ret < 0) {
return;
}
hid_km_state = HID_STATE_BUSY;
while (hid_km_state == HID_STATE_BUSY) {
// __WFI();
}
}
void hid_mouse_send(uint8_t busid, uint8_t buttons, int8_t x, int8_t y, int8_t wheel)
{
static USB_MEM_ALIGNX uint8_t report[HID_KM_IN_EP_SIZE];
memset(report, 0, sizeof(report));
report[0] = 4; //ID
report[1] = buttons; //鼠标按键
report[2] = x; //Delta x
report[3] = y; //Delta y
report[4] = wheel; //滚轮
int ret = usbd_ep_start_write(busid, HID_KM_IN_EP, report, sizeof(report));
if (ret < 0) {
return;
}
hid_km_state = HID_STATE_BUSY;
while (hid_km_state == HID_STATE_BUSY) {
// __WFI();
}
}

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ch32v203_ir_box/src/user/usb_hid_km.h Normal file
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#ifndef __USB_HID_KM_H
#define __USB_HID_KM_H
#include "ch32v20x.h"
#include "usbd_core.h"
#include "usbd_hid.h"
#define HID_MOUSE_BUTTON_LEFT 0x01
#define HID_MOUSE_BUTTON_MIDDLE 0x02
#define HID_MOUSE_BUTTON_RIGHT 0x04
#define HID_CONSUMER_USAGE_MENU 0x0040
#define HID_CONSUMER_USAGE_NEXTTRACK 0x00B5
#define HID_CONSUMER_USAGE_PREVTRACK 0x00B6
#define HID_CONSUMER_USAGE_STOP 0x00B7
#define HID_CONSUMER_USAGE_PLAYPAUSE 0x00CD
#define HID_CONSUMER_USAGE_MUTE 0x00E2
#define HID_CONSUMER_USAGE_VOLUMEINC 0x00E9
#define HID_CONSUMER_USAGE_VOLUMEDEC 0x00EA
#define HID_CONSUMER_USAGE_MEDIASELECT 0x0181
#define HID_CONSUMER_USAGE_MAIL 0x018A
#define HID_CONSUMER_USAGE_CALCULATOR 0x0192
#define HID_CONSUMER_USAGE_MYCOMPUTER 0x0194
#define HID_CONSUMER_USAGE_WWWSEARCH 0x0221
#define HID_CONSUMER_USAGE_WEBHOME 0x0223
#define HID_CONSUMER_USAGE_WWWBACK 0x0224
#define HID_CONSUMER_USAGE_WWWFORWARD 0x0225
#define HID_CONSUMER_USAGE_WWWSTOP 0x0226
#define HID_CONSUMER_USAGE_WWWREFRESH 0x0227
#define HID_CONSUMER_USAGE_WWWFAVORITES 0x022A
#define HID_SYSTEM_USAGE_POWER 0x01
#define HID_SYSTEM_USAGE_SLEEP 0x02
#define HID_SYSTEM_USAGE_WAKEUP 0x04
void hid_keyboard_mouse_init(uint8_t busid, uint32_t reg_base);
void hid_keyboard_key_send(uint8_t busid, uint8_t modifier_keys, uint8_t key);
void hid_consumer_control_key_send(uint8_t busid, uint16_t consumer_control_key);
void hid_system_control_key_send(uint8_t busid, uint16_t system_control_key);
void hid_mouse_send(uint8_t busid, uint8_t buttons, int8_t x, int8_t y, int8_t wheel);
#endif