mijia_haier_bridge: add project templete
This commit is contained in:
parent
3d35b132f2
commit
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1
.gitignore
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.gitignore
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@ -6,3 +6,4 @@ build/
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.vscode
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# MRS IDE files
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*.launch
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.mrs/
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283
mijia_haier_bridge/.cproject
Normal file
283
mijia_haier_bridge/.cproject
Normal file
@ -0,0 +1,283 @@
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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<?fileVersion 4.0.0?><cproject storage_type_id="org.eclipse.cdt.core.XmlProjectDescriptionStorage">
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<storageModule moduleId="org.eclipse.cdt.core.settings">
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<cconfiguration id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074">
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<storageModule buildSystemId="org.eclipse.cdt.managedbuilder.core.configurationDataProvider" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074" moduleId="org.eclipse.cdt.core.settings" name="build">
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<macros/>
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<externalSettings/>
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<extensions>
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<extension id="org.eclipse.cdt.core.ELF" point="org.eclipse.cdt.core.BinaryParser"/>
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<extension id="org.eclipse.cdt.core.GASErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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<extension id="org.eclipse.cdt.core.GmakeErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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<extension id="org.eclipse.cdt.core.GLDErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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<extension id="org.eclipse.cdt.core.CWDLocator" point="org.eclipse.cdt.core.ErrorParser"/>
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<extension id="org.eclipse.cdt.core.GCCErrorParser" point="org.eclipse.cdt.core.ErrorParser"/>
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</extensions>
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</storageModule>
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<storageModule moduleId="cdtBuildSystem" version="4.0.0">
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<configuration artifactExtension="elf" artifactName="${ProjName}" buildArtefactType="org.eclipse.cdt.build.core.buildArtefactType.exe" buildProperties="org.eclipse.cdt.build.core.buildArtefactType=org.eclipse.cdt.build.core.buildArtefactType.exe,org.eclipse.cdt.build.core.buildType=org.eclipse.cdt.build.core.buildType.release" cleanCommand="${cross_rm} -rf" description="" errorParsers="org.eclipse.cdt.core.GASErrorParser;org.eclipse.cdt.core.GmakeErrorParser;org.eclipse.cdt.core.GLDErrorParser;org.eclipse.cdt.core.CWDLocator;org.eclipse.cdt.core.GCCErrorParser" id="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074" name="build" parent="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release" postannouncebuildStep="" postbuildStep="" preannouncebuildStep="" prebuildStep="">
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.nostdlibs.924960428" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.nostdlibs" useByScannerDiscovery="false" value="false" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.gcsections.1689063433" name="Remove unused sections (-Xlinker --gc-sections)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.gcsections" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.printgcsections.621524254" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.printgcsections" useByScannerDiscovery="false" value="false" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.printmap.2073713641" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.cpp.linker.printmap" useByScannerDiscovery="false" value="false" valueType="boolean"/>
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||||
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||||
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||||
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||||
<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createflash.1801165667" name="GNU RISC-V Cross Create Flash Image" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createflash">
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||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createflash.textsection.1097396305" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createflash.textsection" useByScannerDiscovery="false" value="false" valueType="boolean"/>
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||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createflash.datasection.2034511797" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createflash.datasection" useByScannerDiscovery="false" value="false" valueType="boolean"/>
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||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createflash.choice.1726268709" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createflash.choice" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createflash.choice.ihex" valueType="enumerated"/>
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||||
<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createlisting.1356766765" name="GNU RISC-V Cross Create Listing" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.createlisting">
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.source.2052761852" name="Display source (--source|-S)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.source" useByScannerDiscovery="false" value="false" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.allheaders.439659821" name="Display all headers (--all-headers|-x)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.allheaders" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.demangle.67111865" name="Demangle names (--demangle|-C)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.demangle" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.debugging.1623481730" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.debugging" useByScannerDiscovery="false" value="false" valueType="boolean"/>
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||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.disassemble.1859590835" name="Disassemble (--disassemble|-d)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.disassemble" useByScannerDiscovery="false" value="true" valueType="boolean"/>
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||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.fileheaders.160868348" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.fileheaders" useByScannerDiscovery="false" value="false" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.linenumbers.1549373929" name="Display line numbers (--line-numbers|-l)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.linenumbers" useByScannerDiscovery="false" value="false" valueType="boolean"/>
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||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.reloc.1008747895" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.reloc" useByScannerDiscovery="false" value="false" valueType="boolean"/>
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<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.symbols.577922241" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.createlisting.symbols" useByScannerDiscovery="false" value="false" valueType="boolean"/>
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||||
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|
||||
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|
||||
<tool id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.printsize.712424314" name="GNU RISC-V Cross Print Size" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.printsize">
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||||
<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.printsize.format.1404031980" name="Size format" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.printsize.format" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.printsize.format.berkeley" valueType="enumerated"/>
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||||
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||||
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||||
</toolChain>
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||||
</folderInfo>
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||||
<sourceEntries>
|
||||
<entry excluding="" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
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||||
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||||
</configuration>
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||||
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|
||||
<storageModule moduleId="org.eclipse.cdt.core.externalSettings"/>
|
||||
<storageModule moduleId="ilg.gnumcueclipse.managedbuild.packs"/>
|
||||
</cconfiguration>
|
||||
</storageModule>
|
||||
<storageModule moduleId="cdtBuildSystem" version="4.0.0">
|
||||
<project id="999.ilg.gnumcueclipse.managedbuild.cross.riscv.target.elf.275846018" name="Executable file" projectType="ilg.gnumcueclipse.managedbuild.cross.riscv.target.elf"/>
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||||
</storageModule>
|
||||
<storageModule moduleId="scannerConfiguration">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
<scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.767917625;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.debug.767917625.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.1375371130;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.1473381709">
|
||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
|
||||
</scannerConfigBuildInfo>
|
||||
<scannerConfigBuildInfo instanceId="ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074;ilg.gnumcueclipse.managedbuild.cross.riscv.config.elf.release.1008047074.;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.1731377187;ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.compiler.input.2036806839">
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||||
<autodiscovery enabled="true" problemReportingEnabled="true" selectedProfileId=""/>
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||||
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|
||||
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||||
<storageModule moduleId="org.eclipse.cdt.core.LanguageSettingsProviders"/>
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||||
<storageModule moduleId="org.eclipse.cdt.make.core.buildtargets"/>
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||||
</cproject>
|
||||
34
mijia_haier_bridge/.project
Normal file
34
mijia_haier_bridge/.project
Normal file
@ -0,0 +1,34 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<projectDescription>
|
||||
<name>mijia_haier_bridge</name>
|
||||
<comment/>
|
||||
<projects/>
|
||||
<buildSpec>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.genmakebuilder</name>
|
||||
<triggers>clean,full,incremental,</triggers>
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||||
<arguments/>
|
||||
</buildCommand>
|
||||
<buildCommand>
|
||||
<name>org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder</name>
|
||||
<triggers>full,incremental,</triggers>
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||||
<arguments/>
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||||
</buildCommand>
|
||||
</buildSpec>
|
||||
<natures>
|
||||
<nature>org.eclipse.cdt.core.cnature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.managedBuildNature</nature>
|
||||
<nature>org.eclipse.cdt.managedbuilder.core.ScannerConfigNature</nature>
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||||
</natures>
|
||||
<linkedResources/>
|
||||
<filteredResources>
|
||||
<filter>
|
||||
<name/>
|
||||
<type>6</type>
|
||||
<matcher>
|
||||
<id>org.eclipse.ui.ide.multiFilter</id>
|
||||
<arguments>1.0-name-matches-false-false-*.wvproj</arguments>
|
||||
</matcher>
|
||||
</filter>
|
||||
</filteredResources>
|
||||
</projectDescription>
|
||||
25
mijia_haier_bridge/.template
Normal file
25
mijia_haier_bridge/.template
Normal file
@ -0,0 +1,25 @@
|
||||
Vendor=WCH
|
||||
Toolchain=RISC-V
|
||||
Series=CH32V103
|
||||
RTOS=NoneOS
|
||||
CalibrateSupport=false
|
||||
CalibrateCommand=
|
||||
MCU=CH32V103C8T6
|
||||
Link=WCH-Link
|
||||
PeripheralVersion====1.0
|
||||
Description====
|
||||
Mcu Type=CH32V10x
|
||||
Address=0x08000000
|
||||
Target Path=build\mijia_haier_bridge.hex
|
||||
Exe Path=
|
||||
Exe Arguments=
|
||||
CLKSpeed=1
|
||||
DebugInterfaceMode=0
|
||||
Erase All=true
|
||||
Program=true
|
||||
Verify=false
|
||||
Reset=true
|
||||
SDIPrintf=false
|
||||
Disable Power Output=false
|
||||
Clear CodeFlash=false
|
||||
Disable Code-Protect=false
|
||||
407
mijia_haier_bridge/mijia_haier_bridge.wvproj
Normal file
407
mijia_haier_bridge/mijia_haier_bridge.wvproj
Normal file
@ -0,0 +1,407 @@
|
||||
{
|
||||
"version": "1.0",
|
||||
"isNormalMRSProject": true,
|
||||
"basic": {
|
||||
"chipInfo": {
|
||||
"vendor": "WCH",
|
||||
"toolchain": "RISC-V",
|
||||
"series": "CH32V103",
|
||||
"rtos": "NoneOS",
|
||||
"mcu": "CH32V103C8T6",
|
||||
"description": "===",
|
||||
"link": "WCH-Link",
|
||||
"peripheral_version": "===1.0",
|
||||
"calibrateSupport": false,
|
||||
"calibrateCommand": ""
|
||||
},
|
||||
"linkedFolders": [],
|
||||
"removedResources": [
|
||||
{
|
||||
"parentLogicPath": "",
|
||||
"type": "file",
|
||||
"name": "*.wvproj"
|
||||
}
|
||||
],
|
||||
"projectName": "mijia_haier_bridge",
|
||||
"architecture": "RISC-V",
|
||||
"projectType": "c"
|
||||
},
|
||||
"buildConfig": {
|
||||
"configurations": [
|
||||
{
|
||||
"buildArtifact": {
|
||||
"artifact_name": "${ProjName}",
|
||||
"artifact_extension": "elf",
|
||||
"output_prefix": "",
|
||||
"artifact_type": "Executable"
|
||||
},
|
||||
"parallelizationNumber": "optimal",
|
||||
"stop_on_first_build_error": true,
|
||||
"pre_script": "",
|
||||
"pre_script_description": "",
|
||||
"post_script": "",
|
||||
"post_script_description": "",
|
||||
"excludeResources": [],
|
||||
"optimization": {
|
||||
"level": "debug",
|
||||
"message_length": true,
|
||||
"char_is_signed": true,
|
||||
"function_sections": true,
|
||||
"data_sections": true,
|
||||
"no_common_unitialized": true,
|
||||
"do_not_inline_functions": false,
|
||||
"assume_freestanding_environment": false,
|
||||
"disable_builtin": false,
|
||||
"single_precision_constants": false,
|
||||
"position_independent_code": false,
|
||||
"link_time_optimizer": false,
|
||||
"disable_loop_invariant_move": false,
|
||||
"optimize_unused_sections_declared_as_high_code": false,
|
||||
"code_generation_without_hardware_floating": false,
|
||||
"use_pipelines": false,
|
||||
"show_caret_indicating_the_column": false,
|
||||
"other_optimization_flags": ""
|
||||
},
|
||||
"warnings": {
|
||||
"check_syntax_only": false,
|
||||
"pedantic": false,
|
||||
"pedantic_warnings_as_errors": false,
|
||||
"inhibit_all_warnings": false,
|
||||
"warn_on_various_unused_elements": true,
|
||||
"warn_on_uninitialized_variables": true,
|
||||
"enable_all_common_warnings": false,
|
||||
"enable_extra_warnings": false,
|
||||
"warn_on_undeclared_global_function": false,
|
||||
"warn_on_implicit_conversions": false,
|
||||
"warn_if_pointer_arthmetic": false,
|
||||
"warn_if_padding_is_included": false,
|
||||
"warn_if_shadowed_variable": false,
|
||||
"warn_if_suspicious_logical_ops": false,
|
||||
"warn_if_struct_is_returned": false,
|
||||
"warn_if_floats_are_compared_as_equal": false,
|
||||
"generate_errors_instead_of_warnings": false,
|
||||
"other_warning_flags": ""
|
||||
},
|
||||
"debugging": {
|
||||
"debug_level": "default",
|
||||
"debug_format": "default",
|
||||
"generate_prof_information": false,
|
||||
"generate_gprof_information": false,
|
||||
"other_debugging_flags": ""
|
||||
},
|
||||
"assembler": {
|
||||
"preprocessor": {
|
||||
"use_preprocessor": true,
|
||||
"do_not_search_system_directories": false,
|
||||
"preprocess_only": false,
|
||||
"defined_symbols": [],
|
||||
"undefined_symbols": []
|
||||
},
|
||||
"includes": {
|
||||
"include_paths": [],
|
||||
"include_system_paths": [],
|
||||
"include_files": []
|
||||
},
|
||||
"other_warning_flags": "",
|
||||
"miscellaneous": {
|
||||
"assembler_flags": [],
|
||||
"generate_assembler_listing": false,
|
||||
"save_temporary_files": false,
|
||||
"verbose": false,
|
||||
"other_assembler_flags": ""
|
||||
}
|
||||
},
|
||||
"ccompiler": {
|
||||
"preprocessor": {
|
||||
"do_not_search_system_directories": false,
|
||||
"preprocess_only": false,
|
||||
"defined_symbols": [],
|
||||
"undefined_symbols": []
|
||||
},
|
||||
"includes": {
|
||||
"include_paths": [
|
||||
"${project}/src/core",
|
||||
"${project}/src/periph",
|
||||
"${project}/src/user",
|
||||
"${project}/3rdparty/CherryUSB/class/cdc",
|
||||
"${project}/3rdparty/CherryUSB/class/hid",
|
||||
"${project}/3rdparty/CherryUSB/core",
|
||||
"${project}/3rdparty/CherryUSB/common",
|
||||
"${project}/3rdparty/CherryUSB/port/ch32v103"
|
||||
],
|
||||
"include_system_paths": [],
|
||||
"include_files": []
|
||||
},
|
||||
"optimization": {
|
||||
"language_standard": "gnu99",
|
||||
"other_optimization_flags": ""
|
||||
},
|
||||
"warnings": {
|
||||
"warn_if_a_global_function_has_no_prototype": false,
|
||||
"warn_if_a_function_has_no_arg_type": false,
|
||||
"warn_if_wrong_cast": false,
|
||||
"other_warning_flags": ""
|
||||
},
|
||||
"miscellaneous": {
|
||||
"generate_assembler_listing": false,
|
||||
"save_temporary_files": false,
|
||||
"verbose": false,
|
||||
"other_compiler_flags": ""
|
||||
}
|
||||
},
|
||||
"cppcompiler": {
|
||||
"preprocessor": {
|
||||
"do_not_search_system_directories": false,
|
||||
"do_not_search_system_cpp_directories": false,
|
||||
"preprocess_only": false,
|
||||
"defined_symbols": [],
|
||||
"undefined_symbols": []
|
||||
},
|
||||
"includes": {
|
||||
"include_paths": [],
|
||||
"include_system_paths": [],
|
||||
"include_files": []
|
||||
},
|
||||
"optimization": {
|
||||
"cpp_language_standard": "gnucpp11",
|
||||
"abi_version": "0",
|
||||
"do_not_use_exceptions": false,
|
||||
"do_not_use_rtti": false,
|
||||
"do_not_use__cxa_atexit": false,
|
||||
"do_not_use_thread_safe_statics": false,
|
||||
"other_optimization_flags": ""
|
||||
},
|
||||
"warnings": {
|
||||
"warn_on_abi_violations": false,
|
||||
"warn_on_class_privacy": false,
|
||||
"warn_on_no_except_expressions": false,
|
||||
"warn_on_virtual_destructors": false,
|
||||
"warn_on_uncast_null": false,
|
||||
"warn_on_sign_promotion": false,
|
||||
"warn_about_effictive_cpp_violcations": false,
|
||||
"other_warning_flags": ""
|
||||
},
|
||||
"miscellaneous": {
|
||||
"generate_assembler_listing": false,
|
||||
"save_temporary_files": false,
|
||||
"verbose": false,
|
||||
"other_compiler_flags": ""
|
||||
}
|
||||
},
|
||||
"clinker": {
|
||||
"general": {
|
||||
"scriptFiles": [
|
||||
"${project}/src/core/ld_ch32v10x.ld"
|
||||
],
|
||||
"do_not_use_standard_start_files": true,
|
||||
"do_not_use_default_libraries": false,
|
||||
"no_startup_or_default_libs": false,
|
||||
"remove_unused_sections": true,
|
||||
"print_removed_sections": false,
|
||||
"omit_all_symbol_information": false
|
||||
},
|
||||
"libraries": {
|
||||
"libraries": [],
|
||||
"library_search_path": []
|
||||
},
|
||||
"miscellaneous": {
|
||||
"picolibc": "double",
|
||||
"linker_flags": [],
|
||||
"other_objects": [],
|
||||
"generate_map": "\"${BuildArtifactFileBaseName}.map\"",
|
||||
"cross_reference": false,
|
||||
"print_link_map": false,
|
||||
"use_newlib_nano": true,
|
||||
"use_float_with_nano_printf": false,
|
||||
"use_float_with_nano_scanf": false,
|
||||
"do_not_use_syscalls": true,
|
||||
"verbose": false,
|
||||
"use_wch_printffloat": false,
|
||||
"use_wch_printf": true,
|
||||
"use_iqmath": false,
|
||||
"other_linker_flags": "-Wl,--print-memory-usage"
|
||||
}
|
||||
},
|
||||
"cpplinker": {
|
||||
"general": {
|
||||
"scriptFiles": [
|
||||
"${project}/src/core/ld_ch32v10x.ld"
|
||||
],
|
||||
"do_not_use_standard_start_files": true,
|
||||
"do_not_use_default_libraries": false,
|
||||
"no_startup_or_default_libs": false,
|
||||
"remove_unused_sections": true,
|
||||
"print_removed_sections": false,
|
||||
"omit_all_symbol_information": false
|
||||
},
|
||||
"libraries": {
|
||||
"libraries": [],
|
||||
"library_search_path": []
|
||||
},
|
||||
"miscellaneous": {
|
||||
"picolibc": "double",
|
||||
"linker_flags": [],
|
||||
"other_objects": [],
|
||||
"generate_map": "\"${BuildArtifactFileBaseName}.map\"",
|
||||
"cross_reference": false,
|
||||
"print_link_map": false,
|
||||
"use_newlib_nano": true,
|
||||
"use_float_with_nano_printf": false,
|
||||
"use_float_with_nano_scanf": false,
|
||||
"do_not_use_syscalls": true,
|
||||
"verbose": false,
|
||||
"use_wch_printffloat": false,
|
||||
"use_wch_printf": true,
|
||||
"use_iqmath": false,
|
||||
"other_linker_flags": "-Wl,--print-memory-usage"
|
||||
}
|
||||
},
|
||||
"archiver": {
|
||||
"archiver_flags": "-r"
|
||||
},
|
||||
"createFlash": {
|
||||
"enabled": true,
|
||||
"outputFileFormat": "ihex",
|
||||
"copy_only_section_text": false,
|
||||
"copy_only_section_data": false,
|
||||
"copy_only_sections": [],
|
||||
"other_flags": ""
|
||||
},
|
||||
"createList": {
|
||||
"enabled": true,
|
||||
"display_source": false,
|
||||
"display_all_headers": true,
|
||||
"demangle_names": true,
|
||||
"display_debug_info": false,
|
||||
"disassemble": true,
|
||||
"display_file_headers": false,
|
||||
"display_line_numbers": false,
|
||||
"display_relocation_info": false,
|
||||
"display_symbols": false,
|
||||
"wide_lines": false,
|
||||
"other_flags": ""
|
||||
},
|
||||
"printSize": {
|
||||
"enabled": false,
|
||||
"size_format": "berkeley",
|
||||
"hex": false,
|
||||
"show_totals": false,
|
||||
"other_flags": ""
|
||||
},
|
||||
"riscvTargetProcessor": {
|
||||
"architecture": "rv32i",
|
||||
"multiply_extension": true,
|
||||
"atomic_extension": true,
|
||||
"floating_point": "none",
|
||||
"compressed_extension": true,
|
||||
"extra_compressed_extension": false,
|
||||
"bit_extension": false,
|
||||
"multiplication_subset_of_the_M_extension": false,
|
||||
"integer_ABI": "ilp32",
|
||||
"floating_point_ABI": "none",
|
||||
"tuning": "default",
|
||||
"code_model": "default",
|
||||
"small_data_limit": 8,
|
||||
"align": "default",
|
||||
"save_restore": true,
|
||||
"other_target_flags": ""
|
||||
},
|
||||
"component_toolchain": "${WCH:Toolchain:GCC12}",
|
||||
"name": "build",
|
||||
"configVariables": []
|
||||
}
|
||||
]
|
||||
},
|
||||
"flashConfig": {
|
||||
"mcutype": "CH32V10x",
|
||||
"address": "0x08000000",
|
||||
"target_path": "build\\mijia_haier_bridge.hex",
|
||||
"clkSpeed": "High",
|
||||
"debug_interface_mode": "1-wire serial",
|
||||
"erase": true,
|
||||
"program": true,
|
||||
"verify": false,
|
||||
"reset": true,
|
||||
"sdiPrintf": false,
|
||||
"disablepowerout": false,
|
||||
"clearcodeflash": false,
|
||||
"disablecodeprotect": false,
|
||||
"exepath": "",
|
||||
"exearguments": ""
|
||||
},
|
||||
"debugConfigurations": {
|
||||
"openOCDCfg": {
|
||||
"useLocalOpenOCD": true,
|
||||
"executable": "${WCH:OpenOCD:default}",
|
||||
"gdbport": 3333,
|
||||
"telnetport": 4444,
|
||||
"tclport": 6666,
|
||||
"configOptions": [
|
||||
"-f \"${WCH:OpenOCD:default}/bin/wch-riscv.cfg\""
|
||||
],
|
||||
"host": "localhost",
|
||||
"port": 3333,
|
||||
"skipDownloadBeforeDebug": false,
|
||||
"enablePageEraser": false,
|
||||
"enableNoZeroWaitingAreaFlash": false
|
||||
},
|
||||
"gdbCfg": {
|
||||
"executable": "${WCH:Toolchain:GCC12}",
|
||||
"options": [],
|
||||
"commands": [
|
||||
"set mem inaccessible-by-default off",
|
||||
"set architecture riscv:rv32",
|
||||
"set remotetimeout unlimited"
|
||||
]
|
||||
},
|
||||
"startup": {
|
||||
"initCommands": {
|
||||
"initReset": true,
|
||||
"initResetType": "init",
|
||||
"additionalCommands": [],
|
||||
"armSemihosting": false,
|
||||
"armSemihosting_old": false
|
||||
},
|
||||
"loadedFiles": {
|
||||
"loadSymbols": true,
|
||||
"useProjBinaryForSymbols": true,
|
||||
"useFileForSymbols": false,
|
||||
"symbolFile": "",
|
||||
"symbolFileOffset": "",
|
||||
"loadImage": true,
|
||||
"useProjBinaryForImage": true,
|
||||
"useFileForImage": false,
|
||||
"executableFile": "",
|
||||
"executableFileOffset": ""
|
||||
},
|
||||
"runCommands": {
|
||||
"runReset": true,
|
||||
"runResetType": "halt",
|
||||
"additionalCommands": [],
|
||||
"setBreakAt": "handle_reset",
|
||||
"continue": true,
|
||||
"setBreak": true,
|
||||
"setProgramCounter": false,
|
||||
"setProgramCounterAddress": ""
|
||||
},
|
||||
"debugInRAM": false
|
||||
},
|
||||
"svdpath": "${WCH:SDK:default}/RISC-V/CH32L103/NoneOS/CH32L103xx.svd",
|
||||
"output": {
|
||||
"showDebugGDBTrace": true,
|
||||
"saveDebugOutputToFile": false,
|
||||
"showDebugOutputTimestamps": true
|
||||
},
|
||||
"reserve": {
|
||||
"PROGRAM_NAME": "obj/mijia_haier_bridge.elf",
|
||||
"PROJECT_ATTR": "mijia_haier_bridge",
|
||||
"PROJECT_BUILD_CONFIG_AUTO_ATTR": true,
|
||||
"PROJECT_BUILD_CONFIG_ID_ATTR": "",
|
||||
"ATTR_BUILD_BEFORE_LAUNCH_ATTR": 2,
|
||||
"GdbServerAllocateConsole": true,
|
||||
"GdbServerAllocateTelnetConsole": false,
|
||||
"StartGdbCLient": true,
|
||||
"UPDATE_THREADLIST_ON_SUSPEND": false
|
||||
}
|
||||
}
|
||||
}
|
||||
303
mijia_haier_bridge/src/core/core_riscv.c
Normal file
303
mijia_haier_bridge/src/core/core_riscv.c
Normal file
@ -0,0 +1,303 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : core_riscv.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.1
|
||||
* Date : 2023/11/11
|
||||
* Description : RISC-V V3 Core Peripheral Access Layer Source File for CH32V10x
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include <stdint.h>
|
||||
|
||||
/* define compiler specific symbols */
|
||||
#if defined(__CC_ARM)
|
||||
#define __ASM __asm /* asm keyword for ARM Compiler */
|
||||
#define __INLINE __inline /* inline keyword for ARM Compiler */
|
||||
|
||||
#elif defined(__ICCARM__)
|
||||
#define __ASM __asm /* asm keyword for IAR Compiler */
|
||||
#define __INLINE inline /* inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
|
||||
|
||||
#elif defined(__GNUC__)
|
||||
#define __ASM __asm /* asm keyword for GNU Compiler */
|
||||
#define __INLINE inline /* inline keyword for GNU Compiler */
|
||||
|
||||
#elif defined(__TASKING__)
|
||||
#define __ASM __asm /* asm keyword for TASKING Compiler */
|
||||
#define __INLINE inline /* inline keyword for TASKING Compiler */
|
||||
|
||||
#endif
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MSTATUS
|
||||
*
|
||||
* @brief Return the Machine Status Register
|
||||
*
|
||||
* @return mstatus value
|
||||
*/
|
||||
uint32_t __get_MSTATUS(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("csrr %0," "mstatus": "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __set_MSTATUS
|
||||
*
|
||||
* @brief Set the Machine Status Register
|
||||
*
|
||||
* @param value - set mstatus value
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void __set_MSTATUS(uint32_t value)
|
||||
{
|
||||
__ASM volatile("csrw mstatus, %0" : : "r"(value));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MISA
|
||||
*
|
||||
* @brief Return the Machine ISA Register
|
||||
*
|
||||
* @return misa value
|
||||
*/
|
||||
uint32_t __get_MISA(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("csrr %0,""misa" : "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __set_MISA
|
||||
*
|
||||
* @brief Set the Machine ISA Register
|
||||
*
|
||||
* @param value - set misa value
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void __set_MISA(uint32_t value)
|
||||
{
|
||||
__ASM volatile("csrw misa, %0" : : "r"(value));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MTVEC
|
||||
*
|
||||
* @brief Return the Machine Trap-Vector Base-Address Register
|
||||
*
|
||||
* @return mtvec value
|
||||
*/
|
||||
uint32_t __get_MTVEC(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("csrr %0," "mtvec": "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __set_MTVEC
|
||||
*
|
||||
* @brief Set the Machine Trap-Vector Base-Address Register
|
||||
*
|
||||
* @param value - set mtvec value
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void __set_MTVEC(uint32_t value)
|
||||
{
|
||||
__ASM volatile("csrw mtvec, %0":: "r"(value));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MSCRATCH
|
||||
*
|
||||
* @brief Return the Machine Seratch Register
|
||||
*
|
||||
* @return mscratch value
|
||||
*/
|
||||
uint32_t __get_MSCRATCH(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("csrr %0," "mscratch" : "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __set_MSCRATCH
|
||||
*
|
||||
* @brief Set the Machine Seratch Register
|
||||
*
|
||||
* @param value - set mscratch value
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void __set_MSCRATCH(uint32_t value)
|
||||
{
|
||||
__ASM volatile("csrw mscratch, %0" : : "r"(value));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MEPC
|
||||
*
|
||||
* @brief Return the Machine Exception Program Register
|
||||
*
|
||||
* @return mepc value
|
||||
*/
|
||||
uint32_t __get_MEPC(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("csrr %0," "mepc" : "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __set_MEPC
|
||||
*
|
||||
* @brief Set the Machine Exception Program Register
|
||||
*
|
||||
* @return mepc value
|
||||
*/
|
||||
void __set_MEPC(uint32_t value)
|
||||
{
|
||||
__ASM volatile("csrw mepc, %0" : : "r"(value));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MCAUSE
|
||||
*
|
||||
* @brief Return the Machine Cause Register
|
||||
*
|
||||
* @return mcause value
|
||||
*/
|
||||
uint32_t __get_MCAUSE(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("csrr %0," "mcause": "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __set_MEPC
|
||||
*
|
||||
* @brief Set the Machine Cause Register
|
||||
*
|
||||
* @return mcause value
|
||||
*/
|
||||
void __set_MCAUSE(uint32_t value)
|
||||
{
|
||||
__ASM volatile("csrw mcause, %0":: "r"(value));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MTVAL
|
||||
*
|
||||
* @brief Return the Machine Trap Value Register
|
||||
*
|
||||
* @return mtval value
|
||||
*/
|
||||
uint32_t __get_MTVAL(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("csrr %0," "mtval" : "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __set_MTVAL
|
||||
*
|
||||
* @brief Set the Machine Trap Value Register
|
||||
*
|
||||
* @return mtval value
|
||||
*/
|
||||
void __set_MTVAL(uint32_t value)
|
||||
{
|
||||
__ASM volatile("csrw mtval, %0":: "r"(value));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MVENDORID
|
||||
*
|
||||
* @brief Return Vendor ID Register
|
||||
*
|
||||
* @return mvendorid value
|
||||
*/
|
||||
uint32_t __get_MVENDORID(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("csrr %0,""mvendorid": "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MARCHID
|
||||
*
|
||||
* @brief Return Machine Architecture ID Register
|
||||
*
|
||||
* @return marchid value
|
||||
*/
|
||||
uint32_t __get_MARCHID(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("csrr %0,""marchid": "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MIMPID
|
||||
*
|
||||
* @brief Return Machine Implementation ID Register
|
||||
*
|
||||
* @return mimpid value
|
||||
*/
|
||||
uint32_t __get_MIMPID(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("csrr %0,""mimpid": "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_MHARTID
|
||||
*
|
||||
* @brief Return Hart ID Register
|
||||
*
|
||||
* @return mhartid value
|
||||
*/
|
||||
uint32_t __get_MHARTID(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("csrr %0,""mhartid": "=r"(result));
|
||||
return (result);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __get_SP
|
||||
*
|
||||
* @brief Return SP Register
|
||||
*
|
||||
* @return SP value
|
||||
*/
|
||||
uint32_t __get_SP(void)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__ASM volatile("mv %0,""sp": "=r"(result):);
|
||||
return (result);
|
||||
}
|
||||
629
mijia_haier_bridge/src/core/core_riscv.h
Normal file
629
mijia_haier_bridge/src/core/core_riscv.h
Normal file
@ -0,0 +1,629 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : core_riscv.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.1
|
||||
* Date : 2023/11/11
|
||||
* Description : RISC-V V3 Core Peripheral Access Layer Header File for CH32V10x
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CORE_RISCV_H__
|
||||
#define __CORE_RISCV_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
|
||||
/* IO definitions */
|
||||
#ifdef __cplusplus
|
||||
#define __I volatile /* defines 'read only' permissions */
|
||||
#else
|
||||
#define __I volatile const /* defines 'read only' permissions */
|
||||
#endif
|
||||
#define __O volatile /* defines 'write only' permissions */
|
||||
#define __IO volatile /* defines 'read / write' permissions */
|
||||
|
||||
/* Standard Peripheral Library old types (maintained for legacy purpose) */
|
||||
typedef __I uint32_t vuc32; /* Read Only */
|
||||
typedef __I uint16_t vuc16; /* Read Only */
|
||||
typedef __I uint8_t vuc8; /* Read Only */
|
||||
|
||||
typedef const uint32_t uc32; /* Read Only */
|
||||
typedef const uint16_t uc16; /* Read Only */
|
||||
typedef const uint8_t uc8; /* Read Only */
|
||||
|
||||
typedef __I int32_t vsc32; /* Read Only */
|
||||
typedef __I int16_t vsc16; /* Read Only */
|
||||
typedef __I int8_t vsc8; /* Read Only */
|
||||
|
||||
typedef const int32_t sc32; /* Read Only */
|
||||
typedef const int16_t sc16; /* Read Only */
|
||||
typedef const int8_t sc8; /* Read Only */
|
||||
|
||||
typedef __IO uint32_t vu32;
|
||||
typedef __IO uint16_t vu16;
|
||||
typedef __IO uint8_t vu8;
|
||||
|
||||
typedef uint32_t u32;
|
||||
typedef uint16_t u16;
|
||||
typedef uint8_t u8;
|
||||
|
||||
typedef __IO int32_t vs32;
|
||||
typedef __IO int16_t vs16;
|
||||
typedef __IO int8_t vs8;
|
||||
|
||||
typedef int32_t s32;
|
||||
typedef int16_t s16;
|
||||
typedef int8_t s8;
|
||||
|
||||
typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus;
|
||||
|
||||
typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
|
||||
|
||||
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
|
||||
|
||||
#define RV_STATIC_INLINE static inline
|
||||
|
||||
/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */
|
||||
typedef struct{
|
||||
__I uint32_t ISR[8];
|
||||
__I uint32_t IPR[8];
|
||||
__IO uint32_t ITHRESDR;
|
||||
__IO uint32_t VTFBADDRR;
|
||||
__IO uint32_t CFGR;
|
||||
__I uint32_t GISR;
|
||||
uint8_t RESERVED0[0x10];
|
||||
__IO uint32_t VTFADDRR[4];
|
||||
uint8_t RESERVED1[0x90];
|
||||
__O uint32_t IENR[8];
|
||||
uint8_t RESERVED2[0x60];
|
||||
__O uint32_t IRER[8];
|
||||
uint8_t RESERVED3[0x60];
|
||||
__O uint32_t IPSR[8];
|
||||
uint8_t RESERVED4[0x60];
|
||||
__O uint32_t IPRR[8];
|
||||
uint8_t RESERVED5[0x60];
|
||||
__IO uint32_t IACTR[8];
|
||||
uint8_t RESERVED6[0xE0];
|
||||
__IO uint8_t IPRIOR[256];
|
||||
uint8_t RESERVED7[0x810];
|
||||
__IO uint32_t SCTLR;
|
||||
}PFIC_Type;
|
||||
|
||||
#define FIBADDRR VTFBADDRR
|
||||
#define FIOFADDRR VTFADDRR
|
||||
|
||||
|
||||
/* memory mapped structure for SysTick */
|
||||
typedef struct
|
||||
{
|
||||
__IO uint32_t CTLR;
|
||||
__IO uint8_t CNTL0;
|
||||
__IO uint8_t CNTL1;
|
||||
__IO uint8_t CNTL2;
|
||||
__IO uint8_t CNTL3;
|
||||
__IO uint8_t CNTH0;
|
||||
__IO uint8_t CNTH1;
|
||||
__IO uint8_t CNTH2;
|
||||
__IO uint8_t CNTH3;
|
||||
__IO uint8_t CMPLR0;
|
||||
__IO uint8_t CMPLR1;
|
||||
__IO uint8_t CMPLR2;
|
||||
__IO uint8_t CMPLR3;
|
||||
__IO uint8_t CMPHR0;
|
||||
__IO uint8_t CMPHR1;
|
||||
__IO uint8_t CMPHR2;
|
||||
__IO uint8_t CMPHR3;
|
||||
}SysTick_Type;
|
||||
|
||||
|
||||
#define PFIC ((PFIC_Type *) 0xE000E000 )
|
||||
#define NVIC PFIC
|
||||
#define NVIC_KEY1 ((uint32_t)0xFA050000)
|
||||
#define NVIC_KEY2 ((uint32_t)0xBCAF0000)
|
||||
#define NVIC_KEY3 ((uint32_t)0xBEEF0000)
|
||||
|
||||
#define SysTick ((SysTick_Type *) 0xE000F000)
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __enable_irq
|
||||
* This function is only used for Machine mode.
|
||||
*
|
||||
* @brief Enable Global Interrupt
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __enable_irq()
|
||||
{
|
||||
__asm volatile ("csrs mstatus, %0" : : "r" (0x88) );
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __disable_irq
|
||||
* This function is only used for Machine mode.
|
||||
*
|
||||
* @brief Disable Global Interrupt
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __disable_irq()
|
||||
{
|
||||
__asm volatile ("csrc mstatus, %0" : : "r" (0x88) );
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __NOP
|
||||
*
|
||||
* @brief nop
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __NOP()
|
||||
{
|
||||
__asm volatile ("nop");
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_EnableIRQ
|
||||
*
|
||||
* @brief Enable Interrupt
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_DisableIRQ
|
||||
*
|
||||
* @brief Disable Interrupt
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
uint32_t t;
|
||||
|
||||
t = NVIC->ITHRESDR;
|
||||
NVIC->ITHRESDR = 0x10;
|
||||
NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||
NVIC->ITHRESDR = t;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_GetStatusIRQ
|
||||
*
|
||||
* @brief Get Interrupt Enable State
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
*
|
||||
* @return 1 - Interrupt Enable
|
||||
* 0 - Interrupt Disable
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_GetPendingIRQ
|
||||
*
|
||||
* @brief Get Interrupt Pending State
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
*
|
||||
* @return 1 - Interrupt Pending Enable
|
||||
* 0 - Interrupt Pending Disable
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_SetPendingIRQ
|
||||
*
|
||||
* @brief Set Interrupt Pending
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_ClearPendingIRQ
|
||||
*
|
||||
* @brief Clear Interrupt Pending
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||
{
|
||||
NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_GetActive
|
||||
*
|
||||
* @brief Get Interrupt Active State
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
*
|
||||
* @return 1 - Interrupt Active
|
||||
* 0 - Interrupt No Active
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
|
||||
{
|
||||
return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_SetPriority
|
||||
*
|
||||
* @brief Set Interrupt Priority
|
||||
*
|
||||
* @param IRQn - Interrupt Numbers
|
||||
* interrupt nesting enable(PFIC->CFGR bit1 = 0)
|
||||
* priority - bit[7] - Preemption Priority
|
||||
* bit[6:4] - Sub priority
|
||||
* bit[3:0] - Reserve
|
||||
* interrupt nesting disable(PFIC->CFGR bit1 = 1)
|
||||
* priority - bit[7:4] - Sub priority
|
||||
* bit[3:0] - Reserve
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority)
|
||||
{
|
||||
NVIC->IPRIOR[(uint32_t)(IRQn)] = priority;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __WFI
|
||||
*
|
||||
* @brief Wait for Interrupt
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void)
|
||||
{
|
||||
NVIC->SCTLR &= ~(1<<3); // wfi
|
||||
asm volatile ("wfi");
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn _SEV
|
||||
*
|
||||
* @brief Set Event
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _SEV(void)
|
||||
{
|
||||
NVIC->SCTLR |= (1<<3)|(1<<5);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn _WFE
|
||||
*
|
||||
* @brief Wait for Events
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _WFE(void)
|
||||
{
|
||||
NVIC->SCTLR |= (1<<3);
|
||||
asm volatile ("wfi");
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __WFE
|
||||
*
|
||||
* @brief Wait for Events
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void)
|
||||
{
|
||||
_SEV();
|
||||
_WFE();
|
||||
_WFE();
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_SetFastIRQ
|
||||
*
|
||||
* @brief Set VTF Interrupt
|
||||
*
|
||||
* @param add - VTF interrupt service function base address.
|
||||
* IRQn - Interrupt Numbers
|
||||
* num - VTF Interrupt Numbers
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetFastIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num)
|
||||
{
|
||||
if(num > 3) return ;
|
||||
NVIC->VTFBADDRR = addr;
|
||||
NVIC->VTFADDRR[num] = ((uint32_t)IRQn<<24)|(addr&0xfffff);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_SystemReset
|
||||
*
|
||||
* @brief Initiate a system reset request
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SystemReset(void)
|
||||
{
|
||||
NVIC->CFGR = NVIC_KEY3|(1<<7);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_HaltPushCfg
|
||||
*
|
||||
* @brief Enable Hardware Stack
|
||||
*
|
||||
* @param NewState - DISABLE or ENABLE
|
||||
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_HaltPushCfg(FunctionalState NewState)
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
NVIC->CFGR = NVIC_KEY1;
|
||||
}
|
||||
else
|
||||
{
|
||||
NVIC->CFGR = NVIC_KEY1|(1<<0);
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_INTNestCfg
|
||||
*
|
||||
* @brief Enable Interrupt Nesting
|
||||
*
|
||||
* @param NewState - DISABLE or ENABLE
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_INTNestCfg(FunctionalState NewState)
|
||||
{
|
||||
if (NewState != DISABLE)
|
||||
{
|
||||
NVIC->CFGR = NVIC_KEY1;
|
||||
}
|
||||
else
|
||||
{
|
||||
NVIC->CFGR = NVIC_KEY1|(1<<1);
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOADD_W
|
||||
*
|
||||
* @brief Atomic Add with 32bit value
|
||||
* Atomically ADD 32bit value with value in memory using amoadd.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* value - value to be ADDed
|
||||
*
|
||||
* @return return memory value + add value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value)
|
||||
{
|
||||
int32_t result;
|
||||
|
||||
__asm volatile ("amoadd.w %0, %2, %1" : \
|
||||
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||
return *addr;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOAND_W
|
||||
*
|
||||
* @brief Atomic And with 32bit value
|
||||
* Atomically AND 32bit value with value in memory using amoand.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* value - value to be ANDed
|
||||
*
|
||||
* @return return memory value & and value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value)
|
||||
{
|
||||
int32_t result;
|
||||
|
||||
__asm volatile ("amoand.w %0, %2, %1" : \
|
||||
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||
return *addr;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOMAX_W
|
||||
*
|
||||
* @brief Atomic signed MAX with 32bit value
|
||||
* Atomically signed max compare 32bit value with value in memory using amomax.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* value - value to be compared
|
||||
*
|
||||
* @return return the bigger value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value)
|
||||
{
|
||||
int32_t result;
|
||||
|
||||
__asm volatile ("amomax.w %0, %2, %1" : \
|
||||
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||
return *addr;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOMAXU_W
|
||||
*
|
||||
* @brief Atomic unsigned MAX with 32bit value
|
||||
* Atomically unsigned max compare 32bit value with value in memory using amomaxu.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* value - value to be compared
|
||||
*
|
||||
* @return return the bigger value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__asm volatile ("amomaxu.w %0, %2, %1" : \
|
||||
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||
return *addr;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOMIN_W
|
||||
*
|
||||
* @brief Atomic signed MIN with 32bit value
|
||||
* Atomically signed min compare 32bit value with value in memory using amomin.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* value - value to be compared
|
||||
*
|
||||
* @return return the smaller value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value)
|
||||
{
|
||||
int32_t result;
|
||||
|
||||
__asm volatile ("amomin.w %0, %2, %1" : \
|
||||
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||
return *addr;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOMINU_W
|
||||
*
|
||||
* @brief Atomic unsigned MIN with 32bit value
|
||||
* Atomically unsigned min compare 32bit value with value in memory using amominu.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* value - value to be compared
|
||||
*
|
||||
* @return return the smaller value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__asm volatile ("amominu.w %0, %2, %1" : \
|
||||
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||
return *addr;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOOR_W
|
||||
*
|
||||
* @brief Atomic OR with 32bit value
|
||||
* Atomically OR 32bit value with value in memory using amoor.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* value - value to be ORed
|
||||
*
|
||||
* @return return memory value | and value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value)
|
||||
{
|
||||
int32_t result;
|
||||
|
||||
__asm volatile ("amoor.w %0, %2, %1" : \
|
||||
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||
return *addr;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOSWAP_W
|
||||
*
|
||||
* @brief Atomically swap new 32bit value into memory using amoswap.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* newval - New value to be stored into the address
|
||||
*
|
||||
* @return return the original value in memory
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval)
|
||||
{
|
||||
uint32_t result;
|
||||
|
||||
__asm volatile ("amoswap.w %0, %2, %1" : \
|
||||
"=r"(result), "+A"(*addr) : "r"(newval) : "memory");
|
||||
return result;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn __AMOXOR_W
|
||||
*
|
||||
* @brief Atomic XOR with 32bit value
|
||||
* Atomically XOR 32bit value with value in memory using amoxor.d.
|
||||
*
|
||||
* @param addr - Address pointer to data, address need to be 4byte aligned
|
||||
* value - value to be XORed
|
||||
*
|
||||
* @return return memory value ^ and value
|
||||
*/
|
||||
__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value)
|
||||
{
|
||||
int32_t result;
|
||||
|
||||
__asm volatile ("amoxor.w %0, %2, %1" : \
|
||||
"=r"(result), "+A"(*addr) : "r"(value) : "memory");
|
||||
return *addr;
|
||||
}
|
||||
|
||||
/* Core_Exported_Functions */
|
||||
extern uint32_t __get_MSTATUS(void);
|
||||
extern void __set_MSTATUS(uint32_t value);
|
||||
extern uint32_t __get_MISA(void);
|
||||
extern void __set_MISA(uint32_t value);
|
||||
extern uint32_t __get_MTVEC(void);
|
||||
extern void __set_MTVEC(uint32_t value);
|
||||
extern uint32_t __get_MSCRATCH(void);
|
||||
extern void __set_MSCRATCH(uint32_t value);
|
||||
extern uint32_t __get_MEPC(void);
|
||||
extern void __set_MEPC(uint32_t value);
|
||||
extern uint32_t __get_MCAUSE(void);
|
||||
extern void __set_MCAUSE(uint32_t value);
|
||||
extern uint32_t __get_MTVAL(void);
|
||||
extern void __set_MTVAL(uint32_t value);
|
||||
extern uint32_t __get_MVENDORID(void);
|
||||
extern uint32_t __get_MARCHID(void);
|
||||
extern uint32_t __get_MIMPID(void);
|
||||
extern uint32_t __get_MHARTID(void);
|
||||
extern uint32_t __get_SP(void);
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif/* __CORE_RISCV_H__ */
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
146
mijia_haier_bridge/src/core/ld_ch32v10x.ld
Normal file
146
mijia_haier_bridge/src/core/ld_ch32v10x.ld
Normal file
@ -0,0 +1,146 @@
|
||||
ENTRY( _start )
|
||||
|
||||
__stack_size = 2048;
|
||||
|
||||
PROVIDE( _stack_size = __stack_size );
|
||||
|
||||
MEMORY
|
||||
{
|
||||
FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K
|
||||
RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.init : {
|
||||
_sinit = .;
|
||||
. = ALIGN(4);
|
||||
KEEP(*(SORT_NONE(.init)))
|
||||
. = ALIGN(4);
|
||||
_einit = .;
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.vector : {
|
||||
*(.vector);
|
||||
. = ALIGN(64);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.text : {
|
||||
. = ALIGN(4);
|
||||
*(.text)
|
||||
*(.text.*)
|
||||
*(.rodata)
|
||||
*(.rodata*)
|
||||
*(.gnu.linkonce.t.*)
|
||||
. = ALIGN(4);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.fini : {
|
||||
KEEP(*(SORT_NONE(.fini)))
|
||||
. = ALIGN(4);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
PROVIDE( _etext = . );
|
||||
PROVIDE( _eitcm = . );
|
||||
|
||||
.preinit_array : {
|
||||
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||
KEEP (*(.preinit_array))
|
||||
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.init_array : {
|
||||
PROVIDE_HIDDEN (__init_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
|
||||
KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
|
||||
PROVIDE_HIDDEN (__init_array_end = .);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.fini_array : {
|
||||
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||
KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
|
||||
KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
|
||||
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.ctors : {
|
||||
/* gcc uses crtbegin.o to find the start of
|
||||
the constructors, so we make sure it is
|
||||
first. Because this is a wildcard, it
|
||||
doesn't matter if the user does not
|
||||
actually link against crtbegin.o; the
|
||||
linker won't look for a file to match a
|
||||
wildcard. The wildcard also means that it
|
||||
doesn't matter which directory crtbegin.o
|
||||
is in. */
|
||||
KEEP (*crtbegin.o(.ctors))
|
||||
KEEP (*crtbegin?.o(.ctors))
|
||||
/* We don't want to include the .ctor section from
|
||||
the crtend.o file until after the sorted ctors.
|
||||
The .ctor section from the crtend file contains the
|
||||
end of ctors marker and it must be last */
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
|
||||
KEEP (*(SORT(.ctors.*)))
|
||||
KEEP (*(.ctors))
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.dtors : {
|
||||
KEEP (*crtbegin.o(.dtors))
|
||||
KEEP (*crtbegin?.o(.dtors))
|
||||
KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
|
||||
KEEP (*(SORT(.dtors.*)))
|
||||
KEEP (*(.dtors))
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.dalign : {
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_data_vma = .);
|
||||
} >RAM AT>FLASH
|
||||
|
||||
.dlalign : {
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_data_lma = .);
|
||||
} >FLASH AT>FLASH
|
||||
|
||||
.data : {
|
||||
*(.gnu.linkonce.r.*)
|
||||
*(.data .data.*)
|
||||
*(.gnu.linkonce.d.*)
|
||||
. = ALIGN(8);
|
||||
PROVIDE( __global_pointer$ = . + 0x800 );
|
||||
*(.sdata .sdata.*)
|
||||
*(.sdata2.*)
|
||||
*(.gnu.linkonce.s.*)
|
||||
. = ALIGN(8);
|
||||
*(.srodata.cst16)
|
||||
*(.srodata.cst8)
|
||||
*(.srodata.cst4)
|
||||
*(.srodata.cst2)
|
||||
*(.srodata .srodata.*)
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _edata = .);
|
||||
} >RAM AT>FLASH
|
||||
|
||||
.bss : {
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _sbss = .);
|
||||
*(.sbss*)
|
||||
*(.gnu.linkonce.sb.*)
|
||||
*(.bss*)
|
||||
*(.gnu.linkonce.b.*)
|
||||
*(COMMON*)
|
||||
. = ALIGN(4);
|
||||
PROVIDE( _ebss = .);
|
||||
} >RAM AT>FLASH
|
||||
|
||||
PROVIDE( _end = _ebss);
|
||||
PROVIDE( end = . );
|
||||
|
||||
.stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : {
|
||||
PROVIDE( _heap_end = . );
|
||||
. = ALIGN(4);
|
||||
PROVIDE(_susrstack = . );
|
||||
. = . + __stack_size;
|
||||
PROVIDE( _eusrstack = .);
|
||||
} >RAM
|
||||
}
|
||||
237
mijia_haier_bridge/src/core/startup_ch32v10x.S
Normal file
237
mijia_haier_bridge/src/core/startup_ch32v10x.S
Normal file
@ -0,0 +1,237 @@
|
||||
;/********************************** (C) COPYRIGHT *******************************
|
||||
;* File Name : startup_ch32v10x.s
|
||||
;* Author : WCH
|
||||
;* Version : V1.0.1
|
||||
;* Date : 2024/01/11
|
||||
;* Description : CH32V10x vector table for eclipse toolchain.
|
||||
;*********************************************************************************
|
||||
;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
;* Attention: This software (modified or not) and binary are used for
|
||||
;* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
;*******************************************************************************/
|
||||
|
||||
.section .init,"ax",@progbits
|
||||
.global _start
|
||||
.align 1
|
||||
_start:
|
||||
j handle_reset
|
||||
.word 0x00000013
|
||||
.word 0x00000013
|
||||
.word 0x00000013
|
||||
.word 0x00000013
|
||||
.word 0x00000013
|
||||
.word 0x00000013
|
||||
.word 0x00000013
|
||||
.word 0x00000013
|
||||
.word 0x00000013
|
||||
.word 0x00000013
|
||||
.word 0x00000013
|
||||
.word 0x00000013
|
||||
.word 0x00100073
|
||||
|
||||
.section .vector,"ax",@progbits
|
||||
.align 1
|
||||
_vector_base:
|
||||
.option norvc;
|
||||
j _start
|
||||
.word 0
|
||||
j NMI_Handler /* NMI Handler */
|
||||
j HardFault_Handler /* Hard Fault Handler */
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
j SysTick_Handler /* SysTick Handler */
|
||||
.word 0
|
||||
j SW_Handler /* SW Handler */
|
||||
.word 0
|
||||
/* External Interrupts */
|
||||
j WWDG_IRQHandler /* Window Watchdog */
|
||||
j PVD_IRQHandler /* PVD through EXTI Line detect */
|
||||
j TAMPER_IRQHandler /* TAMPER */
|
||||
j RTC_IRQHandler /* RTC */
|
||||
j FLASH_IRQHandler /* Flash */
|
||||
j RCC_IRQHandler /* RCC */
|
||||
j EXTI0_IRQHandler /* EXTI Line 0 */
|
||||
j EXTI1_IRQHandler /* EXTI Line 1 */
|
||||
j EXTI2_IRQHandler /* EXTI Line 2 */
|
||||
j EXTI3_IRQHandler /* EXTI Line 3 */
|
||||
j EXTI4_IRQHandler /* EXTI Line 4 */
|
||||
j DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */
|
||||
j DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */
|
||||
j DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */
|
||||
j DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */
|
||||
j DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */
|
||||
j DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */
|
||||
j DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */
|
||||
j ADC1_2_IRQHandler /* ADC1_2 */
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
.word 0
|
||||
j EXTI9_5_IRQHandler /* EXTI Line 9..5 */
|
||||
j TIM1_BRK_IRQHandler /* TIM1 Break */
|
||||
j TIM1_UP_IRQHandler /* TIM1 Update */
|
||||
j TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */
|
||||
j TIM1_CC_IRQHandler /* TIM1 Capture Compare */
|
||||
j TIM2_IRQHandler /* TIM2 */
|
||||
j TIM3_IRQHandler /* TIM3 */
|
||||
j TIM4_IRQHandler /* TIM4 */
|
||||
j I2C1_EV_IRQHandler /* I2C1 Event */
|
||||
j I2C1_ER_IRQHandler /* I2C1 Error */
|
||||
j I2C2_EV_IRQHandler /* I2C2 Event */
|
||||
j I2C2_ER_IRQHandler /* I2C2 Error */
|
||||
j SPI1_IRQHandler /* SPI1 */
|
||||
j SPI2_IRQHandler /* SPI2 */
|
||||
j USART1_IRQHandler /* USART1 */
|
||||
j USART2_IRQHandler /* USART2 */
|
||||
j USART3_IRQHandler /* USART3 */
|
||||
j EXTI15_10_IRQHandler /* EXTI Line 15..10 */
|
||||
j RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */
|
||||
j USBWakeUp_IRQHandler /* USB Wakeup from suspend */
|
||||
j USBFS_IRQHandler /* USBFS */
|
||||
|
||||
.option rvc;
|
||||
.section .text.vector_handler, "ax", @progbits
|
||||
.weak NMI_Handler
|
||||
.weak HardFault_Handler
|
||||
.weak SysTick_Handler
|
||||
.weak SW_Handler
|
||||
.weak WWDG_IRQHandler
|
||||
.weak PVD_IRQHandler
|
||||
.weak TAMPER_IRQHandler
|
||||
.weak RTC_IRQHandler
|
||||
.weak FLASH_IRQHandler
|
||||
.weak RCC_IRQHandler
|
||||
.weak EXTI0_IRQHandler
|
||||
.weak EXTI1_IRQHandler
|
||||
.weak EXTI2_IRQHandler
|
||||
.weak EXTI3_IRQHandler
|
||||
.weak EXTI4_IRQHandler
|
||||
.weak DMA1_Channel1_IRQHandler
|
||||
.weak DMA1_Channel2_IRQHandler
|
||||
.weak DMA1_Channel3_IRQHandler
|
||||
.weak DMA1_Channel4_IRQHandler
|
||||
.weak DMA1_Channel5_IRQHandler
|
||||
.weak DMA1_Channel6_IRQHandler
|
||||
.weak DMA1_Channel7_IRQHandler
|
||||
.weak ADC1_2_IRQHandler
|
||||
.weak EXTI9_5_IRQHandler
|
||||
.weak TIM1_BRK_IRQHandler
|
||||
.weak TIM1_UP_IRQHandler
|
||||
.weak TIM1_TRG_COM_IRQHandler
|
||||
.weak TIM1_CC_IRQHandler
|
||||
.weak TIM2_IRQHandler
|
||||
.weak TIM3_IRQHandler
|
||||
.weak TIM4_IRQHandler
|
||||
.weak I2C1_EV_IRQHandler
|
||||
.weak I2C1_ER_IRQHandler
|
||||
.weak I2C2_EV_IRQHandler
|
||||
.weak I2C2_ER_IRQHandler
|
||||
.weak SPI1_IRQHandler
|
||||
.weak SPI2_IRQHandler
|
||||
.weak USART1_IRQHandler
|
||||
.weak USART2_IRQHandler
|
||||
.weak USART3_IRQHandler
|
||||
.weak EXTI15_10_IRQHandler
|
||||
.weak RTCAlarm_IRQHandler
|
||||
.weak USBWakeUp_IRQHandler
|
||||
.weak USBFS_IRQHandler
|
||||
|
||||
NMI_Handler:
|
||||
HardFault_Handler:
|
||||
SysTick_Handler:
|
||||
SW_Handler:
|
||||
WWDG_IRQHandler:
|
||||
PVD_IRQHandler:
|
||||
TAMPER_IRQHandler:
|
||||
RTC_IRQHandler:
|
||||
FLASH_IRQHandler:
|
||||
RCC_IRQHandler:
|
||||
EXTI0_IRQHandler:
|
||||
EXTI1_IRQHandler:
|
||||
EXTI2_IRQHandler:
|
||||
EXTI3_IRQHandler:
|
||||
EXTI4_IRQHandler:
|
||||
DMA1_Channel1_IRQHandler:
|
||||
DMA1_Channel2_IRQHandler:
|
||||
DMA1_Channel3_IRQHandler:
|
||||
DMA1_Channel4_IRQHandler:
|
||||
DMA1_Channel5_IRQHandler:
|
||||
DMA1_Channel6_IRQHandler:
|
||||
DMA1_Channel7_IRQHandler:
|
||||
ADC1_2_IRQHandler:
|
||||
EXTI9_5_IRQHandler:
|
||||
TIM1_BRK_IRQHandler:
|
||||
TIM1_UP_IRQHandler:
|
||||
TIM1_TRG_COM_IRQHandler:
|
||||
TIM1_CC_IRQHandler:
|
||||
TIM2_IRQHandler:
|
||||
TIM3_IRQHandler:
|
||||
TIM4_IRQHandler:
|
||||
I2C1_EV_IRQHandler:
|
||||
I2C1_ER_IRQHandler:
|
||||
I2C2_EV_IRQHandler:
|
||||
I2C2_ER_IRQHandler:
|
||||
SPI1_IRQHandler:
|
||||
SPI2_IRQHandler:
|
||||
USART1_IRQHandler:
|
||||
USART2_IRQHandler:
|
||||
USART3_IRQHandler:
|
||||
EXTI15_10_IRQHandler:
|
||||
RTCAlarm_IRQHandler:
|
||||
USBWakeUp_IRQHandler:
|
||||
USBFS_IRQHandler:
|
||||
1:
|
||||
j 1b
|
||||
|
||||
.section .text.handle_reset,"ax",@progbits
|
||||
.weak handle_reset
|
||||
.align 1
|
||||
handle_reset:
|
||||
.option push
|
||||
.option norelax
|
||||
la gp, __global_pointer$
|
||||
.option pop
|
||||
1:
|
||||
la sp, _eusrstack
|
||||
2:
|
||||
/* Load data section from flash to RAM */
|
||||
la a0, _data_lma
|
||||
la a1, _data_vma
|
||||
la a2, _edata
|
||||
bgeu a1, a2, 2f
|
||||
1:
|
||||
lw t0, (a0)
|
||||
sw t0, (a1)
|
||||
addi a0, a0, 4
|
||||
addi a1, a1, 4
|
||||
bltu a1, a2, 1b
|
||||
2:
|
||||
/* Clear bss section */
|
||||
la a0, _sbss
|
||||
la a1, _ebss
|
||||
bgeu a0, a1, 2f
|
||||
1:
|
||||
sw zero, (a0)
|
||||
addi a0, a0, 4
|
||||
bltu a0, a1, 1b
|
||||
2:
|
||||
/* Enable global interrupt and configure privileged mode */
|
||||
li t0, 0x88
|
||||
csrw mstatus, t0
|
||||
/* Configure entry address mode */
|
||||
la t0, _vector_base
|
||||
ori t0, t0, 1
|
||||
csrw mtvec, t0
|
||||
|
||||
jal SystemInit
|
||||
la t0, main
|
||||
csrw mepc, t0
|
||||
mret
|
||||
|
||||
|
||||
3209
mijia_haier_bridge/src/periph/ch32v10x.h
Normal file
3209
mijia_haier_bridge/src/periph/ch32v10x.h
Normal file
File diff suppressed because it is too large
Load Diff
552
mijia_haier_bridge/src/periph/ch32v10x_dma.c
Normal file
552
mijia_haier_bridge/src/periph/ch32v10x_dma.c
Normal file
@ -0,0 +1,552 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v10x_dma.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2020/04/30
|
||||
* Description : This file provides all the DMA firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32v10x_dma.h"
|
||||
#include "ch32v10x_rcc.h"
|
||||
|
||||
/* DMA1 Channelx interrupt pending bit masks */
|
||||
#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1))
|
||||
#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2))
|
||||
#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3))
|
||||
#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4))
|
||||
#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5))
|
||||
#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6))
|
||||
#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7))
|
||||
|
||||
/* DMA2 Channelx interrupt pending bit masks */
|
||||
#define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1))
|
||||
#define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2))
|
||||
#define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3))
|
||||
#define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4))
|
||||
#define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5))
|
||||
|
||||
/* DMA2 FLAG mask */
|
||||
#define FLAG_Mask ((uint32_t)0x10000000)
|
||||
|
||||
/* DMA registers Masks */
|
||||
#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F)
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DMA_DeInit
|
||||
*
|
||||
* @brief Deinitializes the DMAy Channelx registers to their default
|
||||
* reset values.
|
||||
*
|
||||
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
|
||||
* 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx)
|
||||
{
|
||||
DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN);
|
||||
DMAy_Channelx->CFGR = 0;
|
||||
DMAy_Channelx->CNTR = 0;
|
||||
DMAy_Channelx->PADDR = 0;
|
||||
DMAy_Channelx->MADDR = 0;
|
||||
if(DMAy_Channelx == DMA1_Channel1)
|
||||
{
|
||||
DMA1->INTFCR |= DMA1_Channel1_IT_Mask;
|
||||
}
|
||||
else if(DMAy_Channelx == DMA1_Channel2)
|
||||
{
|
||||
DMA1->INTFCR |= DMA1_Channel2_IT_Mask;
|
||||
}
|
||||
else if(DMAy_Channelx == DMA1_Channel3)
|
||||
{
|
||||
DMA1->INTFCR |= DMA1_Channel3_IT_Mask;
|
||||
}
|
||||
else if(DMAy_Channelx == DMA1_Channel4)
|
||||
{
|
||||
DMA1->INTFCR |= DMA1_Channel4_IT_Mask;
|
||||
}
|
||||
else if(DMAy_Channelx == DMA1_Channel5)
|
||||
{
|
||||
DMA1->INTFCR |= DMA1_Channel5_IT_Mask;
|
||||
}
|
||||
else if(DMAy_Channelx == DMA1_Channel6)
|
||||
{
|
||||
DMA1->INTFCR |= DMA1_Channel6_IT_Mask;
|
||||
}
|
||||
else if(DMAy_Channelx == DMA1_Channel7)
|
||||
{
|
||||
DMA1->INTFCR |= DMA1_Channel7_IT_Mask;
|
||||
}
|
||||
else if(DMAy_Channelx == DMA2_Channel1)
|
||||
{
|
||||
DMA2->INTFCR |= DMA2_Channel1_IT_Mask;
|
||||
}
|
||||
else if(DMAy_Channelx == DMA2_Channel2)
|
||||
{
|
||||
DMA2->INTFCR |= DMA2_Channel2_IT_Mask;
|
||||
}
|
||||
else if(DMAy_Channelx == DMA2_Channel3)
|
||||
{
|
||||
DMA2->INTFCR |= DMA2_Channel3_IT_Mask;
|
||||
}
|
||||
else if(DMAy_Channelx == DMA2_Channel4)
|
||||
{
|
||||
DMA2->INTFCR |= DMA2_Channel4_IT_Mask;
|
||||
}
|
||||
else
|
||||
{
|
||||
if(DMAy_Channelx == DMA2_Channel5)
|
||||
{
|
||||
DMA2->INTFCR |= DMA2_Channel5_IT_Mask;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DMA_Init
|
||||
*
|
||||
* @brief Initializes the DMAy Channelx according to the specified
|
||||
* parameters in the DMA_InitStruct.
|
||||
*
|
||||
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
|
||||
* 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||
* DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains
|
||||
* contains the configuration information for the specified DMA Channel.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
tmpreg = DMAy_Channelx->CFGR;
|
||||
tmpreg &= CFGR_CLEAR_Mask;
|
||||
tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode |
|
||||
DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
|
||||
DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
|
||||
DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M;
|
||||
|
||||
DMAy_Channelx->CFGR = tmpreg;
|
||||
DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize;
|
||||
DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr;
|
||||
DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DMA_StructInit
|
||||
*
|
||||
* @brief Fills each DMA_InitStruct member with its default value.
|
||||
*
|
||||
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
|
||||
* 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||
* DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains
|
||||
* contains the configuration information for the specified DMA Channel.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct)
|
||||
{
|
||||
DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
|
||||
DMA_InitStruct->DMA_MemoryBaseAddr = 0;
|
||||
DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC;
|
||||
DMA_InitStruct->DMA_BufferSize = 0;
|
||||
DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
|
||||
DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
|
||||
DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
|
||||
DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
|
||||
DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
|
||||
DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
|
||||
DMA_InitStruct->DMA_M2M = DMA_M2M_Disable;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DMA_Cmd
|
||||
*
|
||||
* @brief Enables or disables the specified DMAy Channelx.
|
||||
*
|
||||
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
|
||||
* 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||
* NewState - new state of the DMAy Channelx(ENABLE or DISABLE).
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
DMAy_Channelx->CFGR |= DMA_CFGR1_EN;
|
||||
}
|
||||
else
|
||||
{
|
||||
DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN);
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DMA_ITConfig
|
||||
*
|
||||
* @brief Enables or disables the specified DMAy Channelx interrupts.
|
||||
*
|
||||
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
|
||||
* 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||
* DMA_IT - specifies the DMA interrupts sources to be enabled
|
||||
* or disabled.
|
||||
* DMA_IT_TC - Transfer complete interrupt mask
|
||||
* DMA_IT_HT - Half transfer interrupt mask
|
||||
* DMA_IT_TE - Transfer error interrupt mask
|
||||
* NewState - new state of the DMAy Channelx(ENABLE or DISABLE).
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
DMAy_Channelx->CFGR |= DMA_IT;
|
||||
}
|
||||
else
|
||||
{
|
||||
DMAy_Channelx->CFGR &= ~DMA_IT;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DMA_SetCurrDataCounter
|
||||
*
|
||||
* @brief Sets the number of data units in the current DMAy Channelx transfer.
|
||||
*
|
||||
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
|
||||
* 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||
* DataNumber - The number of data units in the current DMAy Channelx
|
||||
* transfer.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber)
|
||||
{
|
||||
DMAy_Channelx->CNTR = DataNumber;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DMA_GetCurrDataCounter
|
||||
*
|
||||
* @brief Returns the number of remaining data units in the current
|
||||
* DMAy Channelx transfer.
|
||||
*
|
||||
* @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be
|
||||
* 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel.
|
||||
*
|
||||
* @return DataNumber - The number of remaining data units in the current
|
||||
* DMAy Channelx transfer.
|
||||
*/
|
||||
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx)
|
||||
{
|
||||
return ((uint16_t)(DMAy_Channelx->CNTR));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DMA_GetFlagStatus
|
||||
*
|
||||
* @brief Checks whether the specified DMAy Channelx flag is set or not.
|
||||
*
|
||||
* @param DMAy_FLAG - specifies the flag to check.
|
||||
* DMA1_FLAG_GL1 - DMA1 Channel1 global flag.
|
||||
* DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag.
|
||||
* DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag.
|
||||
* DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag.
|
||||
* DMA1_FLAG_GL2 - DMA1 Channel2 global flag.
|
||||
* DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag.
|
||||
* DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag.
|
||||
* DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag.
|
||||
* DMA1_FLAG_GL3 - DMA1 Channel3 global flag.
|
||||
* DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag.
|
||||
* DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag.
|
||||
* DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag.
|
||||
* DMA1_FLAG_GL4 - DMA1 Channel4 global flag.
|
||||
* DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag.
|
||||
* DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag.
|
||||
* DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag.
|
||||
* DMA1_FLAG_GL5 - DMA1 Channel5 global flag.
|
||||
* DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag.
|
||||
* DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag.
|
||||
* DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag.
|
||||
* DMA1_FLAG_GL6 - DMA1 Channel6 global flag.
|
||||
* DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag.
|
||||
* DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag.
|
||||
* DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag.
|
||||
* DMA1_FLAG_GL7 - DMA1 Channel7 global flag.
|
||||
* DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag.
|
||||
* DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag.
|
||||
* DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag.
|
||||
* DMA2_FLAG_GL1 - DMA2 Channel1 global flag.
|
||||
* DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag.
|
||||
* DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag.
|
||||
* DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag.
|
||||
* DMA2_FLAG_GL2 - DMA2 Channel2 global flag.
|
||||
* DMA2_FLAG_TC2 - DMA2 Channel2 transfer complete flag.
|
||||
* DMA2_FLAG_HT2 - DMA2 Channel2 half transfer flag.
|
||||
* DMA2_FLAG_TE2 - DMA2 Channel2 transfer error flag.
|
||||
* DMA2_FLAG_GL3 - DMA2 Channel3 global flag.
|
||||
* DMA2_FLAG_TC3 - DMA2 Channel3 transfer complete flag.
|
||||
* DMA2_FLAG_HT3 - DMA2 Channel3 half transfer flag.
|
||||
* DMA2_FLAG_TE3 - DMA2 Channel3 transfer error flag.
|
||||
* DMA2_FLAG_GL4 - DMA2 Channel4 global flag.
|
||||
* DMA2_FLAG_TC4 - DMA2 Channel4 transfer complete flag.
|
||||
* DMA2_FLAG_HT4 - DMA2 Channel4 half transfer flag.
|
||||
* DMA2_FLAG_TE4 - DMA2 Channel4 transfer error flag.
|
||||
* DMA2_FLAG_GL5 - DMA2 Channel5 global flag.
|
||||
* DMA2_FLAG_TC5 - DMA2 Channel5 transfer complete flag.
|
||||
* DMA2_FLAG_HT5 - DMA2 Channel5 half transfer flag.
|
||||
* DMA2_FLAG_TE5 - DMA2 Channel5 transfer error flag.
|
||||
*
|
||||
* @return The new state of DMAy_FLAG (SET or RESET).
|
||||
*/
|
||||
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
if((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
|
||||
{
|
||||
tmpreg = DMA2->INTFR;
|
||||
}
|
||||
else
|
||||
{
|
||||
tmpreg = DMA1->INTFR;
|
||||
}
|
||||
|
||||
if((tmpreg & DMAy_FLAG) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DMA_ClearFlag
|
||||
*
|
||||
* @brief Clears the DMAy Channelx's pending flags.
|
||||
*
|
||||
* @param DMAy_FLAG - specifies the flag to check.
|
||||
* DMA1_FLAG_GL1 - DMA1 Channel1 global flag.
|
||||
* DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag.
|
||||
* DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag.
|
||||
* DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag.
|
||||
* DMA1_FLAG_GL2 - DMA1 Channel2 global flag.
|
||||
* DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag.
|
||||
* DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag.
|
||||
* DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag.
|
||||
* DMA1_FLAG_GL3 - DMA1 Channel3 global flag.
|
||||
* DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag.
|
||||
* DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag.
|
||||
* DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag.
|
||||
* DMA1_FLAG_GL4 - DMA1 Channel4 global flag.
|
||||
* DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag.
|
||||
* DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag.
|
||||
* DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag.
|
||||
* DMA1_FLAG_GL5 - DMA1 Channel5 global flag.
|
||||
* DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag.
|
||||
* DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag.
|
||||
* DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag.
|
||||
* DMA1_FLAG_GL6 - DMA1 Channel6 global flag.
|
||||
* DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag.
|
||||
* DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag.
|
||||
* DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag.
|
||||
* DMA1_FLAG_GL7 - DMA1 Channel7 global flag.
|
||||
* DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag.
|
||||
* DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag.
|
||||
* DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag.
|
||||
* DMA2_FLAG_GL1 - DMA2 Channel1 global flag.
|
||||
* DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag.
|
||||
* DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag.
|
||||
* DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag.
|
||||
* DMA2_FLAG_GL2 - DMA2 Channel2 global flag.
|
||||
* DMA2_FLAG_TC2 - DMA2 Channel2 transfer complete flag.
|
||||
* DMA2_FLAG_HT2 - DMA2 Channel2 half transfer flag.
|
||||
* DMA2_FLAG_TE2 - DMA2 Channel2 transfer error flag.
|
||||
* DMA2_FLAG_GL3 - DMA2 Channel3 global flag.
|
||||
* DMA2_FLAG_TC3 - DMA2 Channel3 transfer complete flag.
|
||||
* DMA2_FLAG_HT3 - DMA2 Channel3 half transfer flag.
|
||||
* DMA2_FLAG_TE3 - DMA2 Channel3 transfer error flag.
|
||||
* DMA2_FLAG_GL4 - DMA2 Channel4 global flag.
|
||||
* DMA2_FLAG_TC4 - DMA2 Channel4 transfer complete flag.
|
||||
* DMA2_FLAG_HT4 - DMA2 Channel4 half transfer flag.
|
||||
* DMA2_FLAG_TE4 - DMA2 Channel4 transfer error flag.
|
||||
* DMA2_FLAG_GL5 - DMA2 Channel5 global flag.
|
||||
* DMA2_FLAG_TC5 - DMA2 Channel5 transfer complete flag.
|
||||
* DMA2_FLAG_HT5 - DMA2 Channel5 half transfer flag.
|
||||
* DMA2_FLAG_TE5 - DMA2 Channel5 transfer error flag.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void DMA_ClearFlag(uint32_t DMAy_FLAG)
|
||||
{
|
||||
if((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET)
|
||||
{
|
||||
DMA2->INTFCR = DMAy_FLAG;
|
||||
}
|
||||
else
|
||||
{
|
||||
DMA1->INTFCR = DMAy_FLAG;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DMA_GetITStatus
|
||||
*
|
||||
* @brief Checks whether the specified DMAy Channelx interrupt has
|
||||
* occurred or not.
|
||||
*
|
||||
* @param DMAy_IT - specifies the DMAy interrupt source to check.
|
||||
* DMA1_IT_GL1 - DMA1 Channel1 global flag.
|
||||
* DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag.
|
||||
* DMA1_IT_HT1 - DMA1 Channel1 half transfer flag.
|
||||
* DMA1_IT_TE1 - DMA1 Channel1 transfer error flag.
|
||||
* DMA1_IT_GL2 - DMA1 Channel2 global flag.
|
||||
* DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag.
|
||||
* DMA1_IT_HT2 - DMA1 Channel2 half transfer flag.
|
||||
* DMA1_IT_TE2 - DMA1 Channel2 transfer error flag.
|
||||
* DMA1_IT_GL3 - DMA1 Channel3 global flag.
|
||||
* DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag.
|
||||
* DMA1_IT_HT3 - DMA1 Channel3 half transfer flag.
|
||||
* DMA1_IT_TE3 - DMA1 Channel3 transfer error flag.
|
||||
* DMA1_IT_GL4 - DMA1 Channel4 global flag.
|
||||
* DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag.
|
||||
* DMA1_IT_HT4 - DMA1 Channel4 half transfer flag.
|
||||
* DMA1_IT_TE4 - DMA1 Channel4 transfer error flag.
|
||||
* DMA1_IT_GL5 - DMA1 Channel5 global flag.
|
||||
* DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag.
|
||||
* DMA1_IT_HT5 - DMA1 Channel5 half transfer flag.
|
||||
* DMA1_IT_TE5 - DMA1 Channel5 transfer error flag.
|
||||
* DMA1_IT_GL6 - DMA1 Channel6 global flag.
|
||||
* DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag.
|
||||
* DMA1_IT_HT6 - DMA1 Channel6 half transfer flag.
|
||||
* DMA1_IT_TE6 - DMA1 Channel6 transfer error flag.
|
||||
* DMA1_IT_GL7 - DMA1 Channel7 global flag.
|
||||
* DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag.
|
||||
* DMA1_IT_HT7 - DMA1 Channel7 half transfer flag.
|
||||
* DMA1_IT_TE7 - DMA1 Channel7 transfer error flag.
|
||||
* DMA2_IT_GL1 - DMA2 Channel1 global flag.
|
||||
* DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag.
|
||||
* DMA2_IT_HT1 - DMA2 Channel1 half transfer flag.
|
||||
* DMA2_IT_TE1 - DMA2 Channel1 transfer error flag.
|
||||
* DMA2_IT_GL2 - DMA2 Channel2 global flag.
|
||||
* DMA2_IT_TC2 - DMA2 Channel2 transfer complete flag.
|
||||
* DMA2_IT_HT2 - DMA2 Channel2 half transfer flag.
|
||||
* DMA2_IT_TE2 - DMA2 Channel2 transfer error flag.
|
||||
* DMA2_IT_GL3 - DMA2 Channel3 global flag.
|
||||
* DMA2_IT_TC3 - DMA2 Channel3 transfer complete flag.
|
||||
* DMA2_IT_HT3 - DMA2 Channel3 half transfer flag.
|
||||
* DMA2_IT_TE3 - DMA2 Channel3 transfer error flag.
|
||||
* DMA2_IT_GL4 - DMA2 Channel4 global flag.
|
||||
* DMA2_IT_TC4 - DMA2 Channel4 transfer complete flag.
|
||||
* DMA2_IT_HT4 - DMA2 Channel4 half transfer flag.
|
||||
* DMA2_IT_TE4 - DMA2 Channel4 transfer error flag.
|
||||
* DMA2_IT_GL5 - DMA2 Channel5 global flag.
|
||||
* DMA2_IT_TC5 - DMA2 Channel5 transfer complete flag.
|
||||
* DMA2_IT_HT5 - DMA2 Channel5 half transfer flag.
|
||||
* DMA2_IT_TE5 - DMA2 Channel5 transfer error flag.
|
||||
*
|
||||
* @return The new state of DMAy_IT (SET or RESET).
|
||||
*/
|
||||
ITStatus DMA_GetITStatus(uint32_t DMAy_IT)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
if((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
|
||||
{
|
||||
tmpreg = DMA2->INTFR;
|
||||
}
|
||||
else
|
||||
{
|
||||
tmpreg = DMA1->INTFR;
|
||||
}
|
||||
|
||||
if((tmpreg & DMAy_IT) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn DMA_ClearITPendingBit
|
||||
*
|
||||
* @brief Clears the DMAy Channelx's interrupt pending bits.
|
||||
*
|
||||
* @param DMAy_IT - specifies the DMAy interrupt source to check.
|
||||
* DMA1_IT_GL1 - DMA1 Channel1 global flag.
|
||||
* DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag.
|
||||
* DMA1_IT_HT1 - DMA1 Channel1 half transfer flag.
|
||||
* DMA1_IT_TE1 - DMA1 Channel1 transfer error flag.
|
||||
* DMA1_IT_GL2 - DMA1 Channel2 global flag.
|
||||
* DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag.
|
||||
* DMA1_IT_HT2 - DMA1 Channel2 half transfer flag.
|
||||
* DMA1_IT_TE2 - DMA1 Channel2 transfer error flag.
|
||||
* DMA1_IT_GL3 - DMA1 Channel3 global flag.
|
||||
* DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag.
|
||||
* DMA1_IT_HT3 - DMA1 Channel3 half transfer flag.
|
||||
* DMA1_IT_TE3 - DMA1 Channel3 transfer error flag.
|
||||
* DMA1_IT_GL4 - DMA1 Channel4 global flag.
|
||||
* DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag.
|
||||
* DMA1_IT_HT4 - DMA1 Channel4 half transfer flag.
|
||||
* DMA1_IT_TE4 - DMA1 Channel4 transfer error flag.
|
||||
* DMA1_IT_GL5 - DMA1 Channel5 global flag.
|
||||
* DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag.
|
||||
* DMA1_IT_HT5 - DMA1 Channel5 half transfer flag.
|
||||
* DMA1_IT_TE5 - DMA1 Channel5 transfer error flag.
|
||||
* DMA1_IT_GL6 - DMA1 Channel6 global flag.
|
||||
* DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag.
|
||||
* DMA1_IT_HT6 - DMA1 Channel6 half transfer flag.
|
||||
* DMA1_IT_TE6 - DMA1 Channel6 transfer error flag.
|
||||
* DMA1_IT_GL7 - DMA1 Channel7 global flag.
|
||||
* DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag.
|
||||
* DMA1_IT_HT7 - DMA1 Channel7 half transfer flag.
|
||||
* DMA1_IT_TE7 - DMA1 Channel7 transfer error flag.
|
||||
* DMA2_IT_GL1 - DMA2 Channel1 global flag.
|
||||
* DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag.
|
||||
* DMA2_IT_HT1 - DMA2 Channel1 half transfer flag.
|
||||
* DMA2_IT_TE1 - DMA2 Channel1 transfer error flag.
|
||||
* DMA2_IT_GL2 - DMA2 Channel2 global flag.
|
||||
* DMA2_IT_TC2 - DMA2 Channel2 transfer complete flag.
|
||||
* DMA2_IT_HT2 - DMA2 Channel2 half transfer flag.
|
||||
* DMA2_IT_TE2 - DMA2 Channel2 transfer error flag.
|
||||
* DMA2_IT_GL3 - DMA2 Channel3 global flag.
|
||||
* DMA2_IT_TC3 - DMA2 Channel3 transfer complete flag.
|
||||
* DMA2_IT_HT3 - DMA2 Channel3 half transfer flag.
|
||||
* DMA2_IT_TE3 - DMA2 Channel3 transfer error flag.
|
||||
* DMA2_IT_GL4 - DMA2 Channel4 global flag.
|
||||
* DMA2_IT_TC4 - DMA2 Channel4 transfer complete flag.
|
||||
* DMA2_IT_HT4 - DMA2 Channel4 half transfer flag.
|
||||
* DMA2_IT_TE4 - DMA2 Channel4 transfer error flag.
|
||||
* DMA2_IT_GL5 - DMA2 Channel5 global flag.
|
||||
* DMA2_IT_TC5 - DMA2 Channel5 transfer complete flag.
|
||||
* DMA2_IT_HT5 - DMA2 Channel5 half transfer flag.
|
||||
* DMA2_IT_TE5 - DMA2 Channel5 transfer error flag.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void DMA_ClearITPendingBit(uint32_t DMAy_IT)
|
||||
{
|
||||
if((DMAy_IT & FLAG_Mask) != (uint32_t)RESET)
|
||||
{
|
||||
DMA2->INTFCR = DMAy_IT;
|
||||
}
|
||||
else
|
||||
{
|
||||
DMA1->INTFCR = DMAy_IT;
|
||||
}
|
||||
}
|
||||
218
mijia_haier_bridge/src/periph/ch32v10x_dma.h
Normal file
218
mijia_haier_bridge/src/periph/ch32v10x_dma.h
Normal file
@ -0,0 +1,218 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v10x_dma.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2020/04/30
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* DMA firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32V10x_DMA_H
|
||||
#define __CH32V10x_DMA_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "ch32v10x.h"
|
||||
|
||||
/* DMA Init structure definition */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */
|
||||
|
||||
uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */
|
||||
|
||||
uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination.
|
||||
This parameter can be a value of @ref DMA_data_transfer_direction */
|
||||
|
||||
uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel.
|
||||
The data unit is equal to the configuration set in DMA_PeripheralDataSize
|
||||
or DMA_MemoryDataSize members depending in the transfer direction. */
|
||||
|
||||
uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not.
|
||||
This parameter can be a value of @ref DMA_peripheral_incremented_mode */
|
||||
|
||||
uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not.
|
||||
This parameter can be a value of @ref DMA_memory_incremented_mode */
|
||||
|
||||
uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width.
|
||||
This parameter can be a value of @ref DMA_peripheral_data_size */
|
||||
|
||||
uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width.
|
||||
This parameter can be a value of @ref DMA_memory_data_size */
|
||||
|
||||
uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_circular_normal_mode.
|
||||
@note: The circular buffer mode cannot be used if the memory-to-memory
|
||||
data transfer is configured on the selected Channel */
|
||||
|
||||
uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx.
|
||||
This parameter can be a value of @ref DMA_priority_level */
|
||||
|
||||
uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer.
|
||||
This parameter can be a value of @ref DMA_memory_to_memory */
|
||||
} DMA_InitTypeDef;
|
||||
|
||||
/* DMA_data_transfer_direction */
|
||||
#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010)
|
||||
#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
|
||||
|
||||
/* DMA_peripheral_incremented_mode */
|
||||
#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040)
|
||||
#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
|
||||
|
||||
/* DMA_memory_incremented_mode */
|
||||
#define DMA_MemoryInc_Enable ((uint32_t)0x00000080)
|
||||
#define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
|
||||
|
||||
/* DMA_peripheral_data_size */
|
||||
#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
|
||||
#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100)
|
||||
#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200)
|
||||
|
||||
/* DMA_memory_data_size */
|
||||
#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
|
||||
#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400)
|
||||
#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800)
|
||||
|
||||
/* DMA_circular_normal_mode */
|
||||
#define DMA_Mode_Circular ((uint32_t)0x00000020)
|
||||
#define DMA_Mode_Normal ((uint32_t)0x00000000)
|
||||
|
||||
/* DMA_priority_level */
|
||||
#define DMA_Priority_VeryHigh ((uint32_t)0x00003000)
|
||||
#define DMA_Priority_High ((uint32_t)0x00002000)
|
||||
#define DMA_Priority_Medium ((uint32_t)0x00001000)
|
||||
#define DMA_Priority_Low ((uint32_t)0x00000000)
|
||||
|
||||
/* DMA_memory_to_memory */
|
||||
#define DMA_M2M_Enable ((uint32_t)0x00004000)
|
||||
#define DMA_M2M_Disable ((uint32_t)0x00000000)
|
||||
|
||||
/* DMA_interrupts_definition */
|
||||
#define DMA_IT_TC ((uint32_t)0x00000002)
|
||||
#define DMA_IT_HT ((uint32_t)0x00000004)
|
||||
#define DMA_IT_TE ((uint32_t)0x00000008)
|
||||
|
||||
#define DMA1_IT_GL1 ((uint32_t)0x00000001)
|
||||
#define DMA1_IT_TC1 ((uint32_t)0x00000002)
|
||||
#define DMA1_IT_HT1 ((uint32_t)0x00000004)
|
||||
#define DMA1_IT_TE1 ((uint32_t)0x00000008)
|
||||
#define DMA1_IT_GL2 ((uint32_t)0x00000010)
|
||||
#define DMA1_IT_TC2 ((uint32_t)0x00000020)
|
||||
#define DMA1_IT_HT2 ((uint32_t)0x00000040)
|
||||
#define DMA1_IT_TE2 ((uint32_t)0x00000080)
|
||||
#define DMA1_IT_GL3 ((uint32_t)0x00000100)
|
||||
#define DMA1_IT_TC3 ((uint32_t)0x00000200)
|
||||
#define DMA1_IT_HT3 ((uint32_t)0x00000400)
|
||||
#define DMA1_IT_TE3 ((uint32_t)0x00000800)
|
||||
#define DMA1_IT_GL4 ((uint32_t)0x00001000)
|
||||
#define DMA1_IT_TC4 ((uint32_t)0x00002000)
|
||||
#define DMA1_IT_HT4 ((uint32_t)0x00004000)
|
||||
#define DMA1_IT_TE4 ((uint32_t)0x00008000)
|
||||
#define DMA1_IT_GL5 ((uint32_t)0x00010000)
|
||||
#define DMA1_IT_TC5 ((uint32_t)0x00020000)
|
||||
#define DMA1_IT_HT5 ((uint32_t)0x00040000)
|
||||
#define DMA1_IT_TE5 ((uint32_t)0x00080000)
|
||||
#define DMA1_IT_GL6 ((uint32_t)0x00100000)
|
||||
#define DMA1_IT_TC6 ((uint32_t)0x00200000)
|
||||
#define DMA1_IT_HT6 ((uint32_t)0x00400000)
|
||||
#define DMA1_IT_TE6 ((uint32_t)0x00800000)
|
||||
#define DMA1_IT_GL7 ((uint32_t)0x01000000)
|
||||
#define DMA1_IT_TC7 ((uint32_t)0x02000000)
|
||||
#define DMA1_IT_HT7 ((uint32_t)0x04000000)
|
||||
#define DMA1_IT_TE7 ((uint32_t)0x08000000)
|
||||
|
||||
#define DMA2_IT_GL1 ((uint32_t)0x10000001)
|
||||
#define DMA2_IT_TC1 ((uint32_t)0x10000002)
|
||||
#define DMA2_IT_HT1 ((uint32_t)0x10000004)
|
||||
#define DMA2_IT_TE1 ((uint32_t)0x10000008)
|
||||
#define DMA2_IT_GL2 ((uint32_t)0x10000010)
|
||||
#define DMA2_IT_TC2 ((uint32_t)0x10000020)
|
||||
#define DMA2_IT_HT2 ((uint32_t)0x10000040)
|
||||
#define DMA2_IT_TE2 ((uint32_t)0x10000080)
|
||||
#define DMA2_IT_GL3 ((uint32_t)0x10000100)
|
||||
#define DMA2_IT_TC3 ((uint32_t)0x10000200)
|
||||
#define DMA2_IT_HT3 ((uint32_t)0x10000400)
|
||||
#define DMA2_IT_TE3 ((uint32_t)0x10000800)
|
||||
#define DMA2_IT_GL4 ((uint32_t)0x10001000)
|
||||
#define DMA2_IT_TC4 ((uint32_t)0x10002000)
|
||||
#define DMA2_IT_HT4 ((uint32_t)0x10004000)
|
||||
#define DMA2_IT_TE4 ((uint32_t)0x10008000)
|
||||
#define DMA2_IT_GL5 ((uint32_t)0x10010000)
|
||||
#define DMA2_IT_TC5 ((uint32_t)0x10020000)
|
||||
#define DMA2_IT_HT5 ((uint32_t)0x10040000)
|
||||
#define DMA2_IT_TE5 ((uint32_t)0x10080000)
|
||||
|
||||
/* DMA_flags_definition */
|
||||
#define DMA1_FLAG_GL1 ((uint32_t)0x00000001)
|
||||
#define DMA1_FLAG_TC1 ((uint32_t)0x00000002)
|
||||
#define DMA1_FLAG_HT1 ((uint32_t)0x00000004)
|
||||
#define DMA1_FLAG_TE1 ((uint32_t)0x00000008)
|
||||
#define DMA1_FLAG_GL2 ((uint32_t)0x00000010)
|
||||
#define DMA1_FLAG_TC2 ((uint32_t)0x00000020)
|
||||
#define DMA1_FLAG_HT2 ((uint32_t)0x00000040)
|
||||
#define DMA1_FLAG_TE2 ((uint32_t)0x00000080)
|
||||
#define DMA1_FLAG_GL3 ((uint32_t)0x00000100)
|
||||
#define DMA1_FLAG_TC3 ((uint32_t)0x00000200)
|
||||
#define DMA1_FLAG_HT3 ((uint32_t)0x00000400)
|
||||
#define DMA1_FLAG_TE3 ((uint32_t)0x00000800)
|
||||
#define DMA1_FLAG_GL4 ((uint32_t)0x00001000)
|
||||
#define DMA1_FLAG_TC4 ((uint32_t)0x00002000)
|
||||
#define DMA1_FLAG_HT4 ((uint32_t)0x00004000)
|
||||
#define DMA1_FLAG_TE4 ((uint32_t)0x00008000)
|
||||
#define DMA1_FLAG_GL5 ((uint32_t)0x00010000)
|
||||
#define DMA1_FLAG_TC5 ((uint32_t)0x00020000)
|
||||
#define DMA1_FLAG_HT5 ((uint32_t)0x00040000)
|
||||
#define DMA1_FLAG_TE5 ((uint32_t)0x00080000)
|
||||
#define DMA1_FLAG_GL6 ((uint32_t)0x00100000)
|
||||
#define DMA1_FLAG_TC6 ((uint32_t)0x00200000)
|
||||
#define DMA1_FLAG_HT6 ((uint32_t)0x00400000)
|
||||
#define DMA1_FLAG_TE6 ((uint32_t)0x00800000)
|
||||
#define DMA1_FLAG_GL7 ((uint32_t)0x01000000)
|
||||
#define DMA1_FLAG_TC7 ((uint32_t)0x02000000)
|
||||
#define DMA1_FLAG_HT7 ((uint32_t)0x04000000)
|
||||
#define DMA1_FLAG_TE7 ((uint32_t)0x08000000)
|
||||
|
||||
#define DMA2_FLAG_GL1 ((uint32_t)0x10000001)
|
||||
#define DMA2_FLAG_TC1 ((uint32_t)0x10000002)
|
||||
#define DMA2_FLAG_HT1 ((uint32_t)0x10000004)
|
||||
#define DMA2_FLAG_TE1 ((uint32_t)0x10000008)
|
||||
#define DMA2_FLAG_GL2 ((uint32_t)0x10000010)
|
||||
#define DMA2_FLAG_TC2 ((uint32_t)0x10000020)
|
||||
#define DMA2_FLAG_HT2 ((uint32_t)0x10000040)
|
||||
#define DMA2_FLAG_TE2 ((uint32_t)0x10000080)
|
||||
#define DMA2_FLAG_GL3 ((uint32_t)0x10000100)
|
||||
#define DMA2_FLAG_TC3 ((uint32_t)0x10000200)
|
||||
#define DMA2_FLAG_HT3 ((uint32_t)0x10000400)
|
||||
#define DMA2_FLAG_TE3 ((uint32_t)0x10000800)
|
||||
#define DMA2_FLAG_GL4 ((uint32_t)0x10001000)
|
||||
#define DMA2_FLAG_TC4 ((uint32_t)0x10002000)
|
||||
#define DMA2_FLAG_HT4 ((uint32_t)0x10004000)
|
||||
#define DMA2_FLAG_TE4 ((uint32_t)0x10008000)
|
||||
#define DMA2_FLAG_GL5 ((uint32_t)0x10010000)
|
||||
#define DMA2_FLAG_TC5 ((uint32_t)0x10020000)
|
||||
#define DMA2_FLAG_HT5 ((uint32_t)0x10040000)
|
||||
#define DMA2_FLAG_TE5 ((uint32_t)0x10080000)
|
||||
|
||||
void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx);
|
||||
void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct);
|
||||
void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct);
|
||||
void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState);
|
||||
void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);
|
||||
void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber);
|
||||
uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx);
|
||||
FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG);
|
||||
void DMA_ClearFlag(uint32_t DMAy_FLAG);
|
||||
ITStatus DMA_GetITStatus(uint32_t DMAy_IT);
|
||||
void DMA_ClearITPendingBit(uint32_t DMAy_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__CH32V10x_DMA_H */
|
||||
578
mijia_haier_bridge/src/periph/ch32v10x_gpio.c
Normal file
578
mijia_haier_bridge/src/periph/ch32v10x_gpio.c
Normal file
@ -0,0 +1,578 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v10x_gpio.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.1
|
||||
* Date : 2025/01/02
|
||||
* Description : This file provides all the GPIO firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32v10x_gpio.h"
|
||||
#include "ch32v10x_rcc.h"
|
||||
|
||||
/* MASK */
|
||||
#define ECR_PORTPINCONFIG_MASK ((uint16_t)0xFF80)
|
||||
#define LSB_MASK ((uint16_t)0xFFFF)
|
||||
#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000)
|
||||
#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF)
|
||||
#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000)
|
||||
#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000)
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_DeInit
|
||||
*
|
||||
* @brief Deinitializes the GPIOx peripheral registers to their default
|
||||
* reset values.
|
||||
*
|
||||
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_DeInit(GPIO_TypeDef *GPIOx)
|
||||
{
|
||||
if(GPIOx == GPIOA)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE);
|
||||
}
|
||||
else if(GPIOx == GPIOB)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE);
|
||||
}
|
||||
else if(GPIOx == GPIOC)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE);
|
||||
}
|
||||
else if(GPIOx == GPIOD)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE);
|
||||
}
|
||||
else if(GPIOx == GPIOE)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE);
|
||||
}
|
||||
else if(GPIOx == GPIOF)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE);
|
||||
}
|
||||
else
|
||||
{
|
||||
if(GPIOx == GPIOG)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_AFIODeInit
|
||||
*
|
||||
* @brief Deinitializes the Alternate Functions (remap, event control
|
||||
* and EXTI configuration) registers to their default reset values.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_AFIODeInit(void)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_Init
|
||||
*
|
||||
* @brief GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||
*
|
||||
* @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that
|
||||
* contains the configuration information for the specified GPIO peripheral.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct)
|
||||
{
|
||||
uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00;
|
||||
uint32_t tmpreg = 0x00, pinmask = 0x00;
|
||||
|
||||
currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F);
|
||||
|
||||
if((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00)
|
||||
{
|
||||
currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed;
|
||||
}
|
||||
|
||||
if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00)
|
||||
{
|
||||
tmpreg = GPIOx->CFGLR;
|
||||
|
||||
for(pinpos = 0x00; pinpos < 0x08; pinpos++)
|
||||
{
|
||||
pos = ((uint32_t)0x01) << pinpos;
|
||||
currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
|
||||
|
||||
if(currentpin == pos)
|
||||
{
|
||||
pos = pinpos << 2;
|
||||
pinmask = ((uint32_t)0x0F) << pos;
|
||||
tmpreg &= ~pinmask;
|
||||
tmpreg |= (currentmode << pos);
|
||||
|
||||
if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
|
||||
{
|
||||
GPIOx->BCR = (((uint32_t)0x01) << pinpos);
|
||||
}
|
||||
else
|
||||
{
|
||||
if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
|
||||
{
|
||||
GPIOx->BSHR = (((uint32_t)0x01) << pinpos);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
GPIOx->CFGLR = tmpreg;
|
||||
}
|
||||
|
||||
if(GPIO_InitStruct->GPIO_Pin > 0x00FF)
|
||||
{
|
||||
tmpreg = GPIOx->CFGHR;
|
||||
|
||||
for(pinpos = 0x00; pinpos < 0x08; pinpos++)
|
||||
{
|
||||
pos = (((uint32_t)0x01) << (pinpos + 0x08));
|
||||
currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos);
|
||||
|
||||
if(currentpin == pos)
|
||||
{
|
||||
pos = pinpos << 2;
|
||||
pinmask = ((uint32_t)0x0F) << pos;
|
||||
tmpreg &= ~pinmask;
|
||||
tmpreg |= (currentmode << pos);
|
||||
|
||||
if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD)
|
||||
{
|
||||
GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x08));
|
||||
}
|
||||
|
||||
if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU)
|
||||
{
|
||||
GPIOx->BSHR = (((uint32_t)0x01) << (pinpos + 0x08));
|
||||
}
|
||||
}
|
||||
}
|
||||
GPIOx->CFGHR = tmpreg;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_StructInit
|
||||
*
|
||||
* @brief Fills each GPIO_InitStruct member with its default
|
||||
*
|
||||
* @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure
|
||||
* which will be initialized.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct)
|
||||
{
|
||||
GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
|
||||
GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
|
||||
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_ReadInputDataBit
|
||||
*
|
||||
* @brief GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||
*
|
||||
* @param GPIO_Pin - specifies the port bit to read.
|
||||
* This parameter can be GPIO_Pin_x where x can be (0..15).
|
||||
*
|
||||
* @return The input port pin value.
|
||||
*/
|
||||
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint8_t bitstatus = 0x00;
|
||||
|
||||
if((GPIOx->INDR & GPIO_Pin) != (uint32_t)Bit_RESET)
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_RESET;
|
||||
}
|
||||
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_ReadInputData
|
||||
*
|
||||
* @brief Reads the specified GPIO input data port.
|
||||
*
|
||||
* @param GPIOx: where x can be (A..G) to select the GPIO peripheral.
|
||||
*
|
||||
* @return The input port pin value.
|
||||
*/
|
||||
uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx)
|
||||
{
|
||||
return ((uint16_t)GPIOx->INDR);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_ReadOutputDataBit
|
||||
*
|
||||
* @brief Reads the specified output data port bit.
|
||||
*
|
||||
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||
* GPIO_Pin - specifies the port bit to read.
|
||||
* This parameter can be GPIO_Pin_x where x can be (0..15).
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint8_t bitstatus = 0x00;
|
||||
|
||||
if((GPIOx->OUTDR & GPIO_Pin) != (uint32_t)Bit_RESET)
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = (uint8_t)Bit_RESET;
|
||||
}
|
||||
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_ReadOutputData
|
||||
*
|
||||
* @brief Reads the specified GPIO output data port.
|
||||
*
|
||||
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||
*
|
||||
* @return GPIO output port pin value.
|
||||
*/
|
||||
uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx)
|
||||
{
|
||||
return ((uint16_t)GPIOx->OUTDR);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_SetBits
|
||||
*
|
||||
* @brief Sets the selected data port bits.
|
||||
*
|
||||
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||
* GPIO_Pin - specifies the port bits to be written.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
GPIOx->BSHR = GPIO_Pin;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_ResetBits
|
||||
*
|
||||
* @brief Clears the selected data port bits.
|
||||
*
|
||||
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||
* GPIO_Pin - specifies the port bits to be written.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
GPIOx->BCR = GPIO_Pin;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_WriteBit
|
||||
*
|
||||
* @brief Sets or clears the selected data port bit.
|
||||
*
|
||||
* @param GPIO_Pin - specifies the port bit to be written.
|
||||
* This parameter can be one of GPIO_Pin_x where x can be (0..15).
|
||||
* BitVal - specifies the value to be written to the selected bit.
|
||||
* Bit_RESET - to clear the port pin.
|
||||
* Bit_SET - to set the port pin.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
|
||||
{
|
||||
if(BitVal != Bit_RESET)
|
||||
{
|
||||
GPIOx->BSHR = GPIO_Pin;
|
||||
}
|
||||
else
|
||||
{
|
||||
GPIOx->BCR = GPIO_Pin;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_Write
|
||||
*
|
||||
* @brief Writes data to the specified GPIO data port.
|
||||
*
|
||||
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||
* PortVal - specifies the value to be written to the port output data register.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal)
|
||||
{
|
||||
GPIOx->OUTDR = PortVal;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_PinLockConfig
|
||||
*
|
||||
* @brief Locks GPIO Pins configuration registers.
|
||||
*
|
||||
* @param GPIOx - where x can be (A..G) to select the GPIO peripheral.
|
||||
* GPIO_Pin - specifies the port bit to be written.
|
||||
* This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin)
|
||||
{
|
||||
uint32_t tmp = 0x00010000;
|
||||
|
||||
tmp |= GPIO_Pin;
|
||||
GPIOx->LCKR = tmp;
|
||||
GPIOx->LCKR = GPIO_Pin;
|
||||
GPIOx->LCKR = tmp;
|
||||
tmp = GPIOx->LCKR;
|
||||
tmp = GPIOx->LCKR;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_EventOutputConfig
|
||||
*
|
||||
* @brief Selects the GPIO pin used as Event output.
|
||||
*
|
||||
* @param GPIO_PortSource - selects the GPIO port to be used as source
|
||||
* for Event output.
|
||||
* This parameter can be GPIO_PortSourceGPIOx where x can be (A..E).
|
||||
* GPIO_PinSource - specifies the pin for the Event output.
|
||||
* This parameter can be GPIO_PinSourcex where x can be (0..15).
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
|
||||
{
|
||||
uint32_t tmpreg = 0x00;
|
||||
|
||||
tmpreg = AFIO->ECR;
|
||||
tmpreg &= ECR_PORTPINCONFIG_MASK;
|
||||
tmpreg |= (uint32_t)GPIO_PortSource << 0x04;
|
||||
tmpreg |= GPIO_PinSource;
|
||||
AFIO->ECR = tmpreg;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_EventOutputCmd
|
||||
*
|
||||
* @brief Enables or disables the Event Output.
|
||||
*
|
||||
* @param NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_EventOutputCmd(FunctionalState NewState)
|
||||
{
|
||||
if(NewState)
|
||||
{
|
||||
AFIO->ECR |= (1 << 7);
|
||||
}
|
||||
else
|
||||
{
|
||||
AFIO->ECR &= ~(1 << 7);
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_PinRemapConfig
|
||||
*
|
||||
* @brief Changes the mapping of the specified pin.
|
||||
*
|
||||
* @param GPIO_Remap - selects the pin to remap.
|
||||
* GPIO_Remap_SPI1 - SPI1 Alternate Function mapping
|
||||
* GPIO_Remap_I2C1 - I2C1 Alternate Function mapping
|
||||
* GPIO_Remap_USART1 - USART1 Alternate Function mapping
|
||||
* GPIO_Remap_USART2 - USART2 Alternate Function mapping
|
||||
* GPIO_PartialRemap_USART3 - USART3 Partial Alternate Function mapping
|
||||
* GPIO_FullRemap_USART3 - USART3 Full Alternate Function mapping
|
||||
* GPIO_PartialRemap_TIM1 - TIM1 Partial Alternate Function mapping
|
||||
* GPIO_FullRemap_TIM1 - TIM1 Full Alternate Function mapping
|
||||
* GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping
|
||||
* GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping
|
||||
* GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping
|
||||
* GPIO_PartialRemap_TIM3 - TIM3 Partial Alternate Function mapping
|
||||
* GPIO_FullRemap_TIM3 - TIM3 Full Alternate Function mapping
|
||||
* GPIO_Remap_TIM4 - TIM4 Alternate Function mapping
|
||||
* GPIO_Remap1_CAN1 - CAN1 Alternate Function mapping
|
||||
* GPIO_Remap2_CAN1 - CAN1 Alternate Function mapping
|
||||
* GPIO_Remap_PD0PD1 - PD0 and PD1 Alternate Function mapping
|
||||
* GPIO_Remap_ADC1_ETRGINJ - ADC1 External Trigger Injected Conversion remapping
|
||||
* GPIO_Remap_ADC1_ETRGREG - ADC1 External Trigger Regular Conversion remapping
|
||||
* GPIO_Remap_ADC2_ETRGINJ - ADC2 External Trigger Injected Conversion remapping
|
||||
* GPIO_Remap_ADC2_ETRGREG - ADC2 External Trigger Regular Conversion remapping
|
||||
* GPIO_Remap_ETH - Ethernet remapping
|
||||
* GPIO_Remap_CAN2 - CAN2 remapping
|
||||
* GPIO_Remap_MII_RMII_SEL - MII or RMII selection
|
||||
* GPIO_Remap_SWJ_Disable - Full SWJ Disabled
|
||||
* GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame) connected
|
||||
* to TIM2 Internal Trigger 1 for calibration
|
||||
* GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame)
|
||||
* GPIO_Remap_TIM8 - TIM8 Alternate Function mapping
|
||||
* GPIO_PartialRemap_TIM9 - TIM9 Partial Alternate Function mapping
|
||||
* GPIO_FullRemap_TIM9 - TIM9 Full Alternate Function mapping
|
||||
* GPIO_PartialRemap_TIM10 - TIM10 Partial Alternate Function mapping
|
||||
* GPIO_FullRemap_TIM10 - TIM10 Full Alternate Function mapping
|
||||
* GPIO_Remap_FSMC_NADV - FSMC_NADV Alternate Function mapping
|
||||
* GPIO_PartialRemap_USART4 - USART4 Partial Alternate Function mapping
|
||||
* GPIO_FullRemap_USART4 - USART4 Full Alternate Function mapping
|
||||
* GPIO_PartialRemap_USART5 - USART5 Partial Alternate Function mapping
|
||||
* GPIO_FullRemap_USART5 - USART5 Full Alternate Function mapping
|
||||
* GPIO_PartialRemap_USART6 - USART6 Partial Alternate Function mapping
|
||||
* GPIO_FullRemap_USART6 - USART6 Full Alternate Function mapping
|
||||
* GPIO_PartialRemap_USART7 - USART7 Partial Alternate Function mapping
|
||||
* GPIO_FullRemap_USART7 - USART7 Full Alternate Function mapping
|
||||
* GPIO_PartialRemap_USART8 - USART8 Partial Alternate Function mapping
|
||||
* GPIO_FullRemap_USART8 - USART8 Full Alternate Function mapping
|
||||
* GPIO_Remap_USART1_HighBit - USART1 Alternate Function mapping high bit
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState)
|
||||
{
|
||||
uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00;
|
||||
|
||||
if((GPIO_Remap & 0x80000000) == 0x80000000)
|
||||
{
|
||||
tmpreg = AFIO->PCFR2;
|
||||
}
|
||||
else
|
||||
{
|
||||
tmpreg = AFIO->PCFR1;
|
||||
}
|
||||
|
||||
tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10;
|
||||
tmp = GPIO_Remap & LSB_MASK;
|
||||
|
||||
if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK))
|
||||
{
|
||||
tmpreg &= DBGAFR_SWJCFG_MASK;
|
||||
AFIO->PCFR1 &= DBGAFR_SWJCFG_MASK;
|
||||
}
|
||||
else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK)
|
||||
{
|
||||
tmp1 = ((uint32_t)0x03) << tmpmask;
|
||||
tmpreg &= ~tmp1;
|
||||
tmpreg |= ~DBGAFR_SWJCFG_MASK;
|
||||
}
|
||||
else
|
||||
{
|
||||
tmpreg &= ~(tmp << (((GPIO_Remap & 0x7FFFFFFF)>> 0x15) * 0x10));
|
||||
tmpreg |= ~DBGAFR_SWJCFG_MASK;
|
||||
}
|
||||
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
tmpreg |= (tmp << (((GPIO_Remap & 0x7FFFFFFF)>> 0x15) * 0x10));
|
||||
}
|
||||
|
||||
if((GPIO_Remap & 0x80000000) == 0x80000000)
|
||||
{
|
||||
AFIO->PCFR2 = tmpreg;
|
||||
}
|
||||
else
|
||||
{
|
||||
AFIO->PCFR1 = tmpreg;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_EXTILineConfig
|
||||
*
|
||||
* @brief Selects the GPIO pin used as EXTI Line.
|
||||
*
|
||||
* @param GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines.
|
||||
* This parameter can be GPIO_PortSourceGPIOx where x can be (A..G).
|
||||
* GPIO_PinSource - specifies the EXTI line to be configured.
|
||||
* This parameter can be GPIO_PinSourcex where x can be (0..15).
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource)
|
||||
{
|
||||
uint32_t tmp = 0x00;
|
||||
|
||||
tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03));
|
||||
AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp;
|
||||
AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)));
|
||||
}
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
* @fn GPIO_IPD_Unused
|
||||
*
|
||||
* @brief Configure unused GPIO as input pull-up.
|
||||
*
|
||||
* @param none
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void GPIO_IPD_Unused(void)
|
||||
{
|
||||
GPIO_InitTypeDef GPIO_InitStructure = {0};
|
||||
uint32_t chip = 0;
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD, ENABLE);
|
||||
chip = *( uint32_t * )0x1FFFF884 & (~0x000000F0);
|
||||
switch(chip)
|
||||
{
|
||||
case 0x25004102: //CH32V103C8T6
|
||||
{
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\
|
||||
|GPIO_Pin_2|GPIO_Pin_3\
|
||||
|GPIO_Pin_4|GPIO_Pin_5\
|
||||
|GPIO_Pin_6|GPIO_Pin_7\
|
||||
|GPIO_Pin_8|GPIO_Pin_9\
|
||||
|GPIO_Pin_10|GPIO_Pin_11|GPIO_Pin_12;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOC, &GPIO_InitStructure);
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOD, &GPIO_InitStructure);
|
||||
break;
|
||||
}
|
||||
default:
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
|
||||
|
||||
161
mijia_haier_bridge/src/periph/ch32v10x_gpio.h
Normal file
161
mijia_haier_bridge/src/periph/ch32v10x_gpio.h
Normal file
@ -0,0 +1,161 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v10x_gpio.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.1
|
||||
* Date : 2025/01/02
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* GPIO firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32V10x_GPIO_H
|
||||
#define __CH32V10x_GPIO_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "ch32v10x.h"
|
||||
|
||||
/* Output Maximum frequency selection */
|
||||
typedef enum
|
||||
{
|
||||
GPIO_Speed_10MHz = 1,
|
||||
GPIO_Speed_2MHz,
|
||||
GPIO_Speed_50MHz
|
||||
} GPIOSpeed_TypeDef;
|
||||
|
||||
/* Configuration Mode enumeration */
|
||||
typedef enum
|
||||
{
|
||||
GPIO_Mode_AIN = 0x0,
|
||||
GPIO_Mode_IN_FLOATING = 0x04,
|
||||
GPIO_Mode_IPD = 0x28,
|
||||
GPIO_Mode_IPU = 0x48,
|
||||
GPIO_Mode_Out_OD = 0x14,
|
||||
GPIO_Mode_Out_PP = 0x10,
|
||||
GPIO_Mode_AF_OD = 0x1C,
|
||||
GPIO_Mode_AF_PP = 0x18
|
||||
} GPIOMode_TypeDef;
|
||||
|
||||
/* GPIO Init structure definition */
|
||||
typedef struct
|
||||
{
|
||||
uint16_t GPIO_Pin; /* Specifies the GPIO pins to be configured.
|
||||
This parameter can be any value of @ref GPIO_pins_define */
|
||||
|
||||
GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins.
|
||||
This parameter can be a value of @ref GPIOSpeed_TypeDef */
|
||||
|
||||
GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins.
|
||||
This parameter can be a value of @ref GPIOMode_TypeDef */
|
||||
} GPIO_InitTypeDef;
|
||||
|
||||
/* Bit_SET and Bit_RESET enumeration */
|
||||
typedef enum
|
||||
{
|
||||
Bit_RESET = 0,
|
||||
Bit_SET
|
||||
} BitAction;
|
||||
|
||||
/* GPIO_pins_define */
|
||||
#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */
|
||||
#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */
|
||||
#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */
|
||||
#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */
|
||||
#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */
|
||||
#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */
|
||||
#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */
|
||||
#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */
|
||||
#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */
|
||||
#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */
|
||||
#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */
|
||||
#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */
|
||||
#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */
|
||||
#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */
|
||||
#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */
|
||||
#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */
|
||||
#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */
|
||||
|
||||
/* GPIO_Remap_define */
|
||||
#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */
|
||||
#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /* I2C1 Alternate Function mapping */
|
||||
#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /* USART1 Alternate Function mapping */
|
||||
#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /* USART2 Alternate Function mapping */
|
||||
#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /* USART3 Partial Alternate Function mapping */
|
||||
#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /* USART3 Full Alternate Function mapping */
|
||||
#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /* TIM1 Partial Alternate Function mapping */
|
||||
#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */
|
||||
#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */
|
||||
#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */
|
||||
#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */
|
||||
#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /* TIM3 Partial Alternate Function mapping */
|
||||
#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /* TIM3 Full Alternate Function mapping */
|
||||
#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /* TIM4 Alternate Function mapping */
|
||||
#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /* CAN1 Alternate Function mapping */
|
||||
#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /* CAN1 Alternate Function mapping */
|
||||
#define GPIO_Remap_PD0PD1 ((uint32_t)0x00008000) /* PD0 and PD1 Alternate Function mapping */
|
||||
#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */
|
||||
#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */
|
||||
#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* Full SWJ Disabled */
|
||||
#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /* Ethernet PTP output or USB OTG SOF (Start of Frame) connected \
|
||||
to TIM2 Internal Trigger 1 for calibration \
|
||||
(only for Connectivity line devices) */
|
||||
#define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /* TIM1 DMA requests mapping (only for Value line devices) */
|
||||
#define GPIO_Remap_TIM67_DAC_DMA ((uint32_t)0x80000800) /* TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */
|
||||
#define GPIO_Remap_MISC ((uint32_t)0x80002000) /* Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, \
|
||||
only for High density Value line devices) */
|
||||
#define GPIO_Remap_PD01 GPIO_Remap_PD0PD1
|
||||
|
||||
/* GPIO_Port_Sources */
|
||||
#define GPIO_PortSourceGPIOA ((uint8_t)0x00)
|
||||
#define GPIO_PortSourceGPIOB ((uint8_t)0x01)
|
||||
#define GPIO_PortSourceGPIOC ((uint8_t)0x02)
|
||||
#define GPIO_PortSourceGPIOD ((uint8_t)0x03)
|
||||
#define GPIO_PortSourceGPIOE ((uint8_t)0x04)
|
||||
#define GPIO_PortSourceGPIOF ((uint8_t)0x05)
|
||||
#define GPIO_PortSourceGPIOG ((uint8_t)0x06)
|
||||
|
||||
/* GPIO_Pin_sources */
|
||||
#define GPIO_PinSource0 ((uint8_t)0x00)
|
||||
#define GPIO_PinSource1 ((uint8_t)0x01)
|
||||
#define GPIO_PinSource2 ((uint8_t)0x02)
|
||||
#define GPIO_PinSource3 ((uint8_t)0x03)
|
||||
#define GPIO_PinSource4 ((uint8_t)0x04)
|
||||
#define GPIO_PinSource5 ((uint8_t)0x05)
|
||||
#define GPIO_PinSource6 ((uint8_t)0x06)
|
||||
#define GPIO_PinSource7 ((uint8_t)0x07)
|
||||
#define GPIO_PinSource8 ((uint8_t)0x08)
|
||||
#define GPIO_PinSource9 ((uint8_t)0x09)
|
||||
#define GPIO_PinSource10 ((uint8_t)0x0A)
|
||||
#define GPIO_PinSource11 ((uint8_t)0x0B)
|
||||
#define GPIO_PinSource12 ((uint8_t)0x0C)
|
||||
#define GPIO_PinSource13 ((uint8_t)0x0D)
|
||||
#define GPIO_PinSource14 ((uint8_t)0x0E)
|
||||
#define GPIO_PinSource15 ((uint8_t)0x0F)
|
||||
|
||||
void GPIO_DeInit(GPIO_TypeDef *GPIOx);
|
||||
void GPIO_AFIODeInit(void);
|
||||
void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct);
|
||||
void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct);
|
||||
uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
|
||||
uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx);
|
||||
uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
|
||||
uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx);
|
||||
void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
|
||||
void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
|
||||
void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
|
||||
void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal);
|
||||
void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin);
|
||||
void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
|
||||
void GPIO_EventOutputCmd(FunctionalState NewState);
|
||||
void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState);
|
||||
void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CH32V10x_GPIO_H */
|
||||
87
mijia_haier_bridge/src/periph/ch32v10x_misc.c
Normal file
87
mijia_haier_bridge/src/periph/ch32v10x_misc.c
Normal file
@ -0,0 +1,87 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v10x_misc.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/01/05
|
||||
* Description : This file provides all the miscellaneous firmware functions .
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32v10x_misc.h"
|
||||
|
||||
__IO uint32_t NVIC_Priority_Group = 0;
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_PriorityGroupConfig
|
||||
*
|
||||
* @brief Configures the priority grouping - pre-emption priority and subpriority.
|
||||
*
|
||||
* @param NVIC_PriorityGroup - specifies the priority grouping bits length.
|
||||
* NVIC_PriorityGroup_0 - 0 bits for pre-emption priority
|
||||
* 4 bits for subpriority
|
||||
* NVIC_PriorityGroup_1 - 1 bits for pre-emption priority
|
||||
* 3 bits for subpriority
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
|
||||
{
|
||||
#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN)
|
||||
NVIC_INTNestCfg(DISABLE);
|
||||
#else
|
||||
NVIC_INTNestCfg(ENABLE);
|
||||
#endif
|
||||
|
||||
NVIC_Priority_Group = NVIC_PriorityGroup;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn NVIC_Init
|
||||
*
|
||||
* @brief Initializes the NVIC peripheral according to the specified parameters in
|
||||
* the NVIC_InitStruct.
|
||||
*
|
||||
* @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the
|
||||
* configuration information for the specified NVIC peripheral.
|
||||
* interrupt nesting enable(PFIC->CFGR bit1 = 0)
|
||||
* NVIC_IRQChannelPreemptionPriority - range from 0 to 1.
|
||||
* NVIC_IRQChannelSubPriority - range from 0 to 7.
|
||||
*
|
||||
* interrupt nesting disable(PFIC->CFGR bit1 = 1)
|
||||
* NVIC_IRQChannelPreemptionPriority - range is 0.
|
||||
* NVIC_IRQChannelSubPriority - range from 0 to 0xF.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct)
|
||||
{
|
||||
#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN)
|
||||
if(NVIC_Priority_Group == NVIC_PriorityGroup_0)
|
||||
{
|
||||
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4);
|
||||
}
|
||||
#else
|
||||
if(NVIC_Priority_Group == NVIC_PriorityGroup_1)
|
||||
{
|
||||
if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1)
|
||||
{
|
||||
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4));
|
||||
}
|
||||
else if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 0)
|
||||
{
|
||||
NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4));
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
|
||||
{
|
||||
NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel);
|
||||
}
|
||||
else
|
||||
{
|
||||
NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel);
|
||||
}
|
||||
}
|
||||
70
mijia_haier_bridge/src/periph/ch32v10x_misc.h
Normal file
70
mijia_haier_bridge/src/periph/ch32v10x_misc.h
Normal file
@ -0,0 +1,70 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v10x_misc.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/01/05
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* miscellaneous firmware library functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32V10X_MISC_H
|
||||
#define __CH32V10X_MISC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "ch32v10x.h"
|
||||
|
||||
/* CSR_INTSYSCR_INEST_definition */
|
||||
#define INTSYSCR_INEST_NoEN 0x00 /* interrupt nesting disable(PFIC->CFGR bit1 = 1) */
|
||||
#define INTSYSCR_INEST_EN 0x01 /* interrupt nesting enable(PFIC->CFGR bit1 = 0) */
|
||||
|
||||
/* Check the configuration of PFIC->CFGR
|
||||
* interrupt nesting enable(PFIC->CFGR bit1 = 0)
|
||||
* priority - bit[7] - Preemption Priority
|
||||
* bit[6:4] - Sub priority
|
||||
* bit[3:0] - Reserve
|
||||
* interrupt nesting disable(PFIC->CFGR bit1 = 1)
|
||||
* priority - bit[7:4] - Sub priority
|
||||
* bit[3:0] - Reserve
|
||||
*/
|
||||
|
||||
#ifndef INTSYSCR_INEST
|
||||
#define INTSYSCR_INEST INTSYSCR_INEST_EN
|
||||
#endif
|
||||
|
||||
/* NVIC Init Structure definition
|
||||
* interrupt nesting enable(PFIC->CFGR bit1 = 0)
|
||||
* NVIC_IRQChannelPreemptionPriority - range from 0 to 1.
|
||||
* NVIC_IRQChannelSubPriority - range from 0 to 7.
|
||||
*
|
||||
* interrupt nesting disable(PFIC->CFGR bit1 = 1)
|
||||
* NVIC_IRQChannelPreemptionPriority - range is 0.
|
||||
* NVIC_IRQChannelSubPriority - range from 0 to 0xF.
|
||||
*
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint8_t NVIC_IRQChannel;
|
||||
uint8_t NVIC_IRQChannelPreemptionPriority;
|
||||
uint8_t NVIC_IRQChannelSubPriority;
|
||||
FunctionalState NVIC_IRQChannelCmd;
|
||||
} NVIC_InitTypeDef;
|
||||
|
||||
/* Preemption_Priority_Group */
|
||||
#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN)
|
||||
#define NVIC_PriorityGroup_0 ((uint32_t)0x00) /* interrupt nesting disable(PFIC->CFGR bit1 = 1) */
|
||||
#else
|
||||
#define NVIC_PriorityGroup_1 ((uint32_t)0x01) /* interrupt nesting enable(PFIC->CFGR bit1 = 0) */
|
||||
#endif
|
||||
|
||||
|
||||
void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
|
||||
void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
|
||||
|
||||
#endif /* __CH32V10x_MISC_H */
|
||||
|
||||
950
mijia_haier_bridge/src/periph/ch32v10x_rcc.c
Normal file
950
mijia_haier_bridge/src/periph/ch32v10x_rcc.c
Normal file
@ -0,0 +1,950 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v10x_rcc.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2020/04/30
|
||||
* Description : This file provides all the RCC firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32v10x_rcc.h"
|
||||
|
||||
/* RCC registers bit address in the alias region */
|
||||
#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
|
||||
|
||||
/* BDCTLR Register */
|
||||
#define BDCTLR_OFFSET (RCC_OFFSET + 0x20)
|
||||
|
||||
/* RCC registers bit mask */
|
||||
|
||||
/* CTLR register bit mask */
|
||||
#define CTLR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF)
|
||||
#define CTLR_HSEBYP_Set ((uint32_t)0x00040000)
|
||||
#define CTLR_HSEON_Reset ((uint32_t)0xFFFEFFFF)
|
||||
#define CTLR_HSEON_Set ((uint32_t)0x00010000)
|
||||
#define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07)
|
||||
|
||||
#define CFGR0_PLL_Mask ((uint32_t)0xFFC0FFFF)
|
||||
#define CFGR0_PLLMull_Mask ((uint32_t)0x003C0000)
|
||||
#define CFGR0_PLLSRC_Mask ((uint32_t)0x00010000)
|
||||
#define CFGR0_PLLXTPRE_Mask ((uint32_t)0x00020000)
|
||||
#define CFGR0_SWS_Mask ((uint32_t)0x0000000C)
|
||||
#define CFGR0_SW_Mask ((uint32_t)0xFFFFFFFC)
|
||||
#define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F)
|
||||
#define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0)
|
||||
#define CFGR0_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF)
|
||||
#define CFGR0_PPRE1_Set_Mask ((uint32_t)0x00000700)
|
||||
#define CFGR0_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF)
|
||||
#define CFGR0_PPRE2_Set_Mask ((uint32_t)0x00003800)
|
||||
#define CFGR0_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF)
|
||||
#define CFGR0_ADCPRE_Set_Mask ((uint32_t)0x0000C000)
|
||||
|
||||
/* RSTSCKR register bit mask */
|
||||
#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000)
|
||||
|
||||
/* RCC Flag Mask */
|
||||
#define FLAG_Mask ((uint8_t)0x1F)
|
||||
|
||||
/* INTR register byte 2 (Bits[15:8]) base address */
|
||||
#define INTR_BYTE2_ADDRESS ((uint32_t)0x40021009)
|
||||
|
||||
/* INTR register byte 3 (Bits[23:16]) base address */
|
||||
#define INTR_BYTE3_ADDRESS ((uint32_t)0x4002100A)
|
||||
|
||||
/* CFGR0 register byte 4 (Bits[31:24]) base address */
|
||||
#define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007)
|
||||
|
||||
/* BDCTLR register base address */
|
||||
#define BDCTLR_ADDRESS (PERIPH_BASE + BDCTLR_OFFSET)
|
||||
|
||||
static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8};
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_DeInit
|
||||
*
|
||||
* @brief Resets the RCC clock configuration to the default reset state.
|
||||
* Note-
|
||||
* HSE can not be stopped if it is used directly or through the PLL as system clock.
|
||||
* @return none
|
||||
*/
|
||||
void RCC_DeInit(void)
|
||||
{
|
||||
RCC->CTLR |= (uint32_t)0x00000001;
|
||||
RCC->CFGR0 &= (uint32_t)0xF8FF0000;
|
||||
RCC->CTLR &= (uint32_t)0xFEF6FFFF;
|
||||
RCC->CTLR &= (uint32_t)0xFFFBFFFF;
|
||||
RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
|
||||
RCC->INTR = 0x009F0000;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_HSEConfig
|
||||
*
|
||||
* @brief Configures the External High Speed oscillator (HSE).
|
||||
*
|
||||
* @param RCC_HSE -
|
||||
* RCC_HSE_OFF - HSE oscillator OFF.
|
||||
* RCC_HSE_ON - HSE oscillator ON.
|
||||
* RCC_HSE_Bypass - HSE oscillator bypassed with external clock.
|
||||
* Note-
|
||||
* HSE can not be stopped if it is used directly or through the PLL as system clock.
|
||||
* @return none
|
||||
*/
|
||||
void RCC_HSEConfig(uint32_t RCC_HSE)
|
||||
{
|
||||
RCC->CTLR &= CTLR_HSEON_Reset;
|
||||
RCC->CTLR &= CTLR_HSEBYP_Reset;
|
||||
|
||||
switch(RCC_HSE)
|
||||
{
|
||||
case RCC_HSE_ON:
|
||||
RCC->CTLR |= CTLR_HSEON_Set;
|
||||
break;
|
||||
|
||||
case RCC_HSE_Bypass:
|
||||
RCC->CTLR |= CTLR_HSEBYP_Set | CTLR_HSEON_Set;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_WaitForHSEStartUp
|
||||
*
|
||||
* @brief Waits for HSE start-up.
|
||||
*
|
||||
* @return READY - HSE oscillator is stable and ready to use.
|
||||
* NoREADY - HSE oscillator not yet ready.
|
||||
*/
|
||||
ErrorStatus RCC_WaitForHSEStartUp(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0;
|
||||
|
||||
ErrorStatus status = NoREADY;
|
||||
FlagStatus HSEStatus = RESET;
|
||||
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
|
||||
StartUpCounter++;
|
||||
} while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET));
|
||||
|
||||
if(RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
|
||||
{
|
||||
status = READY;
|
||||
}
|
||||
else
|
||||
{
|
||||
status = NoREADY;
|
||||
}
|
||||
|
||||
return (status);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_AdjustHSICalibrationValue
|
||||
*
|
||||
* @brief Adjusts the Internal High Speed oscillator (HSI) calibration value.
|
||||
*
|
||||
* @param HSICalibrationValue - specifies the calibration trimming value.
|
||||
* This parameter must be a number between 0 and 0x1F.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
tmpreg = RCC->CTLR;
|
||||
tmpreg &= CTLR_HSITRIM_Mask;
|
||||
tmpreg |= (uint32_t)HSICalibrationValue << 3;
|
||||
RCC->CTLR = tmpreg;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_HSICmd
|
||||
*
|
||||
* @brief Enables or disables the Internal High Speed oscillator (HSI).
|
||||
*
|
||||
* @param NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RCC_HSICmd(FunctionalState NewState)
|
||||
{
|
||||
if(NewState)
|
||||
{
|
||||
RCC->CTLR |= (1 << 0);
|
||||
}
|
||||
else
|
||||
{
|
||||
RCC->CTLR &= ~(1 << 0);
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_PLLConfig
|
||||
*
|
||||
* @brief Configures the PLL clock source and multiplication factor.
|
||||
*
|
||||
* @param RCC_PLLSource - specifies the PLL entry clock source.
|
||||
* RCC_PLLSource_HSI_Div2 - HSI oscillator clock divided by 2
|
||||
* selected as PLL clock entry.
|
||||
* RCC_PLLSource_HSE_Div1 - HSE oscillator clock selected as PLL
|
||||
* clock entry.
|
||||
* RCC_PLLSource_HSE_Div2 - HSE oscillator clock divided by 2
|
||||
* selected as PLL clock entry.
|
||||
* RCC_PLLMul - specifies the PLL multiplication factor.
|
||||
* This parameter can be RCC_PLLMul_x where x:[2,16].
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
tmpreg = RCC->CFGR0;
|
||||
tmpreg &= CFGR0_PLL_Mask;
|
||||
tmpreg |= RCC_PLLSource | RCC_PLLMul;
|
||||
RCC->CFGR0 = tmpreg;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_PLLCmd
|
||||
*
|
||||
* @brief Enables or disables the PLL.
|
||||
* Note-The PLL can not be disabled if it is used as system clock.
|
||||
*
|
||||
*
|
||||
* @param NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RCC_PLLCmd(FunctionalState NewState)
|
||||
{
|
||||
if(NewState)
|
||||
{
|
||||
RCC->CTLR |= (1 << 24);
|
||||
}
|
||||
else
|
||||
{
|
||||
RCC->CTLR &= ~(1 << 24);
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_SYSCLKConfig
|
||||
*
|
||||
* @brief Configures the system clock (SYSCLK).
|
||||
*
|
||||
* @param RCC_SYSCLKSource - specifies the clock source used as system clock.
|
||||
* RCC_SYSCLKSource_HSI - HSI selected as system clock.
|
||||
* RCC_SYSCLKSource_HSE - HSE selected as system clock.
|
||||
* RCC_SYSCLKSource_PLLCLK - PLL selected as system clock.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
tmpreg = RCC->CFGR0;
|
||||
tmpreg &= CFGR0_SW_Mask;
|
||||
tmpreg |= RCC_SYSCLKSource;
|
||||
RCC->CFGR0 = tmpreg;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_GetSYSCLKSource
|
||||
*
|
||||
* @brief Returns the clock source used as system clock.
|
||||
*
|
||||
* @return 0x00 - HSI used as system clock.
|
||||
* 0x04 - HSE used as system clock.
|
||||
* 0x08 - PLL used as system clock.
|
||||
*/
|
||||
uint8_t RCC_GetSYSCLKSource(void)
|
||||
{
|
||||
return ((uint8_t)(RCC->CFGR0 & CFGR0_SWS_Mask));
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_HCLKConfig
|
||||
*
|
||||
* @brief Configures the AHB clock (HCLK).
|
||||
*
|
||||
* @param RCC_SYSCLK - defines the AHB clock divider. This clock is derived from
|
||||
* the system clock (SYSCLK).
|
||||
* RCC_SYSCLK_Div1 - AHB clock = SYSCLK.
|
||||
* RCC_SYSCLK_Div2 - AHB clock = SYSCLK/2.
|
||||
* RCC_SYSCLK_Div4 - AHB clock = SYSCLK/4.
|
||||
* RCC_SYSCLK_Div8 - AHB clock = SYSCLK/8.
|
||||
* RCC_SYSCLK_Div16 - AHB clock = SYSCLK/16.
|
||||
* RCC_SYSCLK_Div64 - AHB clock = SYSCLK/64.
|
||||
* RCC_SYSCLK_Div128 - AHB clock = SYSCLK/128.
|
||||
* RCC_SYSCLK_Div256 - AHB clock = SYSCLK/256.
|
||||
* RCC_SYSCLK_Div512 - AHB clock = SYSCLK/512.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
tmpreg = RCC->CFGR0;
|
||||
tmpreg &= CFGR0_HPRE_Reset_Mask;
|
||||
tmpreg |= RCC_SYSCLK;
|
||||
RCC->CFGR0 = tmpreg;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_PCLK1Config
|
||||
*
|
||||
* @brief Configures the Low Speed APB clock (PCLK1).
|
||||
*
|
||||
* @param RCC_HCLK - defines the APB1 clock divider. This clock is derived from
|
||||
* the AHB clock (HCLK).
|
||||
* RCC_HCLK_Div1 - APB1 clock = HCLK.
|
||||
* RCC_HCLK_Div2 - APB1 clock = HCLK/2.
|
||||
* RCC_HCLK_Div4 - APB1 clock = HCLK/4.
|
||||
* RCC_HCLK_Div8 - APB1 clock = HCLK/8.
|
||||
* RCC_HCLK_Div16 - APB1 clock = HCLK/16.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RCC_PCLK1Config(uint32_t RCC_HCLK)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
tmpreg = RCC->CFGR0;
|
||||
tmpreg &= CFGR0_PPRE1_Reset_Mask;
|
||||
tmpreg |= RCC_HCLK;
|
||||
RCC->CFGR0 = tmpreg;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_PCLK2Config
|
||||
*
|
||||
* @brief Configures the High Speed APB clock (PCLK2).
|
||||
*
|
||||
* @param RCC_HCLK - defines the APB2 clock divider. This clock is derived from
|
||||
* the AHB clock (HCLK).
|
||||
* RCC_HCLK_Div1 - APB2 clock = HCLK.
|
||||
* RCC_HCLK_Div2 - APB2 clock = HCLK/2.
|
||||
* RCC_HCLK_Div4 - APB2 clock = HCLK/4.
|
||||
* RCC_HCLK_Div8 - APB2 clock = HCLK/8.
|
||||
* RCC_HCLK_Div16 - APB2 clock = HCLK/16.
|
||||
* @return none
|
||||
*/
|
||||
void RCC_PCLK2Config(uint32_t RCC_HCLK)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
tmpreg = RCC->CFGR0;
|
||||
tmpreg &= CFGR0_PPRE2_Reset_Mask;
|
||||
tmpreg |= RCC_HCLK << 3;
|
||||
RCC->CFGR0 = tmpreg;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_ITConfig
|
||||
*
|
||||
* @brief Enables or disables the specified RCC interrupts.
|
||||
*
|
||||
* @param RCC_IT - specifies the RCC interrupt sources to be enabled or disabled.
|
||||
* RCC_IT_LSIRDY - LSI ready interrupt.
|
||||
* RCC_IT_LSERDY - LSE ready interrupt.
|
||||
* RCC_IT_HSIRDY - HSI ready interrupt.
|
||||
* RCC_IT_HSERDY - HSE ready interrupt.
|
||||
* RCC_IT_PLLRDY - PLL ready interrupt.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
*(__IO uint8_t *)INTR_BYTE2_ADDRESS |= RCC_IT;
|
||||
}
|
||||
else
|
||||
{
|
||||
*(__IO uint8_t *)INTR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_USBCLKConfig
|
||||
*
|
||||
* @brief Configures the USB clock (USBCLK).
|
||||
*
|
||||
* @param RCC_USBCLKSource: specifies the USB clock source. This clock is
|
||||
* derived from the PLL output.
|
||||
* RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB
|
||||
* clock source.
|
||||
* RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource)
|
||||
{
|
||||
if(RCC_USBCLKSource)
|
||||
{
|
||||
RCC->CFGR0 |= (1 << 22);
|
||||
}
|
||||
else
|
||||
{
|
||||
RCC->CFGR0 &= ~(1 << 22);
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_ADCCLKConfig
|
||||
*
|
||||
* @brief Configures the ADC clock (ADCCLK).
|
||||
*
|
||||
* @param RCC_PCLK2 - defines the ADC clock divider. This clock is derived from
|
||||
* the APB2 clock (PCLK2).
|
||||
* RCC_PCLK2_Div2 - ADC clock = PCLK2/2.
|
||||
* RCC_PCLK2_Div4 - ADC clock = PCLK2/4.
|
||||
* RCC_PCLK2_Div6 - ADC clock = PCLK2/6.
|
||||
* RCC_PCLK2_Div8 - ADC clock = PCLK2/8.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RCC_ADCCLKConfig(uint32_t RCC_PCLK2)
|
||||
{
|
||||
uint32_t tmpreg = 0;
|
||||
|
||||
tmpreg = RCC->CFGR0;
|
||||
tmpreg &= CFGR0_ADCPRE_Reset_Mask;
|
||||
tmpreg |= RCC_PCLK2;
|
||||
RCC->CFGR0 = tmpreg;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_LSEConfig
|
||||
*
|
||||
* @brief Configures the External Low Speed oscillator (LSE).
|
||||
*
|
||||
* @param RCC_LSE - specifies the new state of the LSE.
|
||||
* RCC_LSE_OFF - LSE oscillator OFF.
|
||||
* RCC_LSE_ON - LSE oscillator ON.
|
||||
* RCC_LSE_Bypass - LSE oscillator bypassed with external clock.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RCC_LSEConfig(uint8_t RCC_LSE)
|
||||
{
|
||||
*(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_OFF;
|
||||
*(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_OFF;
|
||||
|
||||
switch(RCC_LSE)
|
||||
{
|
||||
case RCC_LSE_ON:
|
||||
*(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_ON;
|
||||
break;
|
||||
|
||||
case RCC_LSE_Bypass:
|
||||
*(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
|
||||
break;
|
||||
|
||||
default:
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_LSICmd
|
||||
*
|
||||
* @brief Enables or disables the Internal Low Speed oscillator (LSI).
|
||||
* Note-
|
||||
* LSI can not be disabled if the IWDG is running.
|
||||
*
|
||||
* @param NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RCC_LSICmd(FunctionalState NewState)
|
||||
{
|
||||
if(NewState)
|
||||
{
|
||||
RCC->RSTSCKR |= (1 << 0);
|
||||
}
|
||||
else
|
||||
{
|
||||
RCC->RSTSCKR &= ~(1 << 0);
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_RTCCLKConfig
|
||||
*
|
||||
* @brief Once the RTC clock is selected it can't be changed unless the Backup domain is reset.
|
||||
*
|
||||
* @param RCC_RTCCLKSource - specifies the RTC clock source.
|
||||
* RCC_RTCCLKSource_LSE - LSE selected as RTC clock.
|
||||
* RCC_RTCCLKSource_LSI - LSI selected as RTC clock.
|
||||
* RCC_RTCCLKSource_HSE_Div128 - HSE clock divided by 128 selected as RTC clock.
|
||||
* Note-
|
||||
* Once the RTC clock is selected it can't be changed unless the Backup domain is reset.
|
||||
* @return none
|
||||
*/
|
||||
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
|
||||
{
|
||||
RCC->BDCTLR |= RCC_RTCCLKSource;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_RTCCLKCmd
|
||||
*
|
||||
* @brief This function must be used only after the RTC clock was selected
|
||||
* using the RCC_RTCCLKConfig function.
|
||||
*
|
||||
* @param NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RCC_RTCCLKCmd(FunctionalState NewState)
|
||||
{
|
||||
if(NewState)
|
||||
{
|
||||
RCC->BDCTLR |= (1 << 15);
|
||||
}
|
||||
else
|
||||
{
|
||||
RCC->BDCTLR &= ~(1 << 15);
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_GetClocksFreq
|
||||
*
|
||||
* @brief The result of this function could be not correct when using
|
||||
* fractional value for HSE crystal.
|
||||
*
|
||||
* @param RCC_Clocks - pointer to a RCC_ClocksTypeDef structure which will hold
|
||||
* the clocks frequencies.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks)
|
||||
{
|
||||
uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0;
|
||||
|
||||
tmp = RCC->CFGR0 & CFGR0_SWS_Mask;
|
||||
|
||||
switch(tmp)
|
||||
{
|
||||
case 0x00:
|
||||
RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
|
||||
break;
|
||||
|
||||
case 0x04:
|
||||
RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
|
||||
break;
|
||||
|
||||
case 0x08:
|
||||
pllmull = RCC->CFGR0 & CFGR0_PLLMull_Mask;
|
||||
pllsource = RCC->CFGR0 & CFGR0_PLLSRC_Mask;
|
||||
pllmull = (pllmull >> 18) + 2;
|
||||
|
||||
if(pllsource == 0x00)
|
||||
{
|
||||
if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE)
|
||||
{
|
||||
RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE)*pllmull;
|
||||
}
|
||||
else
|
||||
{
|
||||
RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if((RCC->CFGR0 & CFGR0_PLLXTPRE_Mask) != (uint32_t)RESET)
|
||||
{
|
||||
RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull;
|
||||
}
|
||||
else
|
||||
{
|
||||
RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull;
|
||||
}
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
|
||||
break;
|
||||
}
|
||||
|
||||
tmp = RCC->CFGR0 & CFGR0_HPRE_Set_Mask;
|
||||
tmp = tmp >> 4;
|
||||
presc = APBAHBPrescTable[tmp];
|
||||
RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
|
||||
tmp = RCC->CFGR0 & CFGR0_PPRE1_Set_Mask;
|
||||
tmp = tmp >> 8;
|
||||
presc = APBAHBPrescTable[tmp];
|
||||
RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
|
||||
tmp = RCC->CFGR0 & CFGR0_PPRE2_Set_Mask;
|
||||
tmp = tmp >> 11;
|
||||
presc = APBAHBPrescTable[tmp];
|
||||
RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
|
||||
tmp = RCC->CFGR0 & CFGR0_ADCPRE_Set_Mask;
|
||||
tmp = tmp >> 14;
|
||||
presc = ADCPrescTable[tmp];
|
||||
RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_AHBPeriphClockCmd
|
||||
*
|
||||
* @brief Enables or disables the AHB peripheral clock.
|
||||
*
|
||||
* @param RCC_AHBPeriph - specifies the AHB peripheral to gates its clock.
|
||||
* RCC_AHBPeriph_DMA1.
|
||||
* RCC_AHBPeriph_DMA2.
|
||||
* RCC_AHBPeriph_SRAM.
|
||||
* Note-
|
||||
* SRAM clock can be disabled only during sleep mode.
|
||||
* NewState: ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
RCC->AHBPCENR |= RCC_AHBPeriph;
|
||||
}
|
||||
else
|
||||
{
|
||||
RCC->AHBPCENR &= ~RCC_AHBPeriph;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_APB2PeriphClockCmd
|
||||
*
|
||||
* @brief Enables or disables the High Speed APB (APB2) peripheral clock.
|
||||
*
|
||||
* @param RCC_APB2Periph - specifies the APB2 peripheral to gates its clock.
|
||||
* RCC_APB2Periph_AFIO.
|
||||
* RCC_APB2Periph_GPIOA.
|
||||
* RCC_APB2Periph_GPIOB.
|
||||
* RCC_APB2Periph_GPIOC.
|
||||
* RCC_APB2Periph_GPIOD.
|
||||
* RCC_APB2Periph_GPIOE
|
||||
* RCC_APB2Periph_ADC1.
|
||||
* RCC_APB2Periph_ADC2
|
||||
* RCC_APB2Periph_TIM1.
|
||||
* RCC_APB2Periph_SPI1.
|
||||
* RCC_APB2Periph_TIM8
|
||||
* RCC_APB2Periph_USART1.
|
||||
* NewState - ENABLE or DISABLE
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
RCC->APB2PCENR |= RCC_APB2Periph;
|
||||
}
|
||||
else
|
||||
{
|
||||
RCC->APB2PCENR &= ~RCC_APB2Periph;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_APB1PeriphClockCmd
|
||||
*
|
||||
* @brief Enables or disables the Low Speed APB (APB1) peripheral clock.
|
||||
*
|
||||
* @param RCC_APB1Periph - specifies the APB1 peripheral to gates its clock.
|
||||
* RCC_APB1Periph_TIM2.
|
||||
* RCC_APB1Periph_TIM3.
|
||||
* RCC_APB1Periph_TIM4.
|
||||
* RCC_APB1Periph_WWDG.
|
||||
* RCC_APB1Periph_SPI2.
|
||||
* RCC_APB1Periph_USART2.
|
||||
* RCC_APB1Periph_I2C1.
|
||||
* RCC_APB1Periph_I2C2.
|
||||
* RCC_APB1Periph_USB.
|
||||
* RCC_APB1Periph_CAN1.
|
||||
* RCC_APB1Periph_BKP.
|
||||
* RCC_APB1Periph_PWR.
|
||||
* RCC_APB1Periph_DAC.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
RCC->APB1PCENR |= RCC_APB1Periph;
|
||||
}
|
||||
else
|
||||
{
|
||||
RCC->APB1PCENR &= ~RCC_APB1Periph;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_APB2PeriphResetCmd
|
||||
*
|
||||
* @brief Forces or releases High Speed APB (APB2) peripheral reset.
|
||||
*
|
||||
* @param RCC_APB2Periph - specifies the APB2 peripheral to reset.
|
||||
* RCC_APB2Periph_AFIO.
|
||||
* RCC_APB2Periph_GPIOA.
|
||||
* RCC_APB2Periph_GPIOB.
|
||||
* RCC_APB2Periph_GPIOC.
|
||||
* RCC_APB2Periph_GPIOD.
|
||||
* RCC_APB2Periph_GPIOE
|
||||
* RCC_APB2Periph_ADC1.
|
||||
* RCC_APB2Periph_TIM1.
|
||||
* RCC_APB2Periph_SPI1.
|
||||
* RCC_APB2Periph_USART1.
|
||||
* NewState - ENABLE or DISABLE
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
RCC->APB2PRSTR |= RCC_APB2Periph;
|
||||
}
|
||||
else
|
||||
{
|
||||
RCC->APB2PRSTR &= ~RCC_APB2Periph;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_APB1PeriphResetCmd
|
||||
*
|
||||
* @brief Forces or releases Low Speed APB (APB1) peripheral reset.
|
||||
*
|
||||
* @param RCC_APB1Periph - specifies the APB1 peripheral to reset.
|
||||
* RCC_APB1Periph_TIM2.
|
||||
* RCC_APB1Periph_TIM3.
|
||||
* RCC_APB1Periph_TIM4.
|
||||
* RCC_APB1Periph_WWDG.
|
||||
* RCC_APB1Periph_SPI2.
|
||||
* RCC_APB1Periph_USART2.
|
||||
* RCC_APB1Periph_USART3.
|
||||
* RCC_APB1Periph_I2C1.
|
||||
* RCC_APB1Periph_I2C2.
|
||||
* RCC_APB1Periph_USB.
|
||||
* RCC_APB1Periph_CAN1.
|
||||
* RCC_APB1Periph_BKP.
|
||||
* RCC_APB1Periph_PWR.
|
||||
* RCC_APB1Periph_DAC.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
RCC->APB1PRSTR |= RCC_APB1Periph;
|
||||
}
|
||||
else
|
||||
{
|
||||
RCC->APB1PRSTR &= ~RCC_APB1Periph;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_BackupResetCmd
|
||||
*
|
||||
* @brief Forces or releases the Backup domain reset.
|
||||
*
|
||||
* @param NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RCC_BackupResetCmd(FunctionalState NewState)
|
||||
{
|
||||
if(NewState)
|
||||
{
|
||||
RCC->BDCTLR |= (1 << 16);
|
||||
}
|
||||
else
|
||||
{
|
||||
RCC->BDCTLR &= ~(1 << 16);
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_ClockSecuritySystemCmd
|
||||
*
|
||||
* @brief Enables or disables the Clock Security System.
|
||||
*
|
||||
* @param NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
|
||||
{
|
||||
if(NewState)
|
||||
{
|
||||
RCC->CTLR |= (1 << 19);
|
||||
}
|
||||
else
|
||||
{
|
||||
RCC->CTLR &= ~(1 << 19);
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_MCOConfig
|
||||
*
|
||||
* @brief Selects the clock source to output on MCO pin.
|
||||
*
|
||||
* @param RCC_MCO - specifies the clock source to output.
|
||||
* RCC_MCO_NoClock - No clock selected.
|
||||
* RCC_MCO_SYSCLK - System clock selected.
|
||||
* RCC_MCO_HSI - HSI oscillator clock selected.
|
||||
* RCC_MCO_HSE - HSE oscillator clock selected.
|
||||
* RCC_MCO_PLLCLK_Div2 - PLL clock divided by 2 selected.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RCC_MCOConfig(uint8_t RCC_MCO)
|
||||
{
|
||||
*(__IO uint8_t *)CFGR0_BYTE4_ADDRESS = RCC_MCO;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_GetFlagStatus
|
||||
*
|
||||
* @brief Checks whether the specified RCC flag is set or not.
|
||||
*
|
||||
* @param RCC_FLAG - specifies the flag to check.
|
||||
* RCC_FLAG_HSIRDY - HSI oscillator clock ready.
|
||||
* RCC_FLAG_HSERDY - HSE oscillator clock ready.
|
||||
* RCC_FLAG_PLLRDY - PLL clock ready.
|
||||
* RCC_FLAG_LSERDY - LSE oscillator clock ready.
|
||||
* RCC_FLAG_LSIRDY - LSI oscillator clock ready.
|
||||
* RCC_FLAG_PINRST - Pin reset.
|
||||
* RCC_FLAG_PORRST - POR/PDR reset.
|
||||
* RCC_FLAG_SFTRST - Software reset.
|
||||
* RCC_FLAG_IWDGRST - Independent Watchdog reset.
|
||||
* RCC_FLAG_WWDGRST - Window Watchdog reset.
|
||||
* RCC_FLAG_LPWRRST - Low Power reset.
|
||||
*
|
||||
* @return FlagStatus - SET or RESET.
|
||||
*/
|
||||
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
|
||||
{
|
||||
uint32_t tmp = 0;
|
||||
uint32_t statusreg = 0;
|
||||
|
||||
FlagStatus bitstatus = RESET;
|
||||
tmp = RCC_FLAG >> 5;
|
||||
|
||||
if(tmp == 1)
|
||||
{
|
||||
statusreg = RCC->CTLR;
|
||||
}
|
||||
else if(tmp == 2)
|
||||
{
|
||||
statusreg = RCC->BDCTLR;
|
||||
}
|
||||
else
|
||||
{
|
||||
statusreg = RCC->RSTSCKR;
|
||||
}
|
||||
|
||||
tmp = RCC_FLAG & FLAG_Mask;
|
||||
|
||||
if((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_ClearFlag
|
||||
*
|
||||
* @brief Clears the RCC reset flags.
|
||||
* Note-
|
||||
* The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
|
||||
* RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
|
||||
* @return none
|
||||
*/
|
||||
void RCC_ClearFlag(void)
|
||||
{
|
||||
RCC->RSTSCKR |= RSTSCKR_RMVF_Set;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_GetITStatus
|
||||
*
|
||||
* @brief Checks whether the specified RCC interrupt has occurred or not.
|
||||
*
|
||||
* @param RCC_IT - specifies the RCC interrupt source to check.
|
||||
* RCC_IT_LSIRDY - LSI ready interrupt.
|
||||
* RCC_IT_LSERDY - LSE ready interrupt.
|
||||
* RCC_IT_HSIRDY - HSI ready interrupt.
|
||||
* RCC_IT_HSERDY - HSE ready interrupt.
|
||||
* RCC_IT_PLLRDY - PLL ready interrupt.
|
||||
* RCC_IT_CSS - Clock Security System interrupt.
|
||||
*
|
||||
* @return ITStatus - SET or RESET.
|
||||
*/
|
||||
ITStatus RCC_GetITStatus(uint8_t RCC_IT)
|
||||
{
|
||||
ITStatus bitstatus = RESET;
|
||||
|
||||
if((RCC->INTR & RCC_IT) != (uint32_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn RCC_ClearITPendingBit
|
||||
*
|
||||
* @brief Clears the RCC's interrupt pending bits.
|
||||
*
|
||||
* @param RCC_IT - specifies the interrupt pending bit to clear.
|
||||
* RCC_IT_LSIRDY - LSI ready interrupt.
|
||||
* RCC_IT_LSERDY - LSE ready interrupt.
|
||||
* RCC_IT_HSIRDY - HSI ready interrupt.
|
||||
* RCC_IT_HSERDY - HSE ready interrupt.
|
||||
* RCC_IT_PLLRDY - PLL ready interrupt.
|
||||
* RCC_IT_CSS - Clock Security System interrupt.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void RCC_ClearITPendingBit(uint8_t RCC_IT)
|
||||
{
|
||||
*(__IO uint8_t *)INTR_BYTE3_ADDRESS = RCC_IT;
|
||||
}
|
||||
|
||||
|
||||
|
||||
230
mijia_haier_bridge/src/periph/ch32v10x_rcc.h
Normal file
230
mijia_haier_bridge/src/periph/ch32v10x_rcc.h
Normal file
@ -0,0 +1,230 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v10x_rcc.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.1
|
||||
* Date : 2025/01/02
|
||||
* Description : This file provides all the RCC firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32V10x_RCC_H
|
||||
#define __CH32V10x_RCC_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "ch32v10x.h"
|
||||
|
||||
/* RCC_Exported_Types */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */
|
||||
uint32_t HCLK_Frequency; /* returns HCLK clock frequency expressed in Hz */
|
||||
uint32_t PCLK1_Frequency; /* returns PCLK1 clock frequency expressed in Hz */
|
||||
uint32_t PCLK2_Frequency; /* returns PCLK2 clock frequency expressed in Hz */
|
||||
uint32_t ADCCLK_Frequency; /* returns ADCCLK clock frequency expressed in Hz */
|
||||
} RCC_ClocksTypeDef;
|
||||
|
||||
/* HSE_configuration */
|
||||
#define RCC_HSE_OFF ((uint32_t)0x00000000)
|
||||
#define RCC_HSE_ON ((uint32_t)0x00010000)
|
||||
#define RCC_HSE_Bypass ((uint32_t)0x00040000)
|
||||
|
||||
/* PLL_entry_clock_source */
|
||||
#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000)
|
||||
#define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000)
|
||||
#define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000)
|
||||
|
||||
/* PLL_multiplication_factor */
|
||||
#define RCC_PLLMul_2 ((uint32_t)0x00000000)
|
||||
#define RCC_PLLMul_3 ((uint32_t)0x00040000)
|
||||
#define RCC_PLLMul_4 ((uint32_t)0x00080000)
|
||||
#define RCC_PLLMul_5 ((uint32_t)0x000C0000)
|
||||
#define RCC_PLLMul_6 ((uint32_t)0x00100000)
|
||||
#define RCC_PLLMul_7 ((uint32_t)0x00140000)
|
||||
#define RCC_PLLMul_8 ((uint32_t)0x00180000)
|
||||
#define RCC_PLLMul_9 ((uint32_t)0x001C0000)
|
||||
#define RCC_PLLMul_10 ((uint32_t)0x00200000)
|
||||
#define RCC_PLLMul_11 ((uint32_t)0x00240000)
|
||||
#define RCC_PLLMul_12 ((uint32_t)0x00280000)
|
||||
#define RCC_PLLMul_13 ((uint32_t)0x002C0000)
|
||||
#define RCC_PLLMul_14 ((uint32_t)0x00300000)
|
||||
#define RCC_PLLMul_15 ((uint32_t)0x00340000)
|
||||
#define RCC_PLLMul_16 ((uint32_t)0x00380000)
|
||||
|
||||
/* System_clock_source */
|
||||
#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000)
|
||||
#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001)
|
||||
#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002)
|
||||
|
||||
/* AHB_clock_source */
|
||||
#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000)
|
||||
#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080)
|
||||
#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090)
|
||||
#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0)
|
||||
#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0)
|
||||
#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0)
|
||||
#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0)
|
||||
#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0)
|
||||
#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0)
|
||||
|
||||
/* APB1_APB2_clock_source */
|
||||
#define RCC_HCLK_Div1 ((uint32_t)0x00000000)
|
||||
#define RCC_HCLK_Div2 ((uint32_t)0x00000400)
|
||||
#define RCC_HCLK_Div4 ((uint32_t)0x00000500)
|
||||
#define RCC_HCLK_Div8 ((uint32_t)0x00000600)
|
||||
#define RCC_HCLK_Div16 ((uint32_t)0x00000700)
|
||||
|
||||
/* RCC_Interrupt_source */
|
||||
#define RCC_IT_LSIRDY ((uint8_t)0x01)
|
||||
#define RCC_IT_LSERDY ((uint8_t)0x02)
|
||||
#define RCC_IT_HSIRDY ((uint8_t)0x04)
|
||||
#define RCC_IT_HSERDY ((uint8_t)0x08)
|
||||
#define RCC_IT_PLLRDY ((uint8_t)0x10)
|
||||
#define RCC_IT_CSS ((uint8_t)0x80)
|
||||
|
||||
/* USB_Device_clock_source */
|
||||
#define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00)
|
||||
#define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01)
|
||||
|
||||
/* ADC_clock_source */
|
||||
#define RCC_PCLK2_Div2 ((uint32_t)0x00000000)
|
||||
#define RCC_PCLK2_Div4 ((uint32_t)0x00004000)
|
||||
#define RCC_PCLK2_Div6 ((uint32_t)0x00008000)
|
||||
#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000)
|
||||
|
||||
/* LSE_configuration */
|
||||
#define RCC_LSE_OFF ((uint8_t)0x00)
|
||||
#define RCC_LSE_ON ((uint8_t)0x01)
|
||||
#define RCC_LSE_Bypass ((uint8_t)0x04)
|
||||
|
||||
/* RTC_clock_source */
|
||||
#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100)
|
||||
#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200)
|
||||
#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300)
|
||||
|
||||
/* AHB_peripheral */
|
||||
#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001)
|
||||
#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002)
|
||||
#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004)
|
||||
#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010)
|
||||
#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040)
|
||||
#define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100)
|
||||
#define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400)
|
||||
#define RCC_AHBPeriph_USBFS ((uint32_t)0x00001000)
|
||||
#define RCC_AHBPeriph_USBHD RCC_AHBPeriph_USBFS
|
||||
|
||||
/* APB2_peripheral */
|
||||
#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001)
|
||||
#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004)
|
||||
#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008)
|
||||
#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010)
|
||||
#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020)
|
||||
#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040)
|
||||
#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080)
|
||||
#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100)
|
||||
#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200)
|
||||
#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400)
|
||||
#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800)
|
||||
#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000)
|
||||
#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000)
|
||||
#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000)
|
||||
#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000)
|
||||
#define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000)
|
||||
#define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000)
|
||||
#define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000)
|
||||
#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000)
|
||||
#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000)
|
||||
#define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000)
|
||||
|
||||
/* APB1_peripheral */
|
||||
#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001)
|
||||
#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002)
|
||||
#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004)
|
||||
#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008)
|
||||
#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010)
|
||||
#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020)
|
||||
#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040)
|
||||
#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080)
|
||||
#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100)
|
||||
#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800)
|
||||
#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000)
|
||||
#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000)
|
||||
#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000)
|
||||
#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000)
|
||||
#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000)
|
||||
#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000)
|
||||
#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000)
|
||||
#define RCC_APB1Periph_USB ((uint32_t)0x00800000)
|
||||
#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000)
|
||||
#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000)
|
||||
#define RCC_APB1Periph_BKP ((uint32_t)0x08000000)
|
||||
#define RCC_APB1Periph_PWR ((uint32_t)0x10000000)
|
||||
#define RCC_APB1Periph_DAC ((uint32_t)0x20000000)
|
||||
#define RCC_APB1Periph_CEC ((uint32_t)0x40000000)
|
||||
|
||||
/* Clock_source_to_output_on_MCO_pin */
|
||||
#define RCC_MCO_NoClock ((uint8_t)0x00)
|
||||
#define RCC_MCO_SYSCLK ((uint8_t)0x04)
|
||||
#define RCC_MCO_HSI ((uint8_t)0x05)
|
||||
#define RCC_MCO_HSE ((uint8_t)0x06)
|
||||
#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07)
|
||||
|
||||
/* RCC_Flag */
|
||||
#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
|
||||
#define RCC_FLAG_HSERDY ((uint8_t)0x31)
|
||||
#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
|
||||
#define RCC_FLAG_LSERDY ((uint8_t)0x41)
|
||||
#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
|
||||
#define RCC_FLAG_PINRST ((uint8_t)0x7A)
|
||||
#define RCC_FLAG_PORRST ((uint8_t)0x7B)
|
||||
#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
|
||||
#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
|
||||
#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
|
||||
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
|
||||
|
||||
/* SysTick_clock_source */
|
||||
#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB)
|
||||
#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004)
|
||||
|
||||
void RCC_DeInit(void);
|
||||
void RCC_HSEConfig(uint32_t RCC_HSE);
|
||||
ErrorStatus RCC_WaitForHSEStartUp(void);
|
||||
void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
|
||||
void RCC_HSICmd(FunctionalState NewState);
|
||||
void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
|
||||
void RCC_PLLCmd(FunctionalState NewState);
|
||||
void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
|
||||
uint8_t RCC_GetSYSCLKSource(void);
|
||||
void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
|
||||
void RCC_PCLK1Config(uint32_t RCC_HCLK);
|
||||
void RCC_PCLK2Config(uint32_t RCC_HCLK);
|
||||
void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
|
||||
void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
|
||||
void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
|
||||
void RCC_LSEConfig(uint8_t RCC_LSE);
|
||||
void RCC_LSICmd(FunctionalState NewState);
|
||||
void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
|
||||
void RCC_RTCCLKCmd(FunctionalState NewState);
|
||||
void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks);
|
||||
void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
|
||||
void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||
void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||
void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
|
||||
void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
|
||||
void RCC_BackupResetCmd(FunctionalState NewState);
|
||||
void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
|
||||
void RCC_MCOConfig(uint8_t RCC_MCO);
|
||||
FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
|
||||
void RCC_ClearFlag(void);
|
||||
ITStatus RCC_GetITStatus(uint8_t RCC_IT);
|
||||
void RCC_ClearITPendingBit(uint8_t RCC_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CH32V10x_RCC_H */
|
||||
2355
mijia_haier_bridge/src/periph/ch32v10x_tim.c
Normal file
2355
mijia_haier_bridge/src/periph/ch32v10x_tim.c
Normal file
File diff suppressed because it is too large
Load Diff
508
mijia_haier_bridge/src/periph/ch32v10x_tim.h
Normal file
508
mijia_haier_bridge/src/periph/ch32v10x_tim.h
Normal file
@ -0,0 +1,508 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v10x_tim.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2020/04/30
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* TIM firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32V10x_TIM_H
|
||||
#define __CH32V10x_TIM_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "ch32v10x.h"
|
||||
|
||||
/* TIM Time Base Init structure definition */
|
||||
typedef struct
|
||||
{
|
||||
uint16_t TIM_Prescaler; /* Specifies the prescaler value used to divide the TIM clock.
|
||||
This parameter can be a number between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t TIM_CounterMode; /* Specifies the counter mode.
|
||||
This parameter can be a value of @ref TIM_Counter_Mode */
|
||||
|
||||
uint16_t TIM_Period; /* Specifies the period value to be loaded into the active
|
||||
Auto-Reload Register at the next update event.
|
||||
This parameter must be a number between 0x0000 and 0xFFFF. */
|
||||
|
||||
uint16_t TIM_ClockDivision; /* Specifies the clock division.
|
||||
This parameter can be a value of @ref TIM_Clock_Division_CKD */
|
||||
|
||||
uint8_t TIM_RepetitionCounter; /* Specifies the repetition counter value. Each time the RCR downcounter
|
||||
reaches zero, an update event is generated and counting restarts
|
||||
from the RCR value (N).
|
||||
This means in PWM mode that (N+1) corresponds to:
|
||||
- the number of PWM periods in edge-aligned mode
|
||||
- the number of half PWM period in center-aligned mode
|
||||
This parameter must be a number between 0x00 and 0xFF.
|
||||
@note This parameter is valid only for TIM1 and TIM8. */
|
||||
} TIM_TimeBaseInitTypeDef;
|
||||
|
||||
/* TIM Output Compare Init structure definition */
|
||||
typedef struct
|
||||
{
|
||||
uint16_t TIM_OCMode; /* Specifies the TIM mode.
|
||||
This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
|
||||
|
||||
uint16_t TIM_OutputState; /* Specifies the TIM Output Compare state.
|
||||
This parameter can be a value of @ref TIM_Output_Compare_state */
|
||||
|
||||
uint16_t TIM_OutputNState; /* Specifies the TIM complementary Output Compare state.
|
||||
This parameter can be a value of @ref TIM_Output_Compare_N_state
|
||||
@note This parameter is valid only for TIM1 and TIM8. */
|
||||
|
||||
uint16_t TIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register.
|
||||
This parameter can be a number between 0x0000 and 0xFFFF */
|
||||
|
||||
uint16_t TIM_OCPolarity; /* Specifies the output polarity.
|
||||
This parameter can be a value of @ref TIM_Output_Compare_Polarity */
|
||||
|
||||
uint16_t TIM_OCNPolarity; /* Specifies the complementary output polarity.
|
||||
This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
|
||||
@note This parameter is valid only for TIM1 and TIM8. */
|
||||
|
||||
uint16_t TIM_OCIdleState; /* Specifies the TIM Output Compare pin state during Idle state.
|
||||
This parameter can be a value of @ref TIM_Output_Compare_Idle_State
|
||||
@note This parameter is valid only for TIM1 and TIM8. */
|
||||
|
||||
uint16_t TIM_OCNIdleState; /* Specifies the TIM Output Compare pin state during Idle state.
|
||||
This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
|
||||
@note This parameter is valid only for TIM1 and TIM8. */
|
||||
} TIM_OCInitTypeDef;
|
||||
|
||||
/* TIM Input Capture Init structure definition */
|
||||
typedef struct
|
||||
{
|
||||
uint16_t TIM_Channel; /* Specifies the TIM channel.
|
||||
This parameter can be a value of @ref TIM_Channel */
|
||||
|
||||
uint16_t TIM_ICPolarity; /* Specifies the active edge of the input signal.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Polarity */
|
||||
|
||||
uint16_t TIM_ICSelection; /* Specifies the input.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Selection */
|
||||
|
||||
uint16_t TIM_ICPrescaler; /* Specifies the Input Capture Prescaler.
|
||||
This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
|
||||
|
||||
uint16_t TIM_ICFilter; /* Specifies the input capture filter.
|
||||
This parameter can be a number between 0x0 and 0xF */
|
||||
} TIM_ICInitTypeDef;
|
||||
|
||||
/* BDTR structure definition */
|
||||
typedef struct
|
||||
{
|
||||
uint16_t TIM_OSSRState; /* Specifies the Off-State selection used in Run mode.
|
||||
This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */
|
||||
|
||||
uint16_t TIM_OSSIState; /* Specifies the Off-State used in Idle state.
|
||||
This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */
|
||||
|
||||
uint16_t TIM_LOCKLevel; /* Specifies the LOCK level parameters.
|
||||
This parameter can be a value of @ref Lock_level */
|
||||
|
||||
uint16_t TIM_DeadTime; /* Specifies the delay time between the switching-off and the
|
||||
switching-on of the outputs.
|
||||
This parameter can be a number between 0x00 and 0xFF */
|
||||
|
||||
uint16_t TIM_Break; /* Specifies whether the TIM Break input is enabled or not.
|
||||
This parameter can be a value of @ref Break_Input_enable_disable */
|
||||
|
||||
uint16_t TIM_BreakPolarity; /* Specifies the TIM Break Input pin polarity.
|
||||
This parameter can be a value of @ref Break_Polarity */
|
||||
|
||||
uint16_t TIM_AutomaticOutput; /* Specifies whether the TIM Automatic Output feature is enabled or not.
|
||||
This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
|
||||
} TIM_BDTRInitTypeDef;
|
||||
|
||||
/* TIM_Output_Compare_and_PWM_modes */
|
||||
#define TIM_OCMode_Timing ((uint16_t)0x0000)
|
||||
#define TIM_OCMode_Active ((uint16_t)0x0010)
|
||||
#define TIM_OCMode_Inactive ((uint16_t)0x0020)
|
||||
#define TIM_OCMode_Toggle ((uint16_t)0x0030)
|
||||
#define TIM_OCMode_PWM1 ((uint16_t)0x0060)
|
||||
#define TIM_OCMode_PWM2 ((uint16_t)0x0070)
|
||||
|
||||
/* TIM_One_Pulse_Mode */
|
||||
#define TIM_OPMode_Single ((uint16_t)0x0008)
|
||||
#define TIM_OPMode_Repetitive ((uint16_t)0x0000)
|
||||
|
||||
/* TIM_Channel */
|
||||
#define TIM_Channel_1 ((uint16_t)0x0000)
|
||||
#define TIM_Channel_2 ((uint16_t)0x0004)
|
||||
#define TIM_Channel_3 ((uint16_t)0x0008)
|
||||
#define TIM_Channel_4 ((uint16_t)0x000C)
|
||||
|
||||
/* TIM_Clock_Division_CKD */
|
||||
#define TIM_CKD_DIV1 ((uint16_t)0x0000)
|
||||
#define TIM_CKD_DIV2 ((uint16_t)0x0100)
|
||||
#define TIM_CKD_DIV4 ((uint16_t)0x0200)
|
||||
|
||||
/* TIM_Counter_Mode */
|
||||
#define TIM_CounterMode_Up ((uint16_t)0x0000)
|
||||
#define TIM_CounterMode_Down ((uint16_t)0x0010)
|
||||
#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
|
||||
#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
|
||||
#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
|
||||
|
||||
/* TIM_Output_Compare_Polarity */
|
||||
#define TIM_OCPolarity_High ((uint16_t)0x0000)
|
||||
#define TIM_OCPolarity_Low ((uint16_t)0x0002)
|
||||
|
||||
/* TIM_Output_Compare_N_Polarity */
|
||||
#define TIM_OCNPolarity_High ((uint16_t)0x0000)
|
||||
#define TIM_OCNPolarity_Low ((uint16_t)0x0008)
|
||||
|
||||
/* TIM_Output_Compare_state */
|
||||
#define TIM_OutputState_Disable ((uint16_t)0x0000)
|
||||
#define TIM_OutputState_Enable ((uint16_t)0x0001)
|
||||
|
||||
/* TIM_Output_Compare_N_state */
|
||||
#define TIM_OutputNState_Disable ((uint16_t)0x0000)
|
||||
#define TIM_OutputNState_Enable ((uint16_t)0x0004)
|
||||
|
||||
/* TIM_Capture_Compare_state */
|
||||
#define TIM_CCx_Enable ((uint16_t)0x0001)
|
||||
#define TIM_CCx_Disable ((uint16_t)0x0000)
|
||||
|
||||
/* TIM_Capture_Compare_N_state */
|
||||
#define TIM_CCxN_Enable ((uint16_t)0x0004)
|
||||
#define TIM_CCxN_Disable ((uint16_t)0x0000)
|
||||
|
||||
/* Break_Input_enable_disable */
|
||||
#define TIM_Break_Enable ((uint16_t)0x1000)
|
||||
#define TIM_Break_Disable ((uint16_t)0x0000)
|
||||
|
||||
/* Break_Polarity */
|
||||
#define TIM_BreakPolarity_Low ((uint16_t)0x0000)
|
||||
#define TIM_BreakPolarity_High ((uint16_t)0x2000)
|
||||
|
||||
/* TIM_AOE_Bit_Set_Reset */
|
||||
#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
|
||||
#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
|
||||
|
||||
/* Lock_level */
|
||||
#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
|
||||
#define TIM_LOCKLevel_1 ((uint16_t)0x0100)
|
||||
#define TIM_LOCKLevel_2 ((uint16_t)0x0200)
|
||||
#define TIM_LOCKLevel_3 ((uint16_t)0x0300)
|
||||
|
||||
/* OSSI_Off_State_Selection_for_Idle_mode_state */
|
||||
#define TIM_OSSIState_Enable ((uint16_t)0x0400)
|
||||
#define TIM_OSSIState_Disable ((uint16_t)0x0000)
|
||||
|
||||
/* OSSR_Off_State_Selection_for_Run_mode_state */
|
||||
#define TIM_OSSRState_Enable ((uint16_t)0x0800)
|
||||
#define TIM_OSSRState_Disable ((uint16_t)0x0000)
|
||||
|
||||
/* TIM_Output_Compare_Idle_State */
|
||||
#define TIM_OCIdleState_Set ((uint16_t)0x0100)
|
||||
#define TIM_OCIdleState_Reset ((uint16_t)0x0000)
|
||||
|
||||
/* TIM_Output_Compare_N_Idle_State */
|
||||
#define TIM_OCNIdleState_Set ((uint16_t)0x0200)
|
||||
#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
|
||||
|
||||
/* TIM_Input_Capture_Polarity */
|
||||
#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
|
||||
#define TIM_ICPolarity_Falling ((uint16_t)0x0002)
|
||||
#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
|
||||
|
||||
/* TIM_Input_Capture_Selection */
|
||||
#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be \
|
||||
connected to IC1, IC2, IC3 or IC4, respectively */
|
||||
#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be \
|
||||
connected to IC2, IC1, IC4 or IC3, respectively. */
|
||||
#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
|
||||
|
||||
/* TIM_Input_Capture_Prescaler */
|
||||
#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */
|
||||
#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */
|
||||
#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */
|
||||
#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */
|
||||
|
||||
/* TIM_interrupt_sources */
|
||||
#define TIM_IT_Update ((uint16_t)0x0001)
|
||||
#define TIM_IT_CC1 ((uint16_t)0x0002)
|
||||
#define TIM_IT_CC2 ((uint16_t)0x0004)
|
||||
#define TIM_IT_CC3 ((uint16_t)0x0008)
|
||||
#define TIM_IT_CC4 ((uint16_t)0x0010)
|
||||
#define TIM_IT_COM ((uint16_t)0x0020)
|
||||
#define TIM_IT_Trigger ((uint16_t)0x0040)
|
||||
#define TIM_IT_Break ((uint16_t)0x0080)
|
||||
|
||||
/* TIM_DMA_Base_address */
|
||||
#define TIM_DMABase_CR1 ((uint16_t)0x0000)
|
||||
#define TIM_DMABase_CR2 ((uint16_t)0x0001)
|
||||
#define TIM_DMABase_SMCR ((uint16_t)0x0002)
|
||||
#define TIM_DMABase_DIER ((uint16_t)0x0003)
|
||||
#define TIM_DMABase_SR ((uint16_t)0x0004)
|
||||
#define TIM_DMABase_EGR ((uint16_t)0x0005)
|
||||
#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
|
||||
#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
|
||||
#define TIM_DMABase_CCER ((uint16_t)0x0008)
|
||||
#define TIM_DMABase_CNT ((uint16_t)0x0009)
|
||||
#define TIM_DMABase_PSC ((uint16_t)0x000A)
|
||||
#define TIM_DMABase_ARR ((uint16_t)0x000B)
|
||||
#define TIM_DMABase_RCR ((uint16_t)0x000C)
|
||||
#define TIM_DMABase_CCR1 ((uint16_t)0x000D)
|
||||
#define TIM_DMABase_CCR2 ((uint16_t)0x000E)
|
||||
#define TIM_DMABase_CCR3 ((uint16_t)0x000F)
|
||||
#define TIM_DMABase_CCR4 ((uint16_t)0x0010)
|
||||
#define TIM_DMABase_BDTR ((uint16_t)0x0011)
|
||||
#define TIM_DMABase_DCR ((uint16_t)0x0012)
|
||||
|
||||
/* TIM_DMA_Burst_Length */
|
||||
#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
|
||||
#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
|
||||
#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
|
||||
#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
|
||||
#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
|
||||
#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
|
||||
#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
|
||||
#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
|
||||
#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
|
||||
#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
|
||||
#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
|
||||
#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
|
||||
#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
|
||||
#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
|
||||
#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
|
||||
#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
|
||||
#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
|
||||
#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
|
||||
|
||||
/* TIM_DMA_sources */
|
||||
#define TIM_DMA_Update ((uint16_t)0x0100)
|
||||
#define TIM_DMA_CC1 ((uint16_t)0x0200)
|
||||
#define TIM_DMA_CC2 ((uint16_t)0x0400)
|
||||
#define TIM_DMA_CC3 ((uint16_t)0x0800)
|
||||
#define TIM_DMA_CC4 ((uint16_t)0x1000)
|
||||
#define TIM_DMA_COM ((uint16_t)0x2000)
|
||||
#define TIM_DMA_Trigger ((uint16_t)0x4000)
|
||||
|
||||
/* TIM_External_Trigger_Prescaler */
|
||||
#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
|
||||
#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
|
||||
#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
|
||||
#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
|
||||
|
||||
/* TIM_Internal_Trigger_Selection */
|
||||
#define TIM_TS_ITR0 ((uint16_t)0x0000)
|
||||
#define TIM_TS_ITR1 ((uint16_t)0x0010)
|
||||
#define TIM_TS_ITR2 ((uint16_t)0x0020)
|
||||
#define TIM_TS_ITR3 ((uint16_t)0x0030)
|
||||
#define TIM_TS_TI1F_ED ((uint16_t)0x0040)
|
||||
#define TIM_TS_TI1FP1 ((uint16_t)0x0050)
|
||||
#define TIM_TS_TI2FP2 ((uint16_t)0x0060)
|
||||
#define TIM_TS_ETRF ((uint16_t)0x0070)
|
||||
|
||||
/* TIM_TIx_External_Clock_Source */
|
||||
#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
|
||||
#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
|
||||
#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
|
||||
|
||||
/* TIM_External_Trigger_Polarity */
|
||||
#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
|
||||
#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
|
||||
|
||||
/* TIM_Prescaler_Reload_Mode */
|
||||
#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
|
||||
#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
|
||||
|
||||
/* TIM_Forced_Action */
|
||||
#define TIM_ForcedAction_Active ((uint16_t)0x0050)
|
||||
#define TIM_ForcedAction_InActive ((uint16_t)0x0040)
|
||||
|
||||
/* TIM_Encoder_Mode */
|
||||
#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
|
||||
#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
|
||||
#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
|
||||
|
||||
/* TIM_Event_Source */
|
||||
#define TIM_EventSource_Update ((uint16_t)0x0001)
|
||||
#define TIM_EventSource_CC1 ((uint16_t)0x0002)
|
||||
#define TIM_EventSource_CC2 ((uint16_t)0x0004)
|
||||
#define TIM_EventSource_CC3 ((uint16_t)0x0008)
|
||||
#define TIM_EventSource_CC4 ((uint16_t)0x0010)
|
||||
#define TIM_EventSource_COM ((uint16_t)0x0020)
|
||||
#define TIM_EventSource_Trigger ((uint16_t)0x0040)
|
||||
#define TIM_EventSource_Break ((uint16_t)0x0080)
|
||||
|
||||
/* TIM_Update_Source */
|
||||
#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow \
|
||||
or the setting of UG bit, or an update generation \
|
||||
through the slave mode controller. */
|
||||
#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */
|
||||
|
||||
/* TIM_Output_Compare_Preload_State */
|
||||
#define TIM_OCPreload_Enable ((uint16_t)0x0008)
|
||||
#define TIM_OCPreload_Disable ((uint16_t)0x0000)
|
||||
|
||||
/* TIM_Output_Compare_Fast_State */
|
||||
#define TIM_OCFast_Enable ((uint16_t)0x0004)
|
||||
#define TIM_OCFast_Disable ((uint16_t)0x0000)
|
||||
|
||||
/* TIM_Output_Compare_Clear_State */
|
||||
#define TIM_OCClear_Enable ((uint16_t)0x0080)
|
||||
#define TIM_OCClear_Disable ((uint16_t)0x0000)
|
||||
|
||||
/* TIM_Trigger_Output_Source */
|
||||
#define TIM_TRGOSource_Reset ((uint16_t)0x0000)
|
||||
#define TIM_TRGOSource_Enable ((uint16_t)0x0010)
|
||||
#define TIM_TRGOSource_Update ((uint16_t)0x0020)
|
||||
#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
|
||||
#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
|
||||
#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
|
||||
#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
|
||||
#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
|
||||
|
||||
/* TIM_Slave_Mode */
|
||||
#define TIM_SlaveMode_Reset ((uint16_t)0x0004)
|
||||
#define TIM_SlaveMode_Gated ((uint16_t)0x0005)
|
||||
#define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
|
||||
#define TIM_SlaveMode_External1 ((uint16_t)0x0007)
|
||||
|
||||
/* TIM_Master_Slave_Mode */
|
||||
#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
|
||||
#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
|
||||
|
||||
/* TIM_Flags */
|
||||
#define TIM_FLAG_Update ((uint16_t)0x0001)
|
||||
#define TIM_FLAG_CC1 ((uint16_t)0x0002)
|
||||
#define TIM_FLAG_CC2 ((uint16_t)0x0004)
|
||||
#define TIM_FLAG_CC3 ((uint16_t)0x0008)
|
||||
#define TIM_FLAG_CC4 ((uint16_t)0x0010)
|
||||
#define TIM_FLAG_COM ((uint16_t)0x0020)
|
||||
#define TIM_FLAG_Trigger ((uint16_t)0x0040)
|
||||
#define TIM_FLAG_Break ((uint16_t)0x0080)
|
||||
#define TIM_FLAG_CC1OF ((uint16_t)0x0200)
|
||||
#define TIM_FLAG_CC2OF ((uint16_t)0x0400)
|
||||
#define TIM_FLAG_CC3OF ((uint16_t)0x0800)
|
||||
#define TIM_FLAG_CC4OF ((uint16_t)0x1000)
|
||||
|
||||
/* TIM_Legacy */
|
||||
#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
|
||||
#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
|
||||
#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
|
||||
#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
|
||||
#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
|
||||
#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
|
||||
#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
|
||||
#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
|
||||
#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
|
||||
#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
|
||||
#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
|
||||
#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
|
||||
#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
|
||||
#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
|
||||
#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
|
||||
#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
|
||||
#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
|
||||
#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
|
||||
|
||||
void TIM_DeInit(TIM_TypeDef *TIMx);
|
||||
void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct);
|
||||
void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct);
|
||||
void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct);
|
||||
void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct);
|
||||
void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct);
|
||||
void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct);
|
||||
void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct);
|
||||
void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
|
||||
void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct);
|
||||
void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct);
|
||||
void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct);
|
||||
void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
|
||||
void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState);
|
||||
void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState);
|
||||
void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState);
|
||||
void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource);
|
||||
void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
|
||||
void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
|
||||
void TIM_InternalClockConfig(TIM_TypeDef *TIMx);
|
||||
void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource);
|
||||
void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource,
|
||||
uint16_t TIM_ICPolarity, uint16_t ICFilter);
|
||||
void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
|
||||
uint16_t ExtTRGFilter);
|
||||
void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler,
|
||||
uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
|
||||
void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
|
||||
uint16_t ExtTRGFilter);
|
||||
void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
|
||||
void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode);
|
||||
void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource);
|
||||
void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode,
|
||||
uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
|
||||
void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction);
|
||||
void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction);
|
||||
void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction);
|
||||
void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction);
|
||||
void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState);
|
||||
void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState);
|
||||
void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState);
|
||||
void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState);
|
||||
void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload);
|
||||
void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload);
|
||||
void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload);
|
||||
void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload);
|
||||
void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast);
|
||||
void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast);
|
||||
void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast);
|
||||
void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast);
|
||||
void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear);
|
||||
void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear);
|
||||
void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear);
|
||||
void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear);
|
||||
void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity);
|
||||
void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity);
|
||||
void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity);
|
||||
void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity);
|
||||
void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity);
|
||||
void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity);
|
||||
void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity);
|
||||
void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
|
||||
void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
|
||||
void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
|
||||
void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState);
|
||||
void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource);
|
||||
void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState);
|
||||
void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode);
|
||||
void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource);
|
||||
void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode);
|
||||
void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode);
|
||||
void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter);
|
||||
void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload);
|
||||
void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1);
|
||||
void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2);
|
||||
void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3);
|
||||
void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4);
|
||||
void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC);
|
||||
void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC);
|
||||
void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC);
|
||||
void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC);
|
||||
void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD);
|
||||
uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx);
|
||||
uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx);
|
||||
uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx);
|
||||
uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx);
|
||||
uint16_t TIM_GetCounter(TIM_TypeDef *TIMx);
|
||||
uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx);
|
||||
FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG);
|
||||
void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG);
|
||||
ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT);
|
||||
void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__CH32V10x_TIM_H */
|
||||
747
mijia_haier_bridge/src/periph/ch32v10x_usart.c
Normal file
747
mijia_haier_bridge/src/periph/ch32v10x_usart.c
Normal file
@ -0,0 +1,747 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v10x_usart.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/01/06
|
||||
* Description : This file provides all the USART firmware functions.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32v10x_usart.h"
|
||||
#include "ch32v10x_rcc.h"
|
||||
|
||||
/* USART_Private_Defines */
|
||||
#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */
|
||||
#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */
|
||||
|
||||
#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */
|
||||
|
||||
#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */
|
||||
#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */
|
||||
#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */
|
||||
#define CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CTLR1 Mask */
|
||||
#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */
|
||||
|
||||
#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */
|
||||
#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */
|
||||
|
||||
#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */
|
||||
#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CTLR2 STOP Bits Mask */
|
||||
#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CTLR2 Clock Mask */
|
||||
|
||||
#define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */
|
||||
#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */
|
||||
|
||||
#define CTLR3_NACK_Set ((uint16_t)0x0010) /* USART SC NACK Enable Mask */
|
||||
#define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */
|
||||
|
||||
#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */
|
||||
#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */
|
||||
|
||||
#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */
|
||||
#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CTLR3 Mask */
|
||||
|
||||
#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */
|
||||
#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */
|
||||
#define GPR_LSB_Mask ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */
|
||||
#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */
|
||||
#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_DeInit
|
||||
*
|
||||
* @brief Deinitializes the USARTx peripheral registers to their default
|
||||
* reset values.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2 or 3 to select the UART peripheral.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_DeInit(USART_TypeDef *USARTx)
|
||||
{
|
||||
if(USARTx == USART1)
|
||||
{
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
|
||||
RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
|
||||
}
|
||||
else if(USARTx == USART2)
|
||||
{
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
|
||||
}
|
||||
else if(USARTx == USART3)
|
||||
{
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
|
||||
}
|
||||
else if(USARTx == UART4)
|
||||
{
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
|
||||
}
|
||||
else
|
||||
{
|
||||
if(USARTx == UART5)
|
||||
{
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
|
||||
RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_Init
|
||||
*
|
||||
* @brief Initializes the USARTx peripheral according to the specified
|
||||
* parameters in the USART_InitStruct.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2 or 3 to select the UART peripheral.
|
||||
* USART_InitStruct - pointer to a USART_InitTypeDef structure
|
||||
* that contains the configuration information for the specified
|
||||
* USART peripheral.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct)
|
||||
{
|
||||
uint32_t tmpreg = 0x00, apbclock = 0x00;
|
||||
uint32_t integerdivider = 0x00;
|
||||
uint32_t fractionaldivider = 0x00;
|
||||
uint32_t usartxbase = 0;
|
||||
RCC_ClocksTypeDef RCC_ClocksStatus;
|
||||
|
||||
if(USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)
|
||||
{
|
||||
}
|
||||
|
||||
usartxbase = (uint32_t)USARTx;
|
||||
tmpreg = USARTx->CTLR2;
|
||||
tmpreg &= CTLR2_STOP_CLEAR_Mask;
|
||||
tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
|
||||
|
||||
USARTx->CTLR2 = (uint16_t)tmpreg;
|
||||
tmpreg = USARTx->CTLR1;
|
||||
tmpreg &= CTLR1_CLEAR_Mask;
|
||||
tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
|
||||
USART_InitStruct->USART_Mode;
|
||||
USARTx->CTLR1 = (uint16_t)tmpreg;
|
||||
|
||||
tmpreg = USARTx->CTLR3;
|
||||
tmpreg &= CTLR3_CLEAR_Mask;
|
||||
tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
|
||||
USARTx->CTLR3 = (uint16_t)tmpreg;
|
||||
|
||||
RCC_GetClocksFreq(&RCC_ClocksStatus);
|
||||
|
||||
if(usartxbase == USART1_BASE)
|
||||
{
|
||||
apbclock = RCC_ClocksStatus.PCLK2_Frequency;
|
||||
}
|
||||
else
|
||||
{
|
||||
apbclock = RCC_ClocksStatus.PCLK1_Frequency;
|
||||
}
|
||||
|
||||
integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));
|
||||
tmpreg = (integerdivider / 100) << 4;
|
||||
fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
|
||||
tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
|
||||
USARTx->BRR = (uint16_t)tmpreg;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_StructInit
|
||||
*
|
||||
* @brief Fills each USART_InitStruct member with its default value.
|
||||
*
|
||||
* @param USART_InitStruct: pointer to a USART_InitTypeDef structure
|
||||
* which will be initialized.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_StructInit(USART_InitTypeDef *USART_InitStruct)
|
||||
{
|
||||
USART_InitStruct->USART_BaudRate = 9600;
|
||||
USART_InitStruct->USART_WordLength = USART_WordLength_8b;
|
||||
USART_InitStruct->USART_StopBits = USART_StopBits_1;
|
||||
USART_InitStruct->USART_Parity = USART_Parity_No;
|
||||
USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
|
||||
USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_ClockInit
|
||||
*
|
||||
* @brief Initializes the USARTx peripheral Clock according to the
|
||||
* specified parameters in the USART_ClockInitStruct .
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef
|
||||
* structure that contains the configuration information for the specified
|
||||
* USART peripheral.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct)
|
||||
{
|
||||
uint32_t tmpreg = 0x00;
|
||||
|
||||
tmpreg = USARTx->CTLR2;
|
||||
tmpreg &= CTLR2_CLOCK_CLEAR_Mask;
|
||||
tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL |
|
||||
USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;
|
||||
USARTx->CTLR2 = (uint16_t)tmpreg;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_ClockStructInit
|
||||
*
|
||||
* @brief Fills each USART_ClockStructInit member with its default value.
|
||||
*
|
||||
* @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef
|
||||
* structure which will be initialized.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct)
|
||||
{
|
||||
USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
|
||||
USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
|
||||
USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
|
||||
USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_Cmd
|
||||
*
|
||||
* @brief Enables or disables the specified USART peripheral.
|
||||
* reset values (Affects also the I2Ss).
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* NewState: ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
USARTx->CTLR1 |= CTLR1_UE_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
USARTx->CTLR1 &= CTLR1_UE_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_ITConfig
|
||||
*
|
||||
* @brief Enables or disables the specified USART interrupts.
|
||||
* reset values (Affects also the I2Ss).
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* USART_IT - specifies the USART interrupt sources to be enabled or disabled.
|
||||
* USART_IT_LBD - LIN Break detection interrupt.
|
||||
* USART_IT_TXE - Transmit Data Register empty interrupt.
|
||||
* USART_IT_TC - Transmission complete interrupt.
|
||||
* USART_IT_RXNE - Receive Data register not empty interrupt.
|
||||
* USART_IT_IDLE - Idle line detection interrupt.
|
||||
* USART_IT_PE - Parity Error interrupt.
|
||||
* USART_IT_ERR - Error interrupt.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState)
|
||||
{
|
||||
uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
|
||||
uint32_t usartxbase = 0x00;
|
||||
|
||||
usartxbase = (uint32_t)USARTx;
|
||||
usartreg = (((uint8_t)USART_IT) >> 0x05);
|
||||
itpos = USART_IT & IT_Mask;
|
||||
itmask = (((uint32_t)0x01) << itpos);
|
||||
|
||||
if(usartreg == 0x01)
|
||||
{
|
||||
usartxbase += 0x0C;
|
||||
}
|
||||
else if(usartreg == 0x02)
|
||||
{
|
||||
usartxbase += 0x10;
|
||||
}
|
||||
else
|
||||
{
|
||||
usartxbase += 0x14;
|
||||
}
|
||||
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
*(__IO uint32_t *)usartxbase |= itmask;
|
||||
}
|
||||
else
|
||||
{
|
||||
*(__IO uint32_t *)usartxbase &= ~itmask;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_DMACmd
|
||||
*
|
||||
* @brief Enables or disables the USART DMA interface.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* USART_DMAReq - specifies the DMA request.
|
||||
* USART_DMAReq_Tx - USART DMA transmit request.
|
||||
* USART_DMAReq_Rx - USART DMA receive request.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
USARTx->CTLR3 |= USART_DMAReq;
|
||||
}
|
||||
else
|
||||
{
|
||||
USARTx->CTLR3 &= (uint16_t)~USART_DMAReq;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_SetAddress
|
||||
*
|
||||
* @brief Sets the address of the USART node.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* USART_Address - Indicates the address of the USART node.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address)
|
||||
{
|
||||
USARTx->CTLR2 &= CTLR2_Address_Mask;
|
||||
USARTx->CTLR2 |= USART_Address;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_WakeUpConfig
|
||||
*
|
||||
* @brief Selects the USART WakeUp method.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* USART_WakeUp - specifies the USART wakeup method.
|
||||
* USART_WakeUp_IdleLine - WakeUp by an idle line detection.
|
||||
* USART_WakeUp_AddressMark - WakeUp by an address mark.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp)
|
||||
{
|
||||
USARTx->CTLR1 &= CTLR1_WAKE_Mask;
|
||||
USARTx->CTLR1 |= USART_WakeUp;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_ReceiverWakeUpCmd
|
||||
*
|
||||
* @brief Determines if the USART is in mute mode or not.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
USARTx->CTLR1 |= CTLR1_RWU_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
USARTx->CTLR1 &= CTLR1_RWU_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_LINBreakDetectLengthConfig
|
||||
*
|
||||
* @brief Sets the USART LIN Break detection length.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* USART_LINBreakDetectLength - specifies the LIN break detection length.
|
||||
* USART_LINBreakDetectLength_10b - 10-bit break detection.
|
||||
* USART_LINBreakDetectLength_11b - 11-bit break detection.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength)
|
||||
{
|
||||
USARTx->CTLR2 &= CTLR2_LBDL_Mask;
|
||||
USARTx->CTLR2 |= USART_LINBreakDetectLength;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_LINCmd
|
||||
*
|
||||
* @brief Enables or disables the USART LIN mode.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
USARTx->CTLR2 |= CTLR2_LINEN_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
USARTx->CTLR2 &= CTLR2_LINEN_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_SendData
|
||||
*
|
||||
* @brief Transmits single data through the USARTx peripheral.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* Data - the data to transmit.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_SendData(USART_TypeDef *USARTx, uint16_t Data)
|
||||
{
|
||||
USARTx->DATAR = (Data & (uint16_t)0x01FF);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_ReceiveData
|
||||
*
|
||||
* @brief Returns the most recent received data by the USARTx peripheral.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
*
|
||||
* @return The received data.
|
||||
*/
|
||||
uint16_t USART_ReceiveData(USART_TypeDef *USARTx)
|
||||
{
|
||||
return (uint16_t)(USARTx->DATAR & (uint16_t)0x01FF);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_SendBreak
|
||||
*
|
||||
* @brief Transmits break characters.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_SendBreak(USART_TypeDef *USARTx)
|
||||
{
|
||||
USARTx->CTLR1 |= CTLR1_SBK_Set;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_SetGuardTime
|
||||
*
|
||||
* @brief Sets the specified USART guard time.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* USART_GuardTime - specifies the guard time.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime)
|
||||
{
|
||||
USARTx->GPR &= GPR_LSB_Mask;
|
||||
USARTx->GPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_SetPrescaler
|
||||
*
|
||||
* @brief Sets the system clock prescaler.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* USART_Prescaler - specifies the prescaler clock.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler)
|
||||
{
|
||||
USARTx->GPR &= GPR_MSB_Mask;
|
||||
USARTx->GPR |= USART_Prescaler;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_SmartCardCmd
|
||||
*
|
||||
* @brief Enables or disables the USART Smart Card mode.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
USARTx->CTLR3 |= CTLR3_SCEN_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
USARTx->CTLR3 &= CTLR3_SCEN_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_SmartCardNACKCmd
|
||||
*
|
||||
* @brief Enables or disables NACK transmission.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
USARTx->CTLR3 |= CTLR3_NACK_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
USARTx->CTLR3 &= CTLR3_NACK_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_HalfDuplexCmd
|
||||
*
|
||||
* @brief Enables or disables the USART Half Duplex communication.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
USARTx->CTLR3 |= CTLR3_HDSEL_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
USARTx->CTLR3 &= CTLR3_HDSEL_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_IrDAConfig
|
||||
*
|
||||
* @brief Configures the USART's IrDA interface.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* USART_IrDAMode - specifies the IrDA mode.
|
||||
* USART_IrDAMode_LowPower.
|
||||
* USART_IrDAMode_Normal.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode)
|
||||
{
|
||||
USARTx->CTLR3 &= CTLR3_IRLP_Mask;
|
||||
USARTx->CTLR3 |= USART_IrDAMode;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_IrDACmd
|
||||
*
|
||||
* @brief Enables or disables the USART's IrDA interface.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* NewState - ENABLE or DISABLE.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState)
|
||||
{
|
||||
if(NewState != DISABLE)
|
||||
{
|
||||
USARTx->CTLR3 |= CTLR3_IREN_Set;
|
||||
}
|
||||
else
|
||||
{
|
||||
USARTx->CTLR3 &= CTLR3_IREN_Reset;
|
||||
}
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_GetFlagStatus
|
||||
*
|
||||
* @brief Checks whether the specified USART flag is set or not.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* USART_FLAG - specifies the flag to check.
|
||||
* USART_FLAG_LBD - LIN Break detection flag.
|
||||
* USART_FLAG_TXE - Transmit data register empty flag.
|
||||
* USART_FLAG_TC - Transmission Complete flag.
|
||||
* USART_FLAG_RXNE - Receive data register not empty flag.
|
||||
* USART_FLAG_IDLE - Idle Line detection flag.
|
||||
* USART_FLAG_ORE - OverRun Error flag.
|
||||
* USART_FLAG_NE - Noise Error flag.
|
||||
* USART_FLAG_FE - Framing Error flag.
|
||||
* USART_FLAG_PE - Parity Error flag.
|
||||
*
|
||||
* @return bitstatus: SET or RESET
|
||||
*/
|
||||
FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG)
|
||||
{
|
||||
FlagStatus bitstatus = RESET;
|
||||
|
||||
if((USARTx->STATR & USART_FLAG) != (uint16_t)RESET)
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_ClearFlag
|
||||
*
|
||||
* @brief Clears the USARTx's pending flags.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* USART_FLAG - specifies the flag to clear.
|
||||
* USART_FLAG_LBD - LIN Break detection flag.
|
||||
* USART_FLAG_TC - Transmission Complete flag.
|
||||
* USART_FLAG_RXNE - Receive data register not empty flag.
|
||||
* Note-
|
||||
* - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
|
||||
* error) and IDLE (Idle line detected) flags are cleared by software
|
||||
* sequence: a read operation to USART_STATR register (USART_GetFlagStatus())
|
||||
* followed by a read operation to USART_DATAR register (USART_ReceiveData()).
|
||||
* - RXNE flag can be also cleared by a read to the USART_DATAR register
|
||||
* (USART_ReceiveData()).
|
||||
* - TC flag can be also cleared by software sequence: a read operation to
|
||||
* USART_STATR register (USART_GetFlagStatus()) followed by a write operation
|
||||
* to USART_DATAR register (USART_SendData()).
|
||||
* - TXE flag is cleared only by a write to the USART_DATAR register
|
||||
* (USART_SendData()).
|
||||
* @return none
|
||||
*/
|
||||
void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG)
|
||||
{
|
||||
|
||||
USARTx->STATR = (uint16_t)~USART_FLAG;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_GetITStatus
|
||||
*
|
||||
* @brief Checks whether the specified USART interrupt has occurred or not.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* USART_IT - specifies the USART interrupt source to check.
|
||||
* USART_IT_LBD - LIN Break detection interrupt.
|
||||
* USART_IT_TXE - Tansmit Data Register empty interrupt.
|
||||
* USART_IT_TC - Transmission complete interrupt.
|
||||
* USART_IT_RXNE - Receive Data register not empty interrupt.
|
||||
* USART_IT_IDLE - Idle line detection interrupt.
|
||||
* USART_IT_ORE_RX - OverRun Error interrupt if the RXNEIE bit is set.
|
||||
* USART_IT_ORE_ER - OverRun Error interrupt if the EIE bit is set.
|
||||
* USART_IT_NE - Noise Error interrupt.
|
||||
* USART_IT_FE - Framing Error interrupt.
|
||||
* USART_IT_PE - Parity Error interrupt.
|
||||
*
|
||||
* @return bitstatus: SET or RESET.
|
||||
*/
|
||||
ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT)
|
||||
{
|
||||
uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
|
||||
ITStatus bitstatus = RESET;
|
||||
|
||||
usartreg = (((uint8_t)USART_IT) >> 0x05);
|
||||
itmask = USART_IT & IT_Mask;
|
||||
itmask = (uint32_t)0x01 << itmask;
|
||||
|
||||
if(usartreg == 0x01)
|
||||
{
|
||||
itmask &= USARTx->CTLR1;
|
||||
}
|
||||
else if(usartreg == 0x02)
|
||||
{
|
||||
itmask &= USARTx->CTLR2;
|
||||
}
|
||||
else
|
||||
{
|
||||
itmask &= USARTx->CTLR3;
|
||||
}
|
||||
|
||||
bitpos = USART_IT >> 0x08;
|
||||
bitpos = (uint32_t)0x01 << bitpos;
|
||||
bitpos &= USARTx->STATR;
|
||||
|
||||
if((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET))
|
||||
{
|
||||
bitstatus = SET;
|
||||
}
|
||||
else
|
||||
{
|
||||
bitstatus = RESET;
|
||||
}
|
||||
|
||||
return bitstatus;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn USART_ClearITPendingBit
|
||||
*
|
||||
* @brief Clears the USARTx's interrupt pending bits.
|
||||
*
|
||||
* @param USARTx - where x can be 1, 2, 3 to select the USART peripheral.
|
||||
* USART_IT - specifies the interrupt pending bit to clear.
|
||||
* USART_IT_LBD - LIN Break detection interrupt.
|
||||
* USART_IT_TC - Transmission complete interrupt.
|
||||
* USART_IT_RXNE - Receive Data register not empty interrupt.
|
||||
* Note-
|
||||
* - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun
|
||||
* error) and IDLE (Idle line detected) pending bits are cleared by
|
||||
* software sequence: a read operation to USART_STATR register
|
||||
* (USART_GetITStatus()) followed by a read operation to USART_DATAR register
|
||||
* (USART_ReceiveData()).
|
||||
* - RXNE pending bit can be also cleared by a read to the USART_DATAR register
|
||||
* (USART_ReceiveData()).
|
||||
* - TC pending bit can be also cleared by software sequence: a read
|
||||
* operation to USART_STATR register (USART_GetITStatus()) followed by a write
|
||||
* operation to USART_DATAR register (USART_SendData()).
|
||||
* - TXE pending bit is cleared only by a write to the USART_DATAR register
|
||||
* (USART_SendData()).
|
||||
* @return none
|
||||
*/
|
||||
void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT)
|
||||
{
|
||||
uint16_t bitpos = 0x00, itmask = 0x00;
|
||||
|
||||
bitpos = USART_IT >> 0x08;
|
||||
itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
|
||||
USARTx->STATR = (uint16_t)~itmask;
|
||||
}
|
||||
185
mijia_haier_bridge/src/periph/ch32v10x_usart.h
Normal file
185
mijia_haier_bridge/src/periph/ch32v10x_usart.h
Normal file
@ -0,0 +1,185 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : ch32v10x_usart.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/01/30
|
||||
* Description : This file contains all the functions prototypes for the
|
||||
* USART firmware library.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __CH32V10x_USART_H
|
||||
#define __CH32V10x_USART_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "ch32v10x.h"
|
||||
|
||||
/* USART Init Structure definition */
|
||||
typedef struct
|
||||
{
|
||||
uint32_t USART_BaudRate; /* This member configures the USART communication baud rate.
|
||||
The baud rate is computed using the following formula:
|
||||
- IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate)))
|
||||
- FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */
|
||||
|
||||
uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame.
|
||||
This parameter can be a value of @ref USART_Word_Length */
|
||||
|
||||
uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted.
|
||||
This parameter can be a value of @ref USART_Stop_Bits */
|
||||
|
||||
uint16_t USART_Parity; /* Specifies the parity mode.
|
||||
This parameter can be a value of @ref USART_Parity
|
||||
@note When parity is enabled, the computed parity is inserted
|
||||
at the MSB position of the transmitted data (9th bit when
|
||||
the word length is set to 9 data bits; 8th bit when the
|
||||
word length is set to 8 data bits). */
|
||||
|
||||
uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled.
|
||||
This parameter can be a value of @ref USART_Mode */
|
||||
|
||||
uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled
|
||||
or disabled.
|
||||
This parameter can be a value of @ref USART_Hardware_Flow_Control */
|
||||
} USART_InitTypeDef;
|
||||
|
||||
/* USART Clock Init Structure definition */
|
||||
typedef struct
|
||||
{
|
||||
uint16_t USART_Clock; /* Specifies whether the USART clock is enabled or disabled.
|
||||
This parameter can be a value of @ref USART_Clock */
|
||||
|
||||
uint16_t USART_CPOL; /* Specifies the steady state value of the serial clock.
|
||||
This parameter can be a value of @ref USART_Clock_Polarity */
|
||||
|
||||
uint16_t USART_CPHA; /* Specifies the clock transition on which the bit capture is made.
|
||||
This parameter can be a value of @ref USART_Clock_Phase */
|
||||
|
||||
uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted
|
||||
data bit (MSB) has to be output on the SCLK pin in synchronous mode.
|
||||
This parameter can be a value of @ref USART_Last_Bit */
|
||||
} USART_ClockInitTypeDef;
|
||||
|
||||
/* USART_Word_Length */
|
||||
#define USART_WordLength_8b ((uint16_t)0x0000)
|
||||
#define USART_WordLength_9b ((uint16_t)0x1000)
|
||||
|
||||
/* USART_Stop_Bits */
|
||||
#define USART_StopBits_1 ((uint16_t)0x0000)
|
||||
#define USART_StopBits_0_5 ((uint16_t)0x1000)
|
||||
#define USART_StopBits_2 ((uint16_t)0x2000)
|
||||
#define USART_StopBits_1_5 ((uint16_t)0x3000)
|
||||
|
||||
/* USART_Parity */
|
||||
#define USART_Parity_No ((uint16_t)0x0000)
|
||||
#define USART_Parity_Even ((uint16_t)0x0400)
|
||||
#define USART_Parity_Odd ((uint16_t)0x0600)
|
||||
|
||||
/* USART_Mode */
|
||||
#define USART_Mode_Rx ((uint16_t)0x0004)
|
||||
#define USART_Mode_Tx ((uint16_t)0x0008)
|
||||
|
||||
/* USART_Hardware_Flow_Control */
|
||||
#define USART_HardwareFlowControl_None ((uint16_t)0x0000)
|
||||
#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100)
|
||||
#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200)
|
||||
#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300)
|
||||
|
||||
/* USART_Clock */
|
||||
#define USART_Clock_Disable ((uint16_t)0x0000)
|
||||
#define USART_Clock_Enable ((uint16_t)0x0800)
|
||||
|
||||
/* USART_Clock_Polarity */
|
||||
#define USART_CPOL_Low ((uint16_t)0x0000)
|
||||
#define USART_CPOL_High ((uint16_t)0x0400)
|
||||
|
||||
/* USART_Clock_Phase */
|
||||
#define USART_CPHA_1Edge ((uint16_t)0x0000)
|
||||
#define USART_CPHA_2Edge ((uint16_t)0x0200)
|
||||
|
||||
/* USART_Last_Bit */
|
||||
#define USART_LastBit_Disable ((uint16_t)0x0000)
|
||||
#define USART_LastBit_Enable ((uint16_t)0x0100)
|
||||
|
||||
/* USART_Interrupt_definition */
|
||||
#define USART_IT_PE ((uint16_t)0x0028)
|
||||
#define USART_IT_TXE ((uint16_t)0x0727)
|
||||
#define USART_IT_TC ((uint16_t)0x0626)
|
||||
#define USART_IT_RXNE ((uint16_t)0x0525)
|
||||
#define USART_IT_ORE_RX ((uint16_t)0x0325)
|
||||
#define USART_IT_IDLE ((uint16_t)0x0424)
|
||||
#define USART_IT_LBD ((uint16_t)0x0846)
|
||||
#define USART_IT_CTS ((uint16_t)0x096A)
|
||||
#define USART_IT_ERR ((uint16_t)0x0060)
|
||||
#define USART_IT_ORE_ER ((uint16_t)0x0360)
|
||||
#define USART_IT_NE ((uint16_t)0x0260)
|
||||
#define USART_IT_FE ((uint16_t)0x0160)
|
||||
|
||||
#define USART_IT_ORE USART_IT_ORE_ER
|
||||
|
||||
/* USART_DMA_Requests */
|
||||
#define USART_DMAReq_Tx ((uint16_t)0x0080)
|
||||
#define USART_DMAReq_Rx ((uint16_t)0x0040)
|
||||
|
||||
/* USART_WakeUp_methods */
|
||||
#define USART_WakeUp_IdleLine ((uint16_t)0x0000)
|
||||
#define USART_WakeUp_AddressMark ((uint16_t)0x0800)
|
||||
|
||||
/* USART_LIN_Break_Detection_Length */
|
||||
#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000)
|
||||
#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020)
|
||||
|
||||
/* USART_IrDA_Low_Power */
|
||||
#define USART_IrDAMode_LowPower ((uint16_t)0x0004)
|
||||
#define USART_IrDAMode_Normal ((uint16_t)0x0000)
|
||||
|
||||
/* USART_Flags */
|
||||
#define USART_FLAG_CTS ((uint16_t)0x0200)
|
||||
#define USART_FLAG_LBD ((uint16_t)0x0100)
|
||||
#define USART_FLAG_TXE ((uint16_t)0x0080)
|
||||
#define USART_FLAG_TC ((uint16_t)0x0040)
|
||||
#define USART_FLAG_RXNE ((uint16_t)0x0020)
|
||||
#define USART_FLAG_IDLE ((uint16_t)0x0010)
|
||||
#define USART_FLAG_ORE ((uint16_t)0x0008)
|
||||
#define USART_FLAG_NE ((uint16_t)0x0004)
|
||||
#define USART_FLAG_FE ((uint16_t)0x0002)
|
||||
#define USART_FLAG_PE ((uint16_t)0x0001)
|
||||
|
||||
void USART_DeInit(USART_TypeDef *USARTx);
|
||||
void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct);
|
||||
void USART_StructInit(USART_InitTypeDef *USART_InitStruct);
|
||||
void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct);
|
||||
void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct);
|
||||
void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState);
|
||||
void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState);
|
||||
void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
|
||||
void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address);
|
||||
void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp);
|
||||
void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState);
|
||||
void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength);
|
||||
void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState);
|
||||
void USART_SendData(USART_TypeDef *USARTx, uint16_t Data);
|
||||
uint16_t USART_ReceiveData(USART_TypeDef *USARTx);
|
||||
void USART_SendBreak(USART_TypeDef *USARTx);
|
||||
void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime);
|
||||
void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler);
|
||||
void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState);
|
||||
void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState);
|
||||
void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState);
|
||||
void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode);
|
||||
void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState);
|
||||
FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG);
|
||||
void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG);
|
||||
ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT);
|
||||
void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __CH32V10x_USART_H */
|
||||
52
mijia_haier_bridge/src/user/app_routines.c
Normal file
52
mijia_haier_bridge/src/user/app_routines.c
Normal file
@ -0,0 +1,52 @@
|
||||
#include "app_routines.h"
|
||||
#include "bsp_tick.h"
|
||||
#include "bsp_led.h"
|
||||
#include "bsp_buzzer.h"
|
||||
#include "bsp_module_io.h"
|
||||
#include "util_delay.h"
|
||||
#include "util_log.h"
|
||||
|
||||
void app_routine_relay_control(uint64_t tick);
|
||||
void app_routine_led_blink(uint64_t tick);
|
||||
|
||||
void app_routines_loop(void)
|
||||
{
|
||||
while (1) {
|
||||
uint64_t tick = bsp_tick_get();
|
||||
|
||||
app_routine_relay_control(tick);
|
||||
app_routine_led_blink(tick);
|
||||
}
|
||||
}
|
||||
|
||||
void app_routine_relay_control(uint64_t tick)
|
||||
{
|
||||
static uint64_t tick_last = 0;
|
||||
static uint8_t relay_stat_last = 0x00;
|
||||
|
||||
if (tick != tick_last) { //每tick执行一次
|
||||
uint8_t relay_stat = bsp_module_relay_read();
|
||||
|
||||
for (uint8_t i = 0; i < BSP_MODULE_RELAY_NUMBER; i ++) {
|
||||
uint8_t relay_bit_mask = 1 << i;
|
||||
if ((relay_stat & relay_bit_mask) != (relay_stat_last & relay_bit_mask)) {
|
||||
LOG_I("%s is turned %s", bsp_relay_index_to_string(relay_bit_mask), relay_stat & relay_bit_mask ? "on" : "off");
|
||||
}
|
||||
}
|
||||
|
||||
relay_stat_last = relay_stat;
|
||||
}
|
||||
|
||||
tick_last = tick;
|
||||
}
|
||||
|
||||
void app_routine_led_blink(uint64_t tick)
|
||||
{
|
||||
static uint64_t tick_last = 0;
|
||||
|
||||
if (tick % 500 == 0 && tick != tick_last) { //每500个tick执行一次
|
||||
bsp_led_toggle();
|
||||
}
|
||||
|
||||
tick_last = tick;
|
||||
}
|
||||
6
mijia_haier_bridge/src/user/app_routines.h
Normal file
6
mijia_haier_bridge/src/user/app_routines.h
Normal file
@ -0,0 +1,6 @@
|
||||
#ifndef __APP_ROUTINES_H
|
||||
#define __APP_ROUTINES_H
|
||||
|
||||
void app_routines_loop(void);
|
||||
|
||||
#endif
|
||||
66
mijia_haier_bridge/src/user/bsp_buzzer.c
Normal file
66
mijia_haier_bridge/src/user/bsp_buzzer.c
Normal file
@ -0,0 +1,66 @@
|
||||
#include "bsp_buzzer.h"
|
||||
#include "util_delay.h"
|
||||
|
||||
static const uint16_t note_frequency_table[] = {
|
||||
//Low do do# re re# mi fa fa# so so# ra ra# si
|
||||
1048, 1108, 1176, 1244, 1320, 1396, 1480, 1568, 1660, 1760, 1864, 1976,
|
||||
//Med do do# re re# mi fa fa# so so# ra ra# si
|
||||
2092, 2216, 2348, 2488, 2636, 2792, 2960, 3136, 3324, 3520, 3728, 3952,
|
||||
//High do do# re re# mi fa fa# so so# ra ra# si
|
||||
4184, 4436, 4700, 4980, 5272, 5588, 5920, 6272, 6644, 7040, 7456, 7904,
|
||||
};
|
||||
|
||||
void bsp_buzzer_init(void)
|
||||
{
|
||||
/* 开启GPIOB和TIM4时钟 */
|
||||
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM4, ENABLE);
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE);
|
||||
|
||||
/* 配置PB6为复用推挽输出 */
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_6;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure); //TIM4_CH1=PB6
|
||||
|
||||
/* 初始化定时器时基 */
|
||||
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
|
||||
TIM_TimeBaseStructInit(&TIM_TimeBaseStructure);
|
||||
TIM_TimeBaseStructure.TIM_Prescaler = 0;
|
||||
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
|
||||
TIM_TimeBaseStructure.TIM_Period = 1;
|
||||
TIM_TimeBaseInit(TIM4, &TIM_TimeBaseStructure);
|
||||
TIM_ARRPreloadConfig(TIM4, ENABLE);
|
||||
|
||||
/* 初始化定时器PWM输出 */
|
||||
TIM_OCInitTypeDef TIM_OCInitStructure;
|
||||
TIM_OCStructInit(&TIM_OCInitStructure);
|
||||
TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
|
||||
TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
|
||||
TIM_OCInitStructure.TIM_Pulse = 0; //关闭输出
|
||||
TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
|
||||
TIM_OC1Init(TIM4, &TIM_OCInitStructure);
|
||||
TIM_OC1PreloadConfig(TIM4, TIM_OCPreload_Enable);
|
||||
|
||||
TIM_Cmd(TIM4, ENABLE);
|
||||
}
|
||||
|
||||
void bsp_buzzer_play_note(bsp_buzzer_key key)
|
||||
{
|
||||
if (key != STOP) {
|
||||
TIM_PrescalerConfig(TIM4, SystemCoreClock / note_frequency_table[key] / 2, TIM_PSCReloadMode_Update);
|
||||
TIM_SetCompare1(TIM4, 1); //占空比为50%
|
||||
} else {
|
||||
TIM_SetCompare1(TIM4, 0);
|
||||
}
|
||||
}
|
||||
|
||||
void bsp_buzzer_play_song(const uint8_t *note_table, uint32_t note_count)
|
||||
{
|
||||
for (uint32_t i = 0; i < note_count; i ++) {
|
||||
bsp_buzzer_play_note(note_table[i * 2]);
|
||||
delay_ms(note_table[i * 2 + 1] * 8);
|
||||
}
|
||||
|
||||
bsp_buzzer_play_note(STOP);
|
||||
}
|
||||
20
mijia_haier_bridge/src/user/bsp_buzzer.h
Normal file
20
mijia_haier_bridge/src/user/bsp_buzzer.h
Normal file
@ -0,0 +1,20 @@
|
||||
#ifndef __BSP_BUZZER_H
|
||||
#define __BSP_BUZZER_H
|
||||
|
||||
#include "ch32v10x.h"
|
||||
|
||||
typedef enum {
|
||||
L1 = 0, LS1 = 1, L2 = 2, LS2 = 3, L3 = 4, L4 = 5,
|
||||
LS4 = 6, L5 = 7, LS5 = 8, L6 = 9, LS6 = 10, L7 = 11,
|
||||
M1 = 12, MS1 = 13, M2 = 14, MS2 = 15, M3 = 16, M4 = 17,
|
||||
MS4 = 18, M5 = 19, MS5 = 20, M6 = 21, MS6 = 22, M7 = 23,
|
||||
H1 = 24, HS1 = 25, H2 = 26, HS2 = 27, H3 = 28, H4 = 29,
|
||||
HS4 = 30, H5 = 31, HS5 = 32, H6 = 33, HS6 = 34, H7 = 35,
|
||||
BEEP = 36, STOP = 0xFF
|
||||
} bsp_buzzer_key;
|
||||
|
||||
void bsp_buzzer_init(void);
|
||||
void bsp_buzzer_play_note(bsp_buzzer_key key);
|
||||
void bsp_buzzer_play_song(const uint8_t *note_table, uint32_t note_count);
|
||||
|
||||
#endif
|
||||
122
mijia_haier_bridge/src/user/bsp_led.c
Normal file
122
mijia_haier_bridge/src/user/bsp_led.c
Normal file
@ -0,0 +1,122 @@
|
||||
#include "bsp_led.h"
|
||||
|
||||
static const uint16_t led_brightness_table[1001];
|
||||
|
||||
void bsp_led_init(void)
|
||||
{
|
||||
/* 开启GPIOA/B和TIM1时钟 */
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_TIM1, ENABLE);
|
||||
|
||||
/* 配置GPIO */
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure); //TIM1_CH1=PA8
|
||||
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP;
|
||||
GPIO_WriteBit(GPIOB, GPIO_InitStructure.GPIO_Pin, Bit_RESET);
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure); //LED=PB9
|
||||
|
||||
/* 初始化定时器时基 */
|
||||
TIM_TimeBaseInitTypeDef TIM_TimeBaseStructure;
|
||||
TIM_TimeBaseStructInit(&TIM_TimeBaseStructure);
|
||||
TIM_TimeBaseStructure.TIM_Prescaler = 3-1;
|
||||
TIM_TimeBaseStructure.TIM_CounterMode = TIM_CounterMode_Up;
|
||||
TIM_TimeBaseStructure.TIM_Period = 10000-1; //2.4kHz PWM
|
||||
TIM_TimeBaseInit(TIM1, &TIM_TimeBaseStructure);
|
||||
TIM_ARRPreloadConfig(TIM1, ENABLE);
|
||||
|
||||
/* 初始化定时器PWM输出 */
|
||||
TIM_OCInitTypeDef TIM_OCInitStructure;
|
||||
TIM_OCStructInit(&TIM_OCInitStructure);
|
||||
TIM_OCInitStructure.TIM_OCMode = TIM_OCMode_PWM1;
|
||||
TIM_OCInitStructure.TIM_OutputState = TIM_OutputState_Enable;
|
||||
TIM_OCInitStructure.TIM_Pulse = 0;
|
||||
TIM_OCInitStructure.TIM_OCPolarity = TIM_OCPolarity_High;
|
||||
TIM_OCInitStructure.TIM_OCIdleState = TIM_OCIdleState_Reset;
|
||||
TIM_OC1Init(TIM1, &TIM_OCInitStructure);
|
||||
TIM_OC1PreloadConfig(TIM1, TIM_OCPreload_Enable);
|
||||
|
||||
TIM_Cmd(TIM1, ENABLE);
|
||||
TIM_CtrlPWMOutputs(TIM1, ENABLE);
|
||||
}
|
||||
|
||||
void bsp_led_on(void)
|
||||
{
|
||||
GPIO_WriteBit(GPIOB, GPIO_Pin_9, Bit_SET);
|
||||
}
|
||||
|
||||
void bsp_led_off(void)
|
||||
{
|
||||
GPIO_WriteBit(GPIOB, GPIO_Pin_9, Bit_RESET);
|
||||
}
|
||||
|
||||
void bsp_led_toggle(void)
|
||||
{
|
||||
GPIO_WriteBit(GPIOB, GPIO_Pin_9, !GPIO_ReadOutputDataBit(GPIOB, GPIO_Pin_9));
|
||||
}
|
||||
|
||||
void bsp_led_strip_set_brightness(uint16_t brightness)
|
||||
{
|
||||
if (brightness > 1000) {
|
||||
brightness = 1000;
|
||||
}
|
||||
|
||||
TIM_SetCompare1(TIM1, led_brightness_table[brightness]);
|
||||
}
|
||||
|
||||
static const uint16_t led_brightness_table[1001] = { //指数亮度表 1000->10000
|
||||
0, 1, 2, 4, 6, 8, 10, 13, 15, 18, 21, 24, 27, 30, 33, 36, 40, 43, 47, 50, 54,
|
||||
57, 61, 65, 69, 73, 77, 80, 85, 89, 93, 97, 101, 105, 110, 114, 118, 123, 127, 132, 136,
|
||||
141, 145, 150, 155, 160, 164, 169, 174, 179, 184, 189, 194, 199, 204, 209, 214, 219, 224, 229, 234,
|
||||
240, 245, 250, 255, 261, 266, 272, 277, 283, 288, 293, 299, 305, 310, 316, 321, 327, 333, 338, 344,
|
||||
350, 356, 362, 367, 373, 379, 385, 391, 397, 403, 409, 415, 421, 427, 433, 439, 445, 451, 457, 464,
|
||||
470, 476, 482, 489, 495, 501, 507, 514, 520, 527, 533, 539, 546, 552, 559, 565, 572, 578, 585, 591,
|
||||
598, 605, 611, 618, 624, 631, 638, 645, 651, 658, 665, 672, 678, 685, 692, 699, 706, 713, 720, 726,
|
||||
733, 740, 747, 754, 761, 768, 775, 782, 789, 796, 804, 811, 818, 825, 832, 839, 846, 854, 861, 868,
|
||||
875, 883, 890, 897, 904, 912, 919, 926, 934, 941, 949, 956, 963, 971, 978, 986, 993, 1001, 1008, 1016,
|
||||
1023, 1031, 1038, 1046, 1054, 1061, 1069, 1076, 1084, 1092, 1099, 1107, 1115, 1123, 1130, 1138, 1146, 1154, 1161, 1169,
|
||||
1177, 1185, 1193, 1200, 1208, 1216, 1224, 1232, 1240, 1248, 1256, 1264, 1272, 1280, 1288, 1295, 1304, 1312, 1320, 1328,
|
||||
1336, 1344, 1352, 1360, 1368, 1376, 1384, 1392, 1401, 1409, 1417, 1425, 1433, 1441, 1450, 1458, 1466, 1474, 1483, 1491,
|
||||
1499, 1508, 1516, 1524, 1533, 1541, 1549, 1558, 1566, 1574, 1583, 1591, 1600, 1608, 1617, 1625, 1633, 1642, 1650, 1659,
|
||||
1667, 1676, 1685, 1693, 1702, 1710, 1719, 1727, 1736, 1745, 1753, 1762, 1770, 1779, 1788, 1796, 1805, 1814, 1823, 1831,
|
||||
1840, 1849, 1858, 1866, 1875, 1884, 1893, 1901, 1910, 1919, 1928, 1937, 1946, 1954, 1963, 1972, 1981, 1990, 1999, 2008,
|
||||
2017, 2026, 2035, 2044, 2053, 2062, 2071, 2080, 2089, 2098, 2107, 2116, 2125, 2134, 2143, 2152, 2161, 2170, 2179, 2188,
|
||||
2197, 2207, 2216, 2225, 2234, 2243, 2252, 2262, 2271, 2280, 2289, 2298, 2308, 2317, 2326, 2335, 2345, 2354, 2363, 2373,
|
||||
2382, 2391, 2400, 2410, 2419, 2429, 2438, 2447, 2457, 2466, 2475, 2485, 2494, 2504, 2513, 2523, 2532, 2542, 2551, 2560,
|
||||
2570, 2579, 2589, 2598, 2608, 2618, 2627, 2637, 2646, 2656, 2665, 2675, 2685, 2694, 2704, 2713, 2723, 2733, 2742, 2752,
|
||||
2762, 2771, 2781, 2791, 2800, 2810, 2820, 2829, 2839, 2849, 2859, 2868, 2878, 2888, 2898, 2907, 2917, 2927, 2937, 2947,
|
||||
2957, 2966, 2976, 2986, 2996, 3006, 3016, 3026, 3035, 3045, 3055, 3065, 3075, 3085, 3095, 3105, 3115, 3125, 3135, 3145,
|
||||
3155, 3165, 3175, 3185, 3195, 3205, 3215, 3225, 3235, 3245, 3255, 3265, 3275, 3285, 3295, 3306, 3316, 3326, 3336, 3346,
|
||||
3356, 3366, 3377, 3387, 3397, 3407, 3417, 3427, 3438, 3448, 3458, 3468, 3479, 3489, 3499, 3509, 3520, 3530, 3540, 3550,
|
||||
3561, 3571, 3581, 3592, 3602, 3612, 3623, 3633, 3643, 3654, 3664, 3674, 3685, 3695, 3706, 3716, 3726, 3737, 3747, 3758,
|
||||
3768, 3779, 3789, 3800, 3810, 3821, 3831, 3842, 3852, 3863, 3873, 3884, 3894, 3905, 3915, 3926, 3936, 3947, 3957, 3968,
|
||||
3979, 3989, 4000, 4010, 4021, 4032, 4042, 4053, 4064, 4074, 4085, 4095, 4106, 4117, 4128, 4138, 4149, 4160, 4170, 4181,
|
||||
4192, 4203, 4213, 4224, 4235, 4246, 4256, 4267, 4278, 4289, 4299, 4310, 4321, 4332, 4343, 4353, 4364, 4375, 4386, 4397,
|
||||
4408, 4419, 4429, 4440, 4451, 4462, 4473, 4484, 4495, 4506, 4517, 4528, 4539, 4550, 4560, 4571, 4582, 4593, 4604, 4615,
|
||||
4626, 4637, 4648, 4659, 4670, 4681, 4692, 4703, 4715, 4726, 4737, 4748, 4759, 4770, 4781, 4792, 4803, 4814, 4825, 4836,
|
||||
4848, 4859, 4870, 4881, 4892, 4903, 4914, 4926, 4937, 4948, 4959, 4970, 4982, 4993, 5004, 5015, 5026, 5038, 5049, 5060,
|
||||
5071, 5083, 5094, 5105, 5116, 5128, 5139, 5150, 5162, 5173, 5184, 5195, 5207, 5218, 5229, 5241, 5252, 5264, 5275, 5286,
|
||||
5298, 5309, 5320, 5332, 5343, 5355, 5366, 5377, 5389, 5400, 5412, 5423, 5435, 5446, 5457, 5469, 5480, 5492, 5503, 5515,
|
||||
5526, 5538, 5549, 5561, 5572, 5584, 5595, 5607, 5619, 5630, 5642, 5653, 5665, 5676, 5688, 5699, 5711, 5723, 5734, 5746,
|
||||
5757, 5769, 5781, 5792, 5804, 5816, 5827, 5839, 5851, 5862, 5874, 5886, 5897, 5909, 5921, 5932, 5944, 5956, 5967, 5979,
|
||||
5991, 6003, 6014, 6026, 6038, 6050, 6061, 6073, 6085, 6097, 6109, 6120, 6132, 6144, 6156, 6168, 6179, 6191, 6203, 6215,
|
||||
6227, 6239, 6250, 6262, 6274, 6286, 6298, 6310, 6322, 6333, 6345, 6357, 6369, 6381, 6393, 6405, 6417, 6429, 6441, 6453,
|
||||
6465, 6477, 6489, 6501, 6513, 6525, 6537, 6549, 6560, 6573, 6585, 6597, 6609, 6621, 6633, 6645, 6657, 6669, 6681, 6693,
|
||||
6705, 6717, 6729, 6741, 6753, 6765, 6777, 6789, 6802, 6814, 6826, 6838, 6850, 6862, 6874, 6886, 6899, 6911, 6923, 6935,
|
||||
6947, 6959, 6972, 6984, 6996, 7008, 7020, 7033, 7045, 7057, 7069, 7082, 7094, 7106, 7118, 7130, 7143, 7155, 7167, 7180,
|
||||
7192, 7204, 7216, 7229, 7241, 7253, 7266, 7278, 7290, 7303, 7315, 7327, 7340, 7352, 7364, 7377, 7389, 7401, 7414, 7426,
|
||||
7438, 7451, 7463, 7476, 7488, 7500, 7513, 7525, 7538, 7550, 7563, 7575, 7587, 7600, 7612, 7625, 7637, 7650, 7662, 7675,
|
||||
7687, 7700, 7712, 7725, 7737, 7750, 7762, 7775, 7787, 7800, 7812, 7825, 7837, 7850, 7862, 7875, 7888, 7900, 7913, 7925,
|
||||
7938, 7950, 7963, 7976, 7988, 8001, 8013, 8026, 8039, 8051, 8064, 8077, 8089, 8102, 8114, 8127, 8140, 8152, 8165, 8178,
|
||||
8191, 8203, 8216, 8229, 8241, 8254, 8267, 8279, 8292, 8305, 8318, 8330, 8343, 8356, 8369, 8381, 8394, 8407, 8420, 8432,
|
||||
8445, 8458, 8471, 8484, 8496, 8509, 8522, 8535, 8548, 8560, 8573, 8586, 8599, 8612, 8625, 8637, 8650, 8663, 8676, 8689,
|
||||
8702, 8715, 8728, 8740, 8753, 8766, 8779, 8792, 8805, 8818, 8831, 8844, 8857, 8870, 8883, 8895, 8908, 8921, 8934, 8947,
|
||||
8960, 8973, 8986, 8999, 9012, 9025, 9038, 9051, 9064, 9077, 9090, 9103, 9116, 9129, 9142, 9155, 9168, 9181, 9195, 9208,
|
||||
9221, 9234, 9247, 9260, 9273, 9286, 9299, 9312, 9325, 9338, 9352, 9365, 9378, 9391, 9404, 9417, 9430, 9443, 9457, 9470,
|
||||
9483, 9496, 9509, 9522, 9536, 9549, 9562, 9575, 9588, 9602, 9615, 9628, 9641, 9654, 9668, 9681, 9694, 9707, 9720, 9734,
|
||||
9747, 9760, 9773, 9787, 9800, 9813, 9827, 9840, 9853, 9866, 9880, 9893, 9906, 9920, 9933, 9946, 9960, 9973, 9986, 9999
|
||||
};
|
||||
12
mijia_haier_bridge/src/user/bsp_led.h
Normal file
12
mijia_haier_bridge/src/user/bsp_led.h
Normal file
@ -0,0 +1,12 @@
|
||||
#ifndef __BSP_LED_H
|
||||
#define __BSP_LED_H
|
||||
|
||||
#include "ch32v10x.h"
|
||||
|
||||
void bsp_led_init(void);
|
||||
void bsp_led_on(void);
|
||||
void bsp_led_off(void);
|
||||
void bsp_led_toggle(void);
|
||||
void bsp_led_strip_set_brightness(uint16_t brightness);
|
||||
|
||||
#endif
|
||||
115
mijia_haier_bridge/src/user/bsp_module_io.c
Normal file
115
mijia_haier_bridge/src/user/bsp_module_io.c
Normal file
@ -0,0 +1,115 @@
|
||||
#include "bsp_module_io.h"
|
||||
#include "util_log.h"
|
||||
|
||||
void bsp_module_io_init(void)
|
||||
{
|
||||
/* 开启GPIOA/B时钟 */
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB, ENABLE);
|
||||
|
||||
/* 配置GPIO */
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_OD;
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz;
|
||||
GPIO_WriteBit(GPIOA, GPIO_InitStructure.GPIO_Pin, Bit_SET);
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure); //MIJIA_KEY3=PA0 MIJIA_KEY2=PA1 MIJIA_KEY1=PA2
|
||||
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12;
|
||||
GPIO_WriteBit(GPIOB, GPIO_InitStructure.GPIO_Pin, Bit_SET);
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure); //MIJIA_KEY4=PB11 HAIER_KEY1=PB12
|
||||
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure); //MIJIA_RELAY1=PA3 MIJIA_RELAY2=PA4 MIJIA_RELAY3=PA5 MIJIA_RELAY4=PA6 MIJIA_BACKLIGHT=PA7
|
||||
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_13;
|
||||
GPIO_Init(GPIOB, &GPIO_InitStructure); //HAIER_RELAY1=PB13
|
||||
}
|
||||
|
||||
bsp_module_relay_t bsp_module_relay_read(void)
|
||||
{
|
||||
bsp_module_relay_t relay_stat = 0x00;
|
||||
|
||||
if (GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_3)) {
|
||||
relay_stat |= bsp_module_mijia_relay1;
|
||||
} else {
|
||||
relay_stat &= ~bsp_module_mijia_relay1;
|
||||
}
|
||||
|
||||
if (GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_4)) {
|
||||
relay_stat |= bsp_module_mijia_relay2;
|
||||
} else {
|
||||
relay_stat &= ~bsp_module_mijia_relay2;
|
||||
}
|
||||
|
||||
if (GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_5)) {
|
||||
relay_stat |= bsp_module_mijia_relay3;
|
||||
} else {
|
||||
relay_stat &= ~bsp_module_mijia_relay3;
|
||||
}
|
||||
|
||||
if (GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_6)) {
|
||||
relay_stat |= bsp_module_mijia_relay4;
|
||||
} else {
|
||||
relay_stat &= ~bsp_module_mijia_relay4;
|
||||
}
|
||||
|
||||
if (GPIO_ReadInputDataBit(GPIOA, GPIO_Pin_7)) {
|
||||
relay_stat |= bsp_module_mijia_backlight;
|
||||
} else {
|
||||
relay_stat &= ~bsp_module_mijia_backlight;
|
||||
}
|
||||
|
||||
if (GPIO_ReadInputDataBit(GPIOB, GPIO_Pin_13)) {
|
||||
relay_stat |= bsp_module_haier_relay1;
|
||||
} else {
|
||||
relay_stat &= ~bsp_module_haier_relay1;
|
||||
}
|
||||
|
||||
return relay_stat;
|
||||
}
|
||||
|
||||
void bsp_module_key_write(bsp_module_relay_t key, uint8_t pressed)
|
||||
{
|
||||
switch (key) {
|
||||
case bsp_module_mijia_relay1:
|
||||
GPIO_WriteBit(GPIOA, GPIO_Pin_2, pressed ? Bit_RESET : Bit_SET);
|
||||
return;
|
||||
case bsp_module_mijia_relay2:
|
||||
GPIO_WriteBit(GPIOA, GPIO_Pin_1, pressed ? Bit_RESET : Bit_SET);
|
||||
return;
|
||||
case bsp_module_mijia_relay3:
|
||||
GPIO_WriteBit(GPIOA, GPIO_Pin_0, pressed ? Bit_RESET : Bit_SET);
|
||||
return;
|
||||
case bsp_module_mijia_relay4:
|
||||
GPIO_WriteBit(GPIOB, GPIO_Pin_11, pressed ? Bit_RESET : Bit_SET);
|
||||
return;
|
||||
case bsp_module_haier_relay1:
|
||||
GPIO_WriteBit(GPIOB, GPIO_Pin_12, pressed ? Bit_RESET : Bit_SET);
|
||||
return;
|
||||
default:
|
||||
LOG_W("unknown relay index");
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
const char *bsp_relay_index_to_string(bsp_module_relay_t relay_stat)
|
||||
{
|
||||
switch (relay_stat) {
|
||||
case bsp_module_mijia_relay1:
|
||||
return "mijia relay1";
|
||||
case bsp_module_mijia_relay2:
|
||||
return "mijia relay2";
|
||||
case bsp_module_mijia_relay3:
|
||||
return "mijia relay3";
|
||||
case bsp_module_mijia_relay4:
|
||||
return "mijia relay4";
|
||||
case bsp_module_mijia_backlight:
|
||||
return "mijia backlight";
|
||||
case bsp_module_haier_relay1:
|
||||
return "haier relay1";
|
||||
default:
|
||||
LOG_W("unknown relay index");
|
||||
return "unknown";
|
||||
}
|
||||
}
|
||||
22
mijia_haier_bridge/src/user/bsp_module_io.h
Normal file
22
mijia_haier_bridge/src/user/bsp_module_io.h
Normal file
@ -0,0 +1,22 @@
|
||||
#ifndef __BSP_MODULE_IO_H
|
||||
#define __BSP_MODULE_IO_H
|
||||
|
||||
#include "ch32v10x.h"
|
||||
|
||||
typedef enum {
|
||||
bsp_module_mijia_relay1 = 1 << 0,
|
||||
bsp_module_mijia_relay2 = 1 << 1,
|
||||
bsp_module_mijia_relay3 = 1 << 2,
|
||||
bsp_module_mijia_relay4 = 1 << 3,
|
||||
bsp_module_mijia_backlight = 1 << 4,
|
||||
bsp_module_haier_relay1 = 1 << 5,
|
||||
} bsp_module_relay_t;
|
||||
|
||||
#define BSP_MODULE_RELAY_NUMBER 6
|
||||
|
||||
void bsp_module_io_init(void);
|
||||
bsp_module_relay_t bsp_module_relay_read(void);
|
||||
void bsp_module_key_write(bsp_module_relay_t key, uint8_t pressed);
|
||||
const char *bsp_relay_index_to_string(bsp_module_relay_t relay_stat);
|
||||
|
||||
#endif
|
||||
45
mijia_haier_bridge/src/user/bsp_tick.c
Normal file
45
mijia_haier_bridge/src/user/bsp_tick.c
Normal file
@ -0,0 +1,45 @@
|
||||
#include "bsp_tick.h"
|
||||
|
||||
static uint64_t tick = 0;
|
||||
|
||||
void TIM3_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||
|
||||
void bsp_tick_init(void)
|
||||
{
|
||||
RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE);
|
||||
|
||||
/* 初始化用于产生时基的定时器 */
|
||||
TIM_TimeBaseInitTypeDef TIM_TimeBaseInitStructure;
|
||||
TIM_TimeBaseInitStructure.TIM_Prescaler = SystemCoreClock / 1000000 - 1; //定时器时钟频率1MHz
|
||||
TIM_TimeBaseInitStructure.TIM_Period = 1000 - 1; //定时器更新频率1kHz
|
||||
TIM_TimeBaseInitStructure.TIM_ClockDivision = TIM_CKD_DIV1;
|
||||
TIM_TimeBaseInitStructure.TIM_CounterMode = TIM_CounterMode_Up;
|
||||
TIM_TimeBaseInit(TIM3, &TIM_TimeBaseInitStructure);
|
||||
|
||||
TIM_ClearITPendingBit(TIM3, TIM_IT_Update); //清除更新中断标志位
|
||||
TIM_ITConfig(TIM3, TIM_IT_Update, ENABLE); //允许更新中断
|
||||
|
||||
/* 配置定时器中断请求 */
|
||||
NVIC_InitTypeDef NVIC_InitStructure;
|
||||
NVIC_InitStructure.NVIC_IRQChannel = TIM3_IRQn;
|
||||
NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1;
|
||||
NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
|
||||
NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
|
||||
NVIC_Init(&NVIC_InitStructure);
|
||||
|
||||
TIM_Cmd(TIM3, ENABLE); //启动定时器
|
||||
}
|
||||
|
||||
uint64_t bsp_tick_get(void)
|
||||
{
|
||||
return tick;
|
||||
}
|
||||
|
||||
void TIM3_IRQHandler(void)
|
||||
{
|
||||
if (TIM_GetITStatus(TIM3, TIM_IT_Update) != RESET) {
|
||||
TIM_ClearITPendingBit(TIM3, TIM_IT_Update);
|
||||
|
||||
tick ++;
|
||||
}
|
||||
}
|
||||
9
mijia_haier_bridge/src/user/bsp_tick.h
Normal file
9
mijia_haier_bridge/src/user/bsp_tick.h
Normal file
@ -0,0 +1,9 @@
|
||||
#ifndef __BSP_TICK_H
|
||||
#define __BSP_TICK_H
|
||||
|
||||
#include "ch32v10x.h"
|
||||
|
||||
void bsp_tick_init(void);
|
||||
uint64_t bsp_tick_get(void);
|
||||
|
||||
#endif
|
||||
11
mijia_haier_bridge/src/user/ch32v10x_conf.h
Normal file
11
mijia_haier_bridge/src/user/ch32v10x_conf.h
Normal file
@ -0,0 +1,11 @@
|
||||
#ifndef __CH32V10x_CONF_H
|
||||
#define __CH32V10x_CONF_H
|
||||
|
||||
#include "ch32v10x_dma.h"
|
||||
#include "ch32v10x_gpio.h"
|
||||
#include "ch32v10x_rcc.h"
|
||||
#include "ch32v10x_tim.h"
|
||||
#include "ch32v10x_usart.h"
|
||||
#include "ch32v10x_misc.h"
|
||||
|
||||
#endif
|
||||
14
mijia_haier_bridge/src/user/ch32v10x_it.c
Normal file
14
mijia_haier_bridge/src/user/ch32v10x_it.c
Normal file
@ -0,0 +1,14 @@
|
||||
#include "ch32v10x.h"
|
||||
|
||||
void NMI_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||
void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast")));
|
||||
|
||||
void NMI_Handler(void)
|
||||
{
|
||||
while (1);
|
||||
}
|
||||
|
||||
void HardFault_Handler(void)
|
||||
{
|
||||
while (1);
|
||||
}
|
||||
26
mijia_haier_bridge/src/user/main.c
Normal file
26
mijia_haier_bridge/src/user/main.c
Normal file
@ -0,0 +1,26 @@
|
||||
#include "bsp_tick.h"
|
||||
#include "bsp_led.h"
|
||||
#include "bsp_buzzer.h"
|
||||
#include "bsp_module_io.h"
|
||||
#include "util_delay.h"
|
||||
#include "util_log.h"
|
||||
#include "app_routines.h"
|
||||
|
||||
int main(void)
|
||||
{
|
||||
NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1);
|
||||
SystemCoreClockUpdate();
|
||||
|
||||
delay_init();
|
||||
bsp_tick_init();
|
||||
log_init(921600);
|
||||
|
||||
bsp_led_init();
|
||||
bsp_buzzer_init();
|
||||
bsp_module_io_init();
|
||||
|
||||
LOG_I("executable compiled time: %s %s", __DATE__, __TIME__);
|
||||
LOG_I("system core clock: %d MHz", SystemCoreClock / 1000000);
|
||||
|
||||
app_routines_loop();
|
||||
}
|
||||
600
mijia_haier_bridge/src/user/system_ch32v10x.c
Normal file
600
mijia_haier_bridge/src/user/system_ch32v10x.c
Normal file
@ -0,0 +1,600 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : system_ch32v10x.c
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2024/06/23
|
||||
* Description : CH32V10x Device Peripheral Access Layer System Source File.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#include "ch32v10x.h"
|
||||
|
||||
/*
|
||||
* Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after
|
||||
* reset the HSI is used as SYSCLK source).
|
||||
* If none of the define below is enabled, the HSI is used as System clock source.
|
||||
*/
|
||||
//#define SYSCLK_FREQ_HSE HSE_VALUE
|
||||
//#define SYSCLK_FREQ_48MHz_HSE 48000000
|
||||
//#define SYSCLK_FREQ_56MHz_HSE 56000000
|
||||
#define SYSCLK_FREQ_72MHz_HSE 72000000
|
||||
//#define SYSCLK_FREQ_HSI HSI_VALUE
|
||||
//#define SYSCLK_FREQ_48MHz_HSI 48000000
|
||||
//#define SYSCLK_FREQ_56MHz_HSI 56000000
|
||||
//#define SYSCLK_FREQ_72MHz_HSI 72000000
|
||||
|
||||
/* Clock Definitions */
|
||||
#ifdef SYSCLK_FREQ_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSE
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSE; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSI
|
||||
uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSI; /* System Clock Frequency (Core Clock) */
|
||||
#else
|
||||
uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */
|
||||
|
||||
#endif
|
||||
|
||||
__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
|
||||
|
||||
/* ch32v10x_system_private_function_proto_types */
|
||||
static void SetSysClock(void);
|
||||
|
||||
#ifdef SYSCLK_FREQ_HSE
|
||||
static void SetSysClockToHSE( void );
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSE
|
||||
static void SetSysClockTo48_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSE
|
||||
static void SetSysClockTo56_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSE
|
||||
static void SetSysClockTo72_HSE( void );
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
static void SetSysClockTo48_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSI
|
||||
static void SetSysClockTo56_HSI( void );
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSI
|
||||
static void SetSysClockTo72_HSI( void );
|
||||
|
||||
#endif
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SystemInit
|
||||
*
|
||||
* @brief Setup the microcontroller system Initialize the Embedded Flash Interface,
|
||||
* the PLL and update the SystemCoreClock variable.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SystemInit(void)
|
||||
{
|
||||
RCC->CTLR |= (uint32_t)0x00000001;
|
||||
RCC->CFGR0 &= (uint32_t)0xF8FF0000;
|
||||
RCC->CTLR &= (uint32_t)0xFEF6FFFF;
|
||||
RCC->CTLR &= (uint32_t)0xFFFBFFFF;
|
||||
RCC->CFGR0 &= (uint32_t)0xFF80FFFF;
|
||||
RCC->INTR = 0x009F0000;
|
||||
SetSysClock();
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SystemCoreClockUpdate
|
||||
*
|
||||
* @brief Update SystemCoreClock variable according to Clock Register Values.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
void SystemCoreClockUpdate(void)
|
||||
{
|
||||
uint32_t tmp = 0, pllmull = 0, pllsource = 0;
|
||||
|
||||
tmp = RCC->CFGR0 & RCC_SWS;
|
||||
|
||||
switch(tmp)
|
||||
{
|
||||
case 0x00:
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
case 0x04:
|
||||
SystemCoreClock = HSE_VALUE;
|
||||
break;
|
||||
case 0x08:
|
||||
pllmull = RCC->CFGR0 & RCC_PLLMULL;
|
||||
pllsource = RCC->CFGR0 & RCC_PLLSRC;
|
||||
pllmull = (pllmull >> 18) + 2;
|
||||
if(pllsource == 0x00)
|
||||
{
|
||||
if( EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE )
|
||||
{
|
||||
SystemCoreClock = ( HSI_VALUE ) * pllmull;
|
||||
}
|
||||
else
|
||||
{
|
||||
SystemCoreClock = ( HSI_VALUE >> 1 ) * pllmull;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET)
|
||||
{
|
||||
SystemCoreClock = (HSE_VALUE >> 1) * pllmull;
|
||||
}
|
||||
else
|
||||
{
|
||||
SystemCoreClock = HSE_VALUE * pllmull;
|
||||
}
|
||||
}
|
||||
break;
|
||||
default:
|
||||
SystemCoreClock = HSI_VALUE;
|
||||
break;
|
||||
}
|
||||
|
||||
tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)];
|
||||
SystemCoreClock >>= tmp;
|
||||
}
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClock
|
||||
*
|
||||
* @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClock(void)
|
||||
{
|
||||
//GPIO_IPD_Unused();
|
||||
#ifdef SYSCLK_FREQ_HSE
|
||||
SetSysClockToHSE();
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSE
|
||||
SetSysClockTo48_HSE();
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSE
|
||||
SetSysClockTo56_HSE();
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSE
|
||||
SetSysClockTo72_HSE();
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
SetSysClockTo48_HSI();
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSI
|
||||
SetSysClockTo56_HSI();
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSI
|
||||
SetSysClockTo72_HSI();
|
||||
|
||||
#endif
|
||||
|
||||
/* If none of the define above is enabled, the HSI is used as System clock
|
||||
* source (default after reset)
|
||||
*/
|
||||
}
|
||||
|
||||
#ifdef SYSCLK_FREQ_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockToHSE
|
||||
*
|
||||
* @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockToHSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if(HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
|
||||
/* Flash 0 wait state */
|
||||
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
|
||||
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1;
|
||||
|
||||
/* Select HSE as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_HSE;
|
||||
|
||||
/* Wait till HSE is used as system clock source */
|
||||
while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo48_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo48_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if(HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* Enable Prefetch Buffer */
|
||||
FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
|
||||
|
||||
/* Flash 1 wait state */
|
||||
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
|
||||
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL6);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo56_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo56_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if(HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* Enable Prefetch Buffer */
|
||||
FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
|
||||
|
||||
/* Flash 2 wait state */
|
||||
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
|
||||
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL7);
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSE
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo72_HSE
|
||||
*
|
||||
* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo72_HSE(void)
|
||||
{
|
||||
__IO uint32_t StartUpCounter = 0, HSEStatus = 0;
|
||||
|
||||
RCC->CTLR |= ((uint32_t)RCC_HSEON);
|
||||
|
||||
/* Wait till HSE is ready and if Time out is reached exit */
|
||||
do
|
||||
{
|
||||
HSEStatus = RCC->CTLR & RCC_HSERDY;
|
||||
StartUpCounter++;
|
||||
} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
|
||||
|
||||
if((RCC->CTLR & RCC_HSERDY) != RESET)
|
||||
{
|
||||
HSEStatus = (uint32_t)0x01;
|
||||
}
|
||||
else
|
||||
{
|
||||
HSEStatus = (uint32_t)0x00;
|
||||
}
|
||||
|
||||
if(HSEStatus == (uint32_t)0x01)
|
||||
{
|
||||
/* Enable Prefetch Buffer */
|
||||
FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
|
||||
|
||||
/* Flash 2 wait state */
|
||||
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
|
||||
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE |
|
||||
RCC_PLLMULL));
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL9);
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/*
|
||||
* If HSE fails to start-up, the application will have wrong clock
|
||||
* configuration. User can add here some code to deal with this error
|
||||
*/
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_48MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo48_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo48_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* Enable Prefetch Buffer */
|
||||
FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
|
||||
|
||||
/* Flash 1 wait state */
|
||||
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
|
||||
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 6 = 48 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_56MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo56_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo56_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* Enable Prefetch Buffer */
|
||||
FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
|
||||
|
||||
/* Flash 2 wait state */
|
||||
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
|
||||
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 7 = 56 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
#elif defined SYSCLK_FREQ_72MHz_HSI
|
||||
|
||||
/*********************************************************************
|
||||
* @fn SetSysClockTo72_HSI
|
||||
*
|
||||
* @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers.
|
||||
*
|
||||
* @return none
|
||||
*/
|
||||
static void SetSysClockTo72_HSI(void)
|
||||
{
|
||||
EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE;
|
||||
|
||||
/* Enable Prefetch Buffer */
|
||||
FLASH->ACTLR |= FLASH_ACTLR_PRFTBE;
|
||||
|
||||
/* Flash 2 wait state */
|
||||
FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY);
|
||||
FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2;
|
||||
|
||||
/* HCLK = SYSCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1;
|
||||
/* PCLK2 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1;
|
||||
/* PCLK1 = HCLK */
|
||||
RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2;
|
||||
|
||||
/* PLL configuration: PLLCLK = HSI * 9 = 72 MHz */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL));
|
||||
RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9);
|
||||
|
||||
/* Enable PLL */
|
||||
RCC->CTLR |= RCC_PLLON;
|
||||
/* Wait till PLL is ready */
|
||||
while((RCC->CTLR & RCC_PLLRDY) == 0)
|
||||
{
|
||||
}
|
||||
/* Select PLL as system clock source */
|
||||
RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW));
|
||||
RCC->CFGR0 |= (uint32_t)RCC_SW_PLL;
|
||||
/* Wait till PLL is used as system clock source */
|
||||
while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08)
|
||||
{
|
||||
}
|
||||
}
|
||||
|
||||
#endif
|
||||
29
mijia_haier_bridge/src/user/system_ch32v10x.h
Normal file
29
mijia_haier_bridge/src/user/system_ch32v10x.h
Normal file
@ -0,0 +1,29 @@
|
||||
/********************************** (C) COPYRIGHT *******************************
|
||||
* File Name : system_ch32v10x.h
|
||||
* Author : WCH
|
||||
* Version : V1.0.0
|
||||
* Date : 2020/04/30
|
||||
* Description : CH32V10x Device Peripheral Access Layer System Header File.
|
||||
*********************************************************************************
|
||||
* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd.
|
||||
* Attention: This software (modified or not) and binary are used for
|
||||
* microcontroller manufactured by Nanjing Qinheng Microelectronics.
|
||||
*******************************************************************************/
|
||||
#ifndef __SYSTEM_CH32V10x_H
|
||||
#define __SYSTEM_CH32V10x_H
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */
|
||||
|
||||
/* System_Exported_Functions */
|
||||
extern void SystemInit(void);
|
||||
extern void SystemCoreClockUpdate(void);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /*__CH32V10x_SYSTEM_H */
|
||||
38
mijia_haier_bridge/src/user/util_delay.c
Normal file
38
mijia_haier_bridge/src/user/util_delay.c
Normal file
@ -0,0 +1,38 @@
|
||||
#include "util_delay.h"
|
||||
|
||||
static uint8_t p_us = 0;
|
||||
static uint16_t p_ms = 0;
|
||||
|
||||
void delay_init(void)
|
||||
{
|
||||
p_us = SystemCoreClock / 8000000;
|
||||
p_ms = (uint16_t)p_us * 1000;
|
||||
}
|
||||
|
||||
void delay_us(uint32_t n_us)
|
||||
{
|
||||
SysTick->CNTL0 = 0;
|
||||
SysTick->CNTL1 = 0;
|
||||
SysTick->CNTL2 = 0;
|
||||
SysTick->CNTL3 = 0;
|
||||
SysTick->CTLR = 1;
|
||||
|
||||
uint32_t i = (uint32_t)n_us * p_us;
|
||||
while((*(volatile uint32_t *)&SysTick->CNTL0) <= i);
|
||||
|
||||
SysTick->CTLR = 0;
|
||||
}
|
||||
|
||||
void delay_ms(uint32_t n_ms)
|
||||
{
|
||||
SysTick->CNTL0 = 0;
|
||||
SysTick->CNTL1 = 0;
|
||||
SysTick->CNTL2 = 0;
|
||||
SysTick->CNTL3 = 0;
|
||||
SysTick->CTLR = 1;
|
||||
|
||||
uint32_t i = (uint32_t)n_ms * p_ms;
|
||||
while((*(volatile uint32_t *)&SysTick->CNTL0) <= i);
|
||||
|
||||
SysTick->CTLR = 0;
|
||||
}
|
||||
10
mijia_haier_bridge/src/user/util_delay.h
Normal file
10
mijia_haier_bridge/src/user/util_delay.h
Normal file
@ -0,0 +1,10 @@
|
||||
#ifndef __UTIL_DELAY_H
|
||||
#define __UTIL_DELAY_H
|
||||
|
||||
#include "ch32v10x.h"
|
||||
|
||||
void delay_init(void);
|
||||
void delay_us(uint32_t n);
|
||||
void delay_ms(uint32_t n);
|
||||
|
||||
#endif
|
||||
77
mijia_haier_bridge/src/user/util_log.c
Normal file
77
mijia_haier_bridge/src/user/util_log.c
Normal file
@ -0,0 +1,77 @@
|
||||
#include "util_log.h"
|
||||
#include <stdio.h>
|
||||
#include <stdarg.h>
|
||||
|
||||
static char string_buffer[256];
|
||||
|
||||
/**
|
||||
* @brief 初始化日志打印
|
||||
*
|
||||
*/
|
||||
void log_init(uint32_t baudrate)
|
||||
{
|
||||
/* 开启时钟 */
|
||||
RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE);
|
||||
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE);
|
||||
|
||||
/* 配置GPIO */
|
||||
GPIO_InitTypeDef GPIO_InitStructure;
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; //USART1_TX=PA9
|
||||
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
|
||||
GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; //USART1_RX=PA10
|
||||
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU;
|
||||
GPIO_Init(GPIOA, &GPIO_InitStructure);
|
||||
|
||||
/* 初始化串口外设 */
|
||||
USART_InitTypeDef USART_InitStructure;
|
||||
USART_InitStructure.USART_BaudRate = baudrate;
|
||||
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
|
||||
USART_InitStructure.USART_StopBits = USART_StopBits_1;
|
||||
USART_InitStructure.USART_Parity = USART_Parity_No;
|
||||
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
|
||||
USART_InitStructure.USART_Mode = USART_Mode_Tx | USART_Mode_Rx;
|
||||
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
|
||||
USART_Init(USART1, &USART_InitStructure);
|
||||
USART_DMACmd(USART1, USART_DMAReq_Tx, ENABLE); //使能UART1的DMA发送
|
||||
|
||||
/* 配置DMA通道 */
|
||||
DMA_InitTypeDef DMA_InitStructure;
|
||||
DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&USART1->DATAR; //USART1数据寄存器地址
|
||||
DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)string_buffer; //数据缓冲区地址
|
||||
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST; //外设->内存方向
|
||||
DMA_InitStructure.DMA_BufferSize = 0; //缓冲区大小
|
||||
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; //外设地址不自增
|
||||
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; //内存地址自增
|
||||
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; //外设数据大小：字节
|
||||
DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; //内存数据大小：字节
|
||||
DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; //普通模式
|
||||
DMA_InitStructure.DMA_Priority = DMA_Priority_Medium; //中优先级
|
||||
DMA_InitStructure.DMA_M2M = DMA_M2M_Disable; //非内存到内存传输
|
||||
DMA_Init(DMA1_Channel4, &DMA_InitStructure);
|
||||
|
||||
USART_Cmd(USART1, ENABLE); //使能串口
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief 使用串口打印日志
|
||||
*
|
||||
* @param fmt 格式化字符串
|
||||
* @param ... 可变参数
|
||||
* @note 本函数将格式化字符串至静态内存，并将其拷贝到发送缓冲区中。若当前未在发送，则启动一次发送
|
||||
*/
|
||||
void log_uart_printf(const char *fmt, ...)
|
||||
{
|
||||
while (DMA_GetCurrDataCounter(DMA1_Channel4) != 0); //等待上次传输完成
|
||||
|
||||
va_list va_args;
|
||||
va_start(va_args, fmt);
|
||||
int length = vsnprintf(string_buffer, sizeof(string_buffer), fmt, va_args);
|
||||
va_end(va_args);
|
||||
|
||||
DMA_Cmd(DMA1_Channel4, DISABLE); //禁用DMA通道4
|
||||
DMA_SetCurrDataCounter(DMA1_Channel4, length); //设置DMA传输数据长度
|
||||
DMA_Cmd(DMA1_Channel4, ENABLE); //使能DMA通道4，开始发送
|
||||
}
|
||||
42
mijia_haier_bridge/src/user/util_log.h
Normal file
42
mijia_haier_bridge/src/user/util_log.h
Normal file
@ -0,0 +1,42 @@
|
||||
#ifndef __UTIL_LOG_H
|
||||
#define __UTIL_LOG_H
|
||||
|
||||
#include "ch32v10x.h"
|
||||
#include "bsp_tick.h"
|
||||
|
||||
#define CSI_START "\033["
|
||||
#define CSI_END "\033[0m"
|
||||
/* output log front color */
|
||||
#define F_BLACK "30;"
|
||||
#define F_RED "31;"
|
||||
#define F_GREEN "32;"
|
||||
#define F_YELLOW "33;"
|
||||
#define F_BLUE "34;"
|
||||
#define F_MAGENTA "35;"
|
||||
#define F_CYAN "36;"
|
||||
#define F_WHITE "37;"
|
||||
/* output log background color */
|
||||
#define B_NULL
|
||||
#define B_BLACK "40;"
|
||||
#define B_RED "41;"
|
||||
#define B_GREEN "42;"
|
||||
#define B_YELLOW "43;"
|
||||
#define B_BLUE "44;"
|
||||
#define B_MAGENTA "45;"
|
||||
#define B_CYAN "46;"
|
||||
#define B_WHITE "47;"
|
||||
/* output log fonts style */
|
||||
#define S_BOLD "1m"
|
||||
#define S_UNDERLINE "4m"
|
||||
#define S_BLINK "5m"
|
||||
#define S_NORMAL "22m"
|
||||
|
||||
#define LOG_E(format, ...) log_uart_printf(CSI_START F_RED S_NORMAL "E/%s(%llu): " format CSI_END "\n", __func__, bsp_tick_get(), ##__VA_ARGS__)
|
||||
#define LOG_W(format, ...) log_uart_printf(CSI_START F_YELLOW S_NORMAL "W/%s(%llu): " format CSI_END "\n", __func__, bsp_tick_get(), ##__VA_ARGS__)
|
||||
#define LOG_I(format, ...) log_uart_printf(CSI_START F_GREEN S_NORMAL "I/%s(%llu): " format CSI_END "\n", __func__, bsp_tick_get(), ##__VA_ARGS__)
|
||||
#define LOG_D(format, ...) log_uart_printf(CSI_START F_CYAN S_NORMAL "D/%s(%llu): " format CSI_END "\n", __func__, bsp_tick_get(), ##__VA_ARGS__)
|
||||
|
||||
void log_init(uint32_t baudrate);
|
||||
void log_uart_printf(const char *fmt, ...);
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user