From 3d35b132f2102e5679fbbdc970a9634d630d2d27 Mon Sep 17 00:00:00 2001 From: wangyz1997 Date: Wed, 30 Apr 2025 22:33:44 +0800 Subject: [PATCH] ch32v103_hallarray_controller: add project --- ch32v103_hallarray_controller/.cproject | 150 + ch32v103_hallarray_controller/.project | 34 + ch32v103_hallarray_controller/.template | 18 + .../3rdparty/CherryUSB/class/cdc/usb_cdc.h | 698 ++++ .../3rdparty/CherryUSB/class/cdc/usbd_cdc.h | 13 + .../CherryUSB/class/cdc/usbd_cdc_acm.c | 134 + .../CherryUSB/class/cdc/usbd_cdc_acm.h | 29 + .../CherryUSB/class/cdc/usbd_cdc_ecm.c | 284 ++ .../CherryUSB/class/cdc/usbd_cdc_ecm.h | 36 + .../3rdparty/CherryUSB/class/hid/usb_hid.h | 669 ++++ .../3rdparty/CherryUSB/class/hid/usbd_hid.c | 126 + .../3rdparty/CherryUSB/class/hid/usbd_hid.h | 34 + .../3rdparty/CherryUSB/common/usb_dc.h | 204 ++ .../3rdparty/CherryUSB/common/usb_dcache.h | 19 + .../3rdparty/CherryUSB/common/usb_def.h | 724 ++++ .../3rdparty/CherryUSB/common/usb_errno.h | 24 + .../3rdparty/CherryUSB/common/usb_hc.h | 118 + .../3rdparty/CherryUSB/common/usb_list.h | 459 +++ .../3rdparty/CherryUSB/common/usb_log.h | 114 + .../3rdparty/CherryUSB/common/usb_memcpy.h | 91 + .../3rdparty/CherryUSB/common/usb_osal.h | 72 + .../3rdparty/CherryUSB/common/usb_otg.h | 41 + .../3rdparty/CherryUSB/common/usb_util.h | 218 ++ .../3rdparty/CherryUSB/common/usb_version.h | 21 + .../3rdparty/CherryUSB/core/usbd_core.c | 1527 ++++++++ .../3rdparty/CherryUSB/core/usbd_core.h | 116 + .../port/ch32v103/usb_ch32v1_usbfs_reg.h | 246 ++ .../port/ch32v103/usb_dc_ch32v1_usbfs.c | 412 +++ .../ch32v103_hallarray_controller.wvproj | Bin 0 -> 202 bytes .../src/core/core_riscv.c | 303 ++ .../src/core/core_riscv.h | 629 ++++ .../src/core/ld_ch32v10x.ld | 1 + .../src/core/startup_ch32v10x.S | 237 ++ .../src/periph/ch32v10x.h | 3209 +++++++++++++++++ .../src/periph/ch32v10x_adc.c | 1147 ++++++ .../src/periph/ch32v10x_adc.h | 190 + .../src/periph/ch32v10x_dma.c | 552 +++ .../src/periph/ch32v10x_dma.h | 218 ++ .../src/periph/ch32v10x_gpio.c | 578 +++ .../src/periph/ch32v10x_gpio.h | 161 + .../src/periph/ch32v10x_misc.c | 87 + .../src/periph/ch32v10x_misc.h | 70 + .../src/periph/ch32v10x_rcc.c | 950 +++++ .../src/periph/ch32v10x_rcc.h | 230 ++ .../src/periph/ch32v10x_tim.c | 2355 ++++++++++++ .../src/periph/ch32v10x_tim.h | 508 +++ .../src/periph/ch32v10x_usart.c | 747 ++++ .../src/periph/ch32v10x_usart.h | 185 + .../src/user/app_main.c | 151 + .../src/user/app_main.h | 8 + .../src/user/app_usb_cdc.c | 208 ++ .../src/user/app_usb_cdc.h | 22 + .../src/user/bsp_adc1.c | 172 + .../src/user/bsp_adc1.h | 15 + .../src/user/bsp_led_key.c | 53 + .../src/user/bsp_led_key.h | 15 + .../src/user/bsp_uart1.c | 65 + .../src/user/bsp_uart1.h | 9 + .../src/user/ch32v10x_conf.h | 12 + .../src/user/ch32v10x_it.c | 8 + ch32v103_hallarray_controller/src/user/main.c | 9 + .../src/user/system_ch32v10x.c | 600 +++ .../src/user/system_ch32v10x.h | 29 + .../src/user/usb_config.h | 21 + .../src/user/util_delay.c | 38 + .../src/user/util_delay.h | 10 + 66 files changed, 20433 insertions(+) create mode 100644 ch32v103_hallarray_controller/.cproject create mode 100644 ch32v103_hallarray_controller/.project create mode 100644 ch32v103_hallarray_controller/.template create mode 100644 ch32v103_hallarray_controller/3rdparty/CherryUSB/class/cdc/usb_cdc.h create mode 100644 ch32v103_hallarray_controller/3rdparty/CherryUSB/class/cdc/usbd_cdc.h create mode 100644 ch32v103_hallarray_controller/3rdparty/CherryUSB/class/cdc/usbd_cdc_acm.c create mode 100644 ch32v103_hallarray_controller/3rdparty/CherryUSB/class/cdc/usbd_cdc_acm.h create mode 100644 ch32v103_hallarray_controller/3rdparty/CherryUSB/class/cdc/usbd_cdc_ecm.c create mode 100644 ch32v103_hallarray_controller/3rdparty/CherryUSB/class/cdc/usbd_cdc_ecm.h create mode 100644 ch32v103_hallarray_controller/3rdparty/CherryUSB/class/hid/usb_hid.h create mode 100644 ch32v103_hallarray_controller/3rdparty/CherryUSB/class/hid/usbd_hid.c create mode 100644 ch32v103_hallarray_controller/3rdparty/CherryUSB/class/hid/usbd_hid.h create mode 100644 ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_dc.h create mode 100644 ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_dcache.h create mode 100644 ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_def.h create mode 100644 ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_errno.h create mode 100644 ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_hc.h create mode 100644 ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_list.h create mode 100644 ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_log.h create mode 100644 ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_memcpy.h create mode 100644 ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_osal.h create mode 100644 ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_otg.h create mode 100644 ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_util.h create mode 100644 ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_version.h create mode 100644 ch32v103_hallarray_controller/3rdparty/CherryUSB/core/usbd_core.c create mode 100644 ch32v103_hallarray_controller/3rdparty/CherryUSB/core/usbd_core.h create mode 100644 ch32v103_hallarray_controller/3rdparty/CherryUSB/port/ch32v103/usb_ch32v1_usbfs_reg.h create mode 100644 ch32v103_hallarray_controller/3rdparty/CherryUSB/port/ch32v103/usb_dc_ch32v1_usbfs.c create mode 100644 ch32v103_hallarray_controller/ch32v103_hallarray_controller.wvproj create mode 100644 ch32v103_hallarray_controller/src/core/core_riscv.c create mode 100644 ch32v103_hallarray_controller/src/core/core_riscv.h create mode 100644 ch32v103_hallarray_controller/src/core/ld_ch32v10x.ld create mode 100644 ch32v103_hallarray_controller/src/core/startup_ch32v10x.S create mode 100644 ch32v103_hallarray_controller/src/periph/ch32v10x.h create mode 100644 ch32v103_hallarray_controller/src/periph/ch32v10x_adc.c create mode 100644 ch32v103_hallarray_controller/src/periph/ch32v10x_adc.h create mode 100644 ch32v103_hallarray_controller/src/periph/ch32v10x_dma.c create mode 100644 ch32v103_hallarray_controller/src/periph/ch32v10x_dma.h create mode 100644 ch32v103_hallarray_controller/src/periph/ch32v10x_gpio.c create mode 100644 ch32v103_hallarray_controller/src/periph/ch32v10x_gpio.h create mode 100644 ch32v103_hallarray_controller/src/periph/ch32v10x_misc.c create mode 100644 ch32v103_hallarray_controller/src/periph/ch32v10x_misc.h create mode 100644 ch32v103_hallarray_controller/src/periph/ch32v10x_rcc.c create mode 100644 ch32v103_hallarray_controller/src/periph/ch32v10x_rcc.h create mode 100644 ch32v103_hallarray_controller/src/periph/ch32v10x_tim.c create mode 100644 ch32v103_hallarray_controller/src/periph/ch32v10x_tim.h create mode 100644 ch32v103_hallarray_controller/src/periph/ch32v10x_usart.c create mode 100644 ch32v103_hallarray_controller/src/periph/ch32v10x_usart.h create mode 100644 ch32v103_hallarray_controller/src/user/app_main.c create mode 100644 ch32v103_hallarray_controller/src/user/app_main.h create mode 100644 ch32v103_hallarray_controller/src/user/app_usb_cdc.c create mode 100644 ch32v103_hallarray_controller/src/user/app_usb_cdc.h create mode 100644 ch32v103_hallarray_controller/src/user/bsp_adc1.c create mode 100644 ch32v103_hallarray_controller/src/user/bsp_adc1.h create mode 100644 ch32v103_hallarray_controller/src/user/bsp_led_key.c create mode 100644 ch32v103_hallarray_controller/src/user/bsp_led_key.h create mode 100644 ch32v103_hallarray_controller/src/user/bsp_uart1.c create mode 100644 ch32v103_hallarray_controller/src/user/bsp_uart1.h create mode 100644 ch32v103_hallarray_controller/src/user/ch32v10x_conf.h create mode 100644 ch32v103_hallarray_controller/src/user/ch32v10x_it.c create mode 100644 ch32v103_hallarray_controller/src/user/main.c create mode 100644 ch32v103_hallarray_controller/src/user/system_ch32v10x.c create mode 100644 ch32v103_hallarray_controller/src/user/system_ch32v10x.h create mode 100644 ch32v103_hallarray_controller/src/user/usb_config.h create mode 100644 ch32v103_hallarray_controller/src/user/util_delay.c create mode 100644 ch32v103_hallarray_controller/src/user/util_delay.h diff --git a/ch32v103_hallarray_controller/.cproject b/ch32v103_hallarray_controller/.cproject new file mode 100644 index 0000000..f6635b3 --- /dev/null +++ b/ch32v103_hallarray_controller/.cproject @@ -0,0 +1,150 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/ch32v103_hallarray_controller/.project b/ch32v103_hallarray_controller/.project new file mode 100644 index 0000000..4c55db6 --- /dev/null +++ b/ch32v103_hallarray_controller/.project @@ -0,0 +1,34 @@ + + + ch32v103_hallarray_controller + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + 1595986042669 + + 22 + + org.eclipse.ui.ide.multiFilter + 1.0-name-matches-false-false-*.wvproj + + + + diff --git a/ch32v103_hallarray_controller/.template b/ch32v103_hallarray_controller/.template new file mode 100644 index 0000000..22aeab9 --- /dev/null +++ b/ch32v103_hallarray_controller/.template @@ -0,0 +1,18 @@ +Vendor=WCH +Toolchain=RISC-V +Series=CH32L103 +RTOS=NoneOS +MCU=CH32V103R8T6 +Link=WCH-Link +PeripheralVersion======1.0 +Description====== +Mcu Type=CH32V10x +Address=0x08000000 +Target Path=build\ch32v103_hallarray_controller.hex +CLKSpeed=1 +DebugInterfaceMode=-1 +Erase All=true +Program=true +Verify=true +Reset=true +SDIPrintf=false diff --git a/ch32v103_hallarray_controller/3rdparty/CherryUSB/class/cdc/usb_cdc.h b/ch32v103_hallarray_controller/3rdparty/CherryUSB/class/cdc/usb_cdc.h new file mode 100644 index 0000000..d1546ee --- /dev/null +++ b/ch32v103_hallarray_controller/3rdparty/CherryUSB/class/cdc/usb_cdc.h @@ -0,0 +1,698 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_CDC_H +#define USB_CDC_H + +/*------------------------------------------------------------------------------ + * Definitions based on usbcdc11.pdf (www.usb.org) + *----------------------------------------------------------------------------*/ +/* Communication device class specification version 1.10 */ +#define CDC_V1_10 0x0110U +// Communication device class specification version 1.2 +#define CDC_V1_2_0 0x0120U + +/* Communication interface class code */ +/* (usbcdc11.pdf, 4.2, Table 15) */ +#define CDC_COMMUNICATION_INTERFACE_CLASS 0x02U + +/* Communication interface class subclass codes */ +/* (usbcdc11.pdf, 4.3, Table 16) */ +#define CDC_SUBCLASS_NONE 0x00 /* Reserved */ +#define CDC_SUBCLASS_DLC 0x01 /* Direct Line Control Model */ +#define CDC_SUBCLASS_ACM 0x02 /* Abstract Control Model */ +#define CDC_SUBCLASS_TCM 0x03 /* Telephone Control Model */ +#define CDC_SUBCLASS_MCM 0x04 /* Multi-Channel Control Model */ +#define CDC_SUBCLASS_CAPI 0x05 /* CAPI Control Model */ +#define CDC_SUBCLASS_ECM 0x06 /* Ethernet Networking Control Model */ +#define CDC_SUBCLASS_ATM 0x07 /* ATM Networking Control Model */ + /* 0x08-0x0d Reserved (future use) */ +#define CDC_SUBCLASS_MBIM 0x0e /* MBIM Control Model */ + /* 0x0f-0x7f Reserved (future use) */ + /* 0x80-0xfe Reserved (vendor specific) */ + +#define CDC_DIRECT_LINE_CONTROL_MODEL 0x01U +#define CDC_ABSTRACT_CONTROL_MODEL 0x02U +#define CDC_TELEPHONE_CONTROL_MODEL 0x03U +#define CDC_MULTI_CHANNEL_CONTROL_MODEL 0x04U +#define CDC_CAPI_CONTROL_MODEL 0x05U +#define CDC_ETHERNET_NETWORKING_CONTROL_MODEL 0x06U +#define CDC_ATM_NETWORKING_CONTROL_MODEL 0x07U +#define CDC_WIRELESS_HANDSET_CONTROL_MODEL 0x08U +#define CDC_DEVICE_MANAGEMENT 0x09U +#define CDC_MOBILE_DIRECT_LINE_MODEL 0x0AU +#define CDC_OBEX 0x0BU +#define CDC_ETHERNET_EMULATION_MODEL 0x0CU +#define CDC_NETWORK_CONTROL_MODEL 0x0DU + +/* Communication interface class control protocol codes */ +/* (usbcdc11.pdf, 4.4, Table 17) */ +#define CDC_COMMON_PROTOCOL_NONE 0x00U +#define CDC_COMMON_PROTOCOL_AT_COMMANDS 0x01U +#define CDC_COMMON_PROTOCOL_AT_COMMANDS_PCCA_101 0x02U +#define CDC_COMMON_PROTOCOL_AT_COMMANDS_PCCA_101_AND_ANNEXO 0x03U +#define CDC_COMMON_PROTOCOL_AT_COMMANDS_GSM_707 0x04U +#define CDC_COMMON_PROTOCOL_AT_COMMANDS_3GPP_27007 0x05U +#define CDC_COMMON_PROTOCOL_AT_COMMANDS_CDMA 0x06U +#define CDC_COMMON_PROTOCOL_ETHERNET_EMULATION_MODEL 0x07U +// NCM Communication Interface Protocol Codes +// (usbncm10.pdf, 4.2, Table 4-2) +#define CDC_NCM_PROTOCOL_NONE 0x00U +#define CDC_NCM_PROTOCOL_OEM 0xFEU + +/* Data interface class code */ +/* (usbcdc11.pdf, 4.5, Table 18) */ +#define CDC_DATA_INTERFACE_CLASS 0x0A + +/* Data Interface Sub-Class Codes ********************************************/ +#define CDC_DATA_SUBCLASS_NONE 0x00 + +/* Data interface class protocol codes */ +/* (usbcdc11.pdf, 4.7, Table 19) */ +#define CDC_DATA_PROTOCOL_ISDN_BRI 0x30 +#define CDC_DATA_PROTOCOL_HDLC 0x31 +#define CDC_DATA_PROTOCOL_TRANSPARENT 0x32 +#define CDC_DATA_PROTOCOL_Q921_MANAGEMENT 0x50 +#define CDC_DATA_PROTOCOL_Q921_DATA_LINK 0x51 +#define CDC_DATA_PROTOCOL_Q921_MULTIPLEXOR 0x52 +#define CDC_DATA_PROTOCOL_V42 0x90 +#define CDC_DATA_PROTOCOL_EURO_ISDN 0x91 +#define CDC_DATA_PROTOCOL_V24_RATE_ADAPTATION 0x92 +#define CDC_DATA_PROTOCOL_CAPI 0x93 +#define CDC_DATA_PROTOCOL_HOST_BASED_DRIVER 0xFD +#define CDC_DATA_PROTOCOL_DESCRIBED_IN_PUFD 0xFE + +/* Type values for bDescriptorType field of functional descriptors */ +/* (usbcdc11.pdf, 5.2.3, Table 24) */ +#define CDC_CS_INTERFACE 0x24 +#define CDC_CS_ENDPOINT 0x25 + +/* Type values for bDescriptorSubtype field of functional descriptors */ +/* (usbcdc11.pdf, 5.2.3, Table 25) */ +#define CDC_FUNC_DESC_HEADER 0x00 +#define CDC_FUNC_DESC_CALL_MANAGEMENT 0x01 +#define CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT 0x02 +#define CDC_FUNC_DESC_DIRECT_LINE_MANAGEMENT 0x03 +#define CDC_FUNC_DESC_TELEPHONE_RINGER 0x04 +#define CDC_FUNC_DESC_REPORTING_CAPABILITIES 0x05 +#define CDC_FUNC_DESC_UNION 0x06 +#define CDC_FUNC_DESC_COUNTRY_SELECTION 0x07 +#define CDC_FUNC_DESC_TELEPHONE_OPERATIONAL_MODES 0x08 +#define CDC_FUNC_DESC_USB_TERMINAL 0x09 +#define CDC_FUNC_DESC_NETWORK_CHANNEL 0x0A +#define CDC_FUNC_DESC_PROTOCOL_UNIT 0x0B +#define CDC_FUNC_DESC_EXTENSION_UNIT 0x0C +#define CDC_FUNC_DESC_MULTI_CHANNEL_MANAGEMENT 0x0D +#define CDC_FUNC_DESC_CAPI_CONTROL_MANAGEMENT 0x0E +#define CDC_FUNC_DESC_ETHERNET_NETWORKING 0x0F +#define CDC_FUNC_DESC_ATM_NETWORKING 0x10 +#define CDC_FUNC_DESC_WIRELESS_HANDSET_CONTROL_MODEL 0x11 +#define CDC_FUNC_DESC_MOBILE_DIRECT_LINE_MODEL 0x12 +#define CDC_FUNC_DESC_MOBILE_DIRECT_LINE_MODEL_DETAIL 0x13 +#define CDC_FUNC_DESC_DEVICE_MANAGEMENT_MODEL 0x14 +#define CDC_FUNC_DESC_OBEX 0x15 +#define CDC_FUNC_DESC_COMMAND_SET 0x16 +#define CDC_FUNC_DESC_COMMAND_SET_DETAIL 0x17 +#define CDC_FUNC_DESC_TELEPHONE_CONTROL_MODEL 0x18 +#define CDC_FUNC_DESC_OBEX_SERVICE_IDENTIFIER 0x19 +#define CDC_FUNC_DESC_NCM 0x1A + +/* CDC class-specific request codes */ +/* (usbcdc11.pdf, 6.2, Table 46) */ +/* see Table 45 for info about the specific requests. */ +#define CDC_REQUEST_SEND_ENCAPSULATED_COMMAND 0x00 +#define CDC_REQUEST_GET_ENCAPSULATED_RESPONSE 0x01 +#define CDC_REQUEST_SET_COMM_FEATURE 0x02 +#define CDC_REQUEST_GET_COMM_FEATURE 0x03 +#define CDC_REQUEST_CLEAR_COMM_FEATURE 0x04 +#define CDC_REQUEST_SET_AUX_LINE_STATE 0x10 +#define CDC_REQUEST_SET_HOOK_STATE 0x11 +#define CDC_REQUEST_PULSE_SETUP 0x12 +#define CDC_REQUEST_SEND_PULSE 0x13 +#define CDC_REQUEST_SET_PULSE_TIME 0x14 +#define CDC_REQUEST_RING_AUX_JACK 0x15 +#define CDC_REQUEST_SET_LINE_CODING 0x20 +#define CDC_REQUEST_GET_LINE_CODING 0x21 +#define CDC_REQUEST_SET_CONTROL_LINE_STATE 0x22 +#define CDC_REQUEST_SEND_BREAK 0x23 +#define CDC_REQUEST_SET_RINGER_PARMS 0x30 +#define CDC_REQUEST_GET_RINGER_PARMS 0x31 +#define CDC_REQUEST_SET_OPERATION_PARMS 0x32 +#define CDC_REQUEST_GET_OPERATION_PARMS 0x33 +#define CDC_REQUEST_SET_LINE_PARMS 0x34 +#define CDC_REQUEST_GET_LINE_PARMS 0x35 +#define CDC_REQUEST_DIAL_DIGITS 0x36 +#define CDC_REQUEST_SET_UNIT_PARAMETER 0x37 +#define CDC_REQUEST_GET_UNIT_PARAMETER 0x38 +#define CDC_REQUEST_CLEAR_UNIT_PARAMETER 0x39 +#define CDC_REQUEST_GET_PROFILE 0x3A +#define CDC_REQUEST_SET_ETHERNET_MULTICAST_FILTERS 0x40 +#define CDC_REQUEST_SET_ETHERNET_PMP_FILTER 0x41 +#define CDC_REQUEST_GET_ETHERNET_PMP_FILTER 0x42 +#define CDC_REQUEST_SET_ETHERNET_PACKET_FILTER 0x43 +#define CDC_REQUEST_GET_ETHERNET_STATISTIC 0x44 +#define CDC_REQUEST_SET_ATM_DATA_FORMAT 0x50 +#define CDC_REQUEST_GET_ATM_DEVICE_STATISTICS 0x51 +#define CDC_REQUEST_SET_ATM_DEFAULT_VC 0x52 +#define CDC_REQUEST_GET_ATM_VC_STATISTICS 0x53 +#define CDC_REQUEST_GET_NTB_PARAMETERS 0x80 +#define CDC_REQUEST_GET_NET_ADDRESS 0x81 +#define CDC_REQUEST_SET_NET_ADDRESS 0x82 +#define CDC_REQUEST_GET_NTB_FORMAT 0x83 +#define CDC_REQUEST_SET_NTB_FORMAT 0x84 +#define CDC_REQUEST_GET_NTB_INPUT_SIZE 0x85 +#define CDC_REQUEST_SET_NTB_INPUT_SIZE 0x86 +#define CDC_REQUEST_GET_MAX_DATAGRAM_SIZE 0x87 +#define CDC_REQUEST_SET_MAX_DATAGRAM_SIZE 0x88 +#define CDC_REQUEST_GET_CRC_MODE 0x89 +#define CDC_REQUEST_SET_CRC_MODE 0x90 + +/* Communication feature selector codes */ +/* (usbcdc11.pdf, 6.2.2..6.2.4, Table 47) */ +#define CDC_ABSTRACT_STATE 0x01 +#define CDC_COUNTRY_SETTING 0x02 + +/** Control Signal Bitmap Values for SetControlLineState */ +#define SET_CONTROL_LINE_STATE_RTS 0x02 +#define SET_CONTROL_LINE_STATE_DTR 0x01 + +/* Feature Status returned for ABSTRACT_STATE Selector */ +/* (usbcdc11.pdf, 6.2.3, Table 48) */ +#define CDC_IDLE_SETTING (1 << 0) +#define CDC_DATA_MULTPLEXED_STATE (1 << 1) + +/* Control signal bitmap values for the SetControlLineState request */ +/* (usbcdc11.pdf, 6.2.14, Table 51) */ +#define CDC_DTE_PRESENT (1 << 0) +#define CDC_ACTIVATE_CARRIER (1 << 1) + +/* CDC class-specific notification codes */ +/* (usbcdc11.pdf, 6.3, Table 68) */ +/* see Table 67 for Info about class-specific notifications */ +#define CDC_NOTIFICATION_NETWORK_CONNECTION 0x00 +#define CDC_RESPONSE_AVAILABLE 0x01 +#define CDC_AUX_JACK_HOOK_STATE 0x08 +#define CDC_RING_DETECT 0x09 +#define CDC_NOTIFICATION_SERIAL_STATE 0x20 +#define CDC_CALL_STATE_CHANGE 0x28 +#define CDC_LINE_STATE_CHANGE 0x29 +#define CDC_CONNECTION_SPEED_CHANGE 0x2A + +/* UART state bitmap values (Serial state notification). */ +/* (usbcdc11.pdf, 6.3.5, Table 69) */ +#define CDC_SERIAL_STATE_OVERRUN (1 << 6) /* receive data overrun error has occurred */ +#define CDC_SERIAL_STATE_OVERRUN_Pos (6) +#define CDC_SERIAL_STATE_OVERRUN_Msk (1 << CDC_SERIAL_STATE_OVERRUN_Pos) +#define CDC_SERIAL_STATE_PARITY (1 << 5) /* parity error has occurred */ +#define CDC_SERIAL_STATE_PARITY_Pos (5) +#define CDC_SERIAL_STATE_PARITY_Msk (1 << CDC_SERIAL_STATE_PARITY_Pos) +#define CDC_SERIAL_STATE_FRAMING (1 << 4) /* framing error has occurred */ +#define CDC_SERIAL_STATE_FRAMING_Pos (4) +#define CDC_SERIAL_STATE_FRAMING_Msk (1 << CDC_SERIAL_STATE_FRAMING_Pos) +#define CDC_SERIAL_STATE_RING (1 << 3) /* state of ring signal detection */ +#define CDC_SERIAL_STATE_RING_Pos (3) +#define CDC_SERIAL_STATE_RING_Msk (1 << CDC_SERIAL_STATE_RING_Pos) +#define CDC_SERIAL_STATE_BREAK (1 << 2) /* state of break detection */ +#define CDC_SERIAL_STATE_BREAK_Pos (2) +#define CDC_SERIAL_STATE_BREAK_Msk (1 << CDC_SERIAL_STATE_BREAK_Pos) +#define CDC_SERIAL_STATE_TX_CARRIER (1 << 1) /* state of transmission carrier */ +#define CDC_SERIAL_STATE_TX_CARRIER_Pos (1) +#define CDC_SERIAL_STATE_TX_CARRIER_Msk (1 << CDC_SERIAL_STATE_TX_CARRIER_Pos) +#define CDC_SERIAL_STATE_RX_CARRIER (1 << 0) /* state of receiver carrier */ +#define CDC_SERIAL_STATE_RX_CARRIER_Pos (0) +#define CDC_SERIAL_STATE_RX_CARRIER_Msk (1 << CDC_SERIAL_STATE_RX_CARRIER_Pos) + +#define CDC_ECM_XMIT_OK (1 << 0) +#define CDC_ECM_RVC_OK (1 << 1) +#define CDC_ECM_XMIT_ERROR (1 << 2) +#define CDC_ECM_RCV_ERROR (1 << 3) +#define CDC_ECM_RCV_NO_BUFFER (1 << 4) +#define CDC_ECM_DIRECTED_BYTES_XMIT (1 << 5) +#define CDC_ECM_DIRECTED_FRAMES_XMIT (1 << 6) +#define CDC_ECM_MULTICAST_BYTES_XMIT (1 << 7) +#define CDC_ECM_MULTICAST_FRAMES_XMIT (1 << 8) +#define CDC_ECM_BROADCAST_BYTES_XMIT (1 << 9) +#define CDC_ECM_BROADCAST_FRAMES_XMIT (1 << 10) +#define CDC_ECM_DIRECTED_BYTES_RCV (1 << 11) +#define CDC_ECM_DIRECTED_FRAMES_RCV (1 << 12) +#define CDC_ECM_MULTICAST_BYTES_RCV (1 << 13) +#define CDC_ECM_MULTICAST_FRAMES_RCV (1 << 14) +#define CDC_ECM_BROADCAST_BYTES_RCV (1 << 15) +#define CDC_ECM_BROADCAST_FRAMES_RCV (1 << 16) +#define CDC_ECM_RCV_CRC_ERROR (1 << 17) +#define CDC_ECM_TRANSMIT_QUEUE_LENGTH (1 << 18) +#define CDC_ECM_RCV_ERROR_ALIGNMENT (1 << 19) +#define CDC_ECM_XMIT_ONE_COLLISION (1 << 20) +#define CDC_ECM_XMIT_MORE_COLLISIONS (1 << 21) +#define CDC_ECM_XMIT_DEFERRED (1 << 22) +#define CDC_ECM_XMIT_MAX_COLLISIONS (1 << 23) +#define CDC_ECM_RCV_OVERRUN (1 << 24) +#define CDC_ECM_XMIT_UNDERRUN (1 << 25) +#define CDC_ECM_XMIT_HEARTBEAT_FAILURE (1 << 26) +#define CDC_ECM_XMIT_TIMES_CRS_LOST (1 << 27) +#define CDC_ECM_XMIT_LATE_COLLISIONS (1 << 28) + +#define CDC_ECM_MAC_STR_DESC (uint8_t *)"010202030000" +#define CDC_ECM_MAC_ADDR0 0x00U /* 01 */ +#define CDC_ECM_MAC_ADDR1 0x02U /* 02 */ +#define CDC_ECM_MAC_ADDR2 0x02U /* 03 */ +#define CDC_ECM_MAC_ADDR3 0x03U /* 00 */ +#define CDC_ECM_MAC_ADDR4 0x00U /* 00 */ +#define CDC_ECM_MAC_ADDR5 0x00U /* 00 */ + +#define CDC_ECM_NET_DISCONNECTED 0x00U +#define CDC_ECM_NET_CONNECTED 0x01U + +#define CDC_ECM_ETH_STATS_RESERVED 0xE0U +#define CDC_ECM_BMREQUEST_TYPE_ECM 0xA1U + +#define CDC_ECM_CONNECT_SPEED_UPSTREAM 0x004C4B40U /* 5Mbps */ +#define CDC_ECM_CONNECT_SPEED_DOWNSTREAM 0x004C4B40U /* 5Mbps */ + +#define CDC_ECM_NOTIFY_CODE_NETWORK_CONNECTION 0x00 +#define CDC_ECM_NOTIFY_CODE_RESPONSE_AVAILABLE 0x01 +#define CDC_ECM_NOTIFY_CODE_CONNECTION_SPEED_CHANGE 0x2A + +#define CDC_NCM_NTH16_SIGNATURE 0x484D434E +#define CDC_NCM_NDP16_SIGNATURE_NCM0 0x304D434E +#define CDC_NCM_NDP16_SIGNATURE_NCM1 0x314D434E + +/*------------------------------------------------------------------------------ + * Structures based on usbcdc11.pdf (www.usb.org) + *----------------------------------------------------------------------------*/ + +/* Header functional descriptor */ +/* (usbcdc11.pdf, 5.2.3.1) */ +/* This header must precede any list of class-specific descriptors. */ +struct cdc_header_descriptor { + uint8_t bFunctionLength; /* size of this descriptor in bytes */ + uint8_t bDescriptorType; /* CS_INTERFACE descriptor type */ + uint8_t bDescriptorSubtype; /* Header functional descriptor subtype */ + uint16_t bcdCDC; /* USB CDC specification release version */ +} __PACKED; + +/* Call management functional descriptor */ +/* (usbcdc11.pdf, 5.2.3.2) */ +/* Describes the processing of calls for the communication class interface. */ +struct cdc_call_management_descriptor { + uint8_t bFunctionLength; /* size of this descriptor in bytes */ + uint8_t bDescriptorType; /* CS_INTERFACE descriptor type */ + uint8_t bDescriptorSubtype; /* call management functional descriptor subtype */ + uint8_t bmCapabilities; /* capabilities that this configuration supports */ + uint8_t bDataInterface; /* interface number of the data class interface used for call management (optional) */ +} __PACKED; + +/* Abstract control management functional descriptor */ +/* (usbcdc11.pdf, 5.2.3.3) */ +/* Describes the command supported by the communication interface class with the Abstract Control Model subclass code. */ +struct cdc_abstract_control_management_descriptor { + uint8_t bFunctionLength; /* size of this descriptor in bytes */ + uint8_t bDescriptorType; /* CS_INTERFACE descriptor type */ + uint8_t bDescriptorSubtype; /* abstract control management functional descriptor subtype */ + uint8_t bmCapabilities; /* capabilities supported by this configuration */ +} __PACKED; + +/* Union functional descriptors */ +/* (usbcdc11.pdf, 5.2.3.8) */ +/* Describes the relationship between a group of interfaces that can be considered to form a functional unit. */ +struct cdc_union_descriptor { + uint8_t bFunctionLength; /* size of this descriptor in bytes */ + uint8_t bDescriptorType; /* CS_INTERFACE descriptor type */ + uint8_t bDescriptorSubtype; /* union functional descriptor subtype */ + uint8_t bMasterInterface; /* interface number designated as master */ +} __PACKED; + +/* Union functional descriptors with one slave interface */ +/* (usbcdc11.pdf, 5.2.3.8) */ +struct cdc_union_1slave_descriptor { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t bControlInterface; + uint8_t bSubordinateInterface0; +} __PACKED; + +/* Line coding structure for GET_LINE_CODING / SET_LINE_CODING class requests*/ +/* Format of the data returned when a GetLineCoding request is received */ +/* (usbcdc11.pdf, 6.2.13) */ +struct cdc_line_coding { + uint32_t dwDTERate; /* Data terminal rate in bits per second */ + uint8_t bCharFormat; /* Number of stop bits */ + uint8_t bParityType; /* Parity bit type */ + uint8_t bDataBits; /* Number of data bits */ +} __PACKED; + +/** Data structure for the notification about SerialState */ +struct cdc_acm_notification { + uint8_t bmRequestType; + uint8_t bNotificationType; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; + uint16_t data; +} __PACKED; + +/** Ethernet Networking Functional Descriptor */ +struct cdc_eth_descriptor { + uint8_t bFunctionLength; + uint8_t bDescriptorType; + uint8_t bDescriptorSubtype; + uint8_t iMACAddress; + uint32_t bmEthernetStatistics; + uint16_t wMaxSegmentSize; + uint16_t wNumberMCFilters; + uint8_t bNumberPowerFilters; +} __PACKED; + +struct cdc_eth_notification { + uint8_t bmRequestType; + uint8_t bNotificationType; + uint16_t wValue; + uint16_t wIndex; + uint16_t wLength; + uint8_t data[8]; +} __PACKED; + +struct cdc_ncm_ntb_parameters { + uint16_t wLength; + uint16_t bmNtbFormatsSupported; + uint32_t dwNtbInMaxSize; + uint16_t wNdbInDivisor; + uint16_t wNdbInPayloadRemainder; + uint16_t wNdbInAlignment; + uint16_t wReserved; + uint32_t dwNtbOutMaxSize; + uint16_t wNdbOutDivisor; + uint16_t wNdbOutPayloadRemainder; + uint16_t wNdbOutAlignment; + uint16_t wNtbOutMaxDatagrams; +}; + +struct cdc_ncm_nth16 { + uint32_t dwSignature; + uint16_t wHeaderLength; + uint16_t wSequence; + uint16_t wBlockLength; + uint16_t wNdpIndex; +}; + +struct cdc_ncm_ndp16_datagram { + uint16_t wDatagramIndex; + uint16_t wDatagramLength; +}; + +struct cdc_ncm_ndp16 { + uint32_t dwSignature; + uint16_t wLength; + uint16_t wNextNdpIndex; + struct cdc_ncm_ndp16_datagram datagram[]; +}; + +/*Length of template descriptor: 66 bytes*/ +#define CDC_ACM_DESCRIPTOR_LEN (8 + 9 + 5 + 5 + 4 + 5 + 7 + 9 + 7 + 7) +// clang-format off +#define CDC_ACM_DESCRIPTOR_INIT(bFirstInterface, int_ep, out_ep, in_ep, wMaxPacketSize, str_idx) \ + /* Interface Associate */ \ + 0x08, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION, /* bDescriptorType */ \ + bFirstInterface, /* bFirstInterface */ \ + 0x02, /* bInterfaceCount */ \ + USB_DEVICE_CLASS_CDC, /* bFunctionClass */ \ + CDC_ABSTRACT_CONTROL_MODEL, /* bFunctionSubClass */ \ + CDC_COMMON_PROTOCOL_NONE, /* bFunctionProtocol */ \ + 0x00, /* iFunction */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bFirstInterface, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x01, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_CDC, /* bInterfaceClass */ \ + CDC_ABSTRACT_CONTROL_MODEL, /* bInterfaceSubClass */ \ + CDC_COMMON_PROTOCOL_NONE, /* bInterfaceProtocol */ \ + str_idx, /* iInterface */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_HEADER, /* bDescriptorSubtype */ \ + WBVAL(CDC_V1_10), /* bcdCDC */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_CALL_MANAGEMENT, /* bDescriptorSubtype */ \ + 0x00, /* bmCapabilities */ \ + (uint8_t)(bFirstInterface + 1), /* bDataInterface */ \ + 0x04, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT, /* bDescriptorSubtype */ \ + 0x02, /* bmCapabilities */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_UNION, /* bDescriptorSubtype */ \ + bFirstInterface, /* bMasterInterface */ \ + (uint8_t)(bFirstInterface + 1), /* bSlaveInterface0 */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + int_ep, /* bEndpointAddress */ \ + 0x03, /* bmAttributes */ \ + 0x08, 0x00, /* wMaxPacketSize */ \ + 0x0a, /* bInterval */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + (uint8_t)(bFirstInterface + 1), /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x02, /* bNumEndpoints */ \ + CDC_DATA_INTERFACE_CLASS, /* bInterfaceClass */ \ + 0x00, /* bInterfaceSubClass */ \ + 0x00, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + out_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00, /* bInterval */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + in_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00 /* bInterval */ +// clang-format on + +/*Length of template descriptor: 66 bytes*/ +#define CDC_RNDIS_DESCRIPTOR_LEN (8 + 9 + 5 + 5 + 4 + 5 + 7 + 9 + 7 + 7) +// clang-format off +#define CDC_RNDIS_DESCRIPTOR_INIT(bFirstInterface, int_ep, out_ep, in_ep, wMaxPacketSize, str_idx) \ + /* Interface Associate */ \ + 0x08, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION, /* bDescriptorType */ \ + bFirstInterface, /* bFirstInterface */ \ + 0x02, /* bInterfaceCount */ \ + USB_DEVICE_CLASS_WIRELESS, /* bFunctionClass */ \ + 0x01, /* bFunctionSubClass */ \ + 0x03, /* bFunctionProtocol */ \ + 0x00, /* iFunction */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bFirstInterface, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x01, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_WIRELESS, /* bInterfaceClass */ \ + 0x01, /* bInterfaceSubClass */ \ + 0x03, /* bInterfaceProtocol */ \ + str_idx, /* iInterface */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_HEADER, /* bDescriptorSubtype */ \ + WBVAL(CDC_V1_10), /* bcdCDC */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_CALL_MANAGEMENT, /* bDescriptorSubtype */ \ + 0x00, /* bmCapabilities */ \ + (uint8_t)(bFirstInterface + 1), /* bDataInterface */ \ + 0x04, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_ABSTRACT_CONTROL_MANAGEMENT, /* bDescriptorSubtype */ \ + 0x00, /* bmCapabilities */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_UNION, /* bDescriptorSubtype */ \ + bFirstInterface, /* bMasterInterface */ \ + (uint8_t)(bFirstInterface + 1), /* bSlaveInterface0 */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + int_ep, /* bEndpointAddress */ \ + 0x03, /* bmAttributes */ \ + 0x08, 0x00, /* wMaxPacketSize */ \ + 0x05, /* bInterval */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + (uint8_t)(bFirstInterface + 1), /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x02, /* bNumEndpoints */ \ + CDC_DATA_INTERFACE_CLASS, /* bInterfaceClass */ \ + 0x00, /* bInterfaceSubClass */ \ + 0x00, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + out_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00, /* bInterval */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + in_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00 /* bInterval */ +// clang-format on + +#define DBVAL_BE(x) ((x >> 24) & 0xFF), ((x >> 16) & 0xFF), ((x >> 8) & 0xFF), (x & 0xFF) + +/*Length of template descriptor: 71 bytes*/ +#define CDC_ECM_DESCRIPTOR_LEN (8 + 9 + 5 + 5 + 13 + 7 + 9 + 7 + 7) +// clang-format off +#define CDC_ECM_DESCRIPTOR_INIT(bFirstInterface, int_ep, out_ep, in_ep, wMaxPacketSize, \ +eth_statistics, wMaxSegmentSize, wNumberMCFilters, bNumberPowerFilters, str_idx) \ + /* Interface Associate */ \ + 0x08, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION, /* bDescriptorType */ \ + bFirstInterface, /* bFirstInterface */ \ + 0x02, /* bInterfaceCount */ \ + USB_DEVICE_CLASS_CDC, /* bFunctionClass */ \ + CDC_ETHERNET_NETWORKING_CONTROL_MODEL, /* bFunctionSubClass */ \ + CDC_COMMON_PROTOCOL_NONE, /* bFunctionProtocol */ \ + 0x00, /* iFunction */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bFirstInterface, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x01, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_CDC, /* bInterfaceClass */ \ + CDC_ETHERNET_NETWORKING_CONTROL_MODEL, /* bInterfaceSubClass */ \ + CDC_COMMON_PROTOCOL_NONE, /* bInterfaceProtocol */ \ + str_idx, /* iInterface */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_HEADER, /* bDescriptorSubtype */ \ + WBVAL(CDC_V1_10), /* bcdCDC */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_UNION, /* bDescriptorSubtype */ \ + bFirstInterface, /* bMasterInterface */ \ + (uint8_t)(bFirstInterface + 1), /* bSlaveInterface0 */ \ + /* CDC_ECM Functional Descriptor */ \ + 0x0D, /* bFunctionLength */\ + CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */\ + CDC_FUNC_DESC_ETHERNET_NETWORKING, /* Ethernet Networking functional descriptor subtype */\ + str_idx, /* Device's MAC string index */\ + DBVAL_BE(eth_statistics), /* Ethernet statistics (bitmap) */\ + WBVAL(wMaxSegmentSize),/* wMaxSegmentSize: Ethernet Maximum Segment size, typically 1514 bytes */\ + WBVAL(wNumberMCFilters), /* wNumberMCFilters: the number of multicast filters */\ + bNumberPowerFilters, /* bNumberPowerFilters: the number of wakeup power filters */\ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + int_ep, /* bEndpointAddress */ \ + 0x03, /* bmAttributes */ \ + 0x10, 0x00, /* wMaxPacketSize */ \ + 0x05, /* bInterval */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + (uint8_t)(bFirstInterface + 1), /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x02, /* bNumEndpoints */ \ + CDC_DATA_INTERFACE_CLASS, /* bInterfaceClass */ \ + 0x00, /* bInterfaceSubClass */ \ + 0x00, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + out_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00, /* bInterval */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + in_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00 /* bInterval */ +// clang-format on + +/*Length of template descriptor: 77 bytes*/ +#define CDC_NCM_DESCRIPTOR_LEN (8 + 9 + 5 + 5 + 13 + 6 + 7 + 9 + 7 + 7) +// clang-format off +#define CDC_NCM_DESCRIPTOR_INIT(bFirstInterface, int_ep, out_ep, in_ep, wMaxPacketSize, \ +eth_statistics, wMaxSegmentSize, wNumberMCFilters, bNumberPowerFilters, str_idx) \ + /* Interface Associate */ \ + 0x08, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION, /* bDescriptorType */ \ + bFirstInterface, /* bFirstInterface */ \ + 0x02, /* bInterfaceCount */ \ + USB_DEVICE_CLASS_CDC, /* bFunctionClass */ \ + CDC_NETWORK_CONTROL_MODEL, /* bFunctionSubClass */ \ + CDC_COMMON_PROTOCOL_NONE, /* bFunctionProtocol */ \ + 0x00, /* iFunction */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bFirstInterface, /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x01, /* bNumEndpoints */ \ + USB_DEVICE_CLASS_CDC, /* bInterfaceClass */ \ + CDC_NETWORK_CONTROL_MODEL, /* bInterfaceSubClass */ \ + CDC_COMMON_PROTOCOL_NONE, /* bInterfaceProtocol */ \ + str_idx, /* iInterface */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_HEADER, /* bDescriptorSubtype */ \ + WBVAL(CDC_V1_10), /* bcdCDC */ \ + 0x05, /* bLength */ \ + CDC_CS_INTERFACE, /* bDescriptorType */ \ + CDC_FUNC_DESC_UNION, /* bDescriptorSubtype */ \ + bFirstInterface, /* bMasterInterface */ \ + (uint8_t)(bFirstInterface + 1), /* bSlaveInterface0 */ \ + /* CDC ETH Functional Descriptor */ \ + 0x0D, /* bFunctionLength */\ + CDC_CS_INTERFACE, /* bDescriptorType: CS_INTERFACE */\ + CDC_FUNC_DESC_ETHERNET_NETWORKING, /* Ethernet Networking functional descriptor subtype */\ + str_idx, /* Device's MAC string index */\ + DBVAL_BE(eth_statistics), /* Ethernet statistics (bitmap) */\ + WBVAL(wMaxPacketSize),/* wMaxSegmentSize: Ethernet Maximum Segment size, typically 1514 bytes */\ + WBVAL(wNumberMCFilters), /* wNumberMCFilters: the number of multicast filters */\ + bNumberPowerFilters, /* bNumberPowerFilters: the number of wakeup power filters */\ + 0x06, \ + CDC_CS_INTERFACE, \ + CDC_FUNC_DESC_NCM, \ + 0x00, 0x01, \ + 0x23, \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + int_ep, /* bEndpointAddress */ \ + 0x03, /* bmAttributes */ \ + 0x10, 0x00, /* wMaxPacketSize */ \ + 0x10, /* bInterval */ \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + (uint8_t)(bFirstInterface + 1), /* bInterfaceNumber */ \ + 0x00, /* bAlternateSetting */ \ + 0x02, /* bNumEndpoints */ \ + CDC_DATA_INTERFACE_CLASS, /* bInterfaceClass */ \ + 0x00, /* bInterfaceSubClass */ \ + 0x00, /* bInterfaceProtocol */ \ + 0x00, /* iInterface */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + out_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00, /* bInterval */ \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + in_ep, /* bEndpointAddress */ \ + 0x02, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + 0x00 /* bInterval */ +// clang-format on + +#endif /* USB_CDC_H */ diff --git a/ch32v103_hallarray_controller/3rdparty/CherryUSB/class/cdc/usbd_cdc.h b/ch32v103_hallarray_controller/3rdparty/CherryUSB/class/cdc/usbd_cdc.h new file mode 100644 index 0000000..2cf3df1 --- /dev/null +++ b/ch32v103_hallarray_controller/3rdparty/CherryUSB/class/cdc/usbd_cdc.h @@ -0,0 +1,13 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBD_CDC_H +#define USBD_CDC_H + +// legacy for old version + +#include "usbd_cdc_acm.h" + +#endif \ No newline at end of file diff --git a/ch32v103_hallarray_controller/3rdparty/CherryUSB/class/cdc/usbd_cdc_acm.c b/ch32v103_hallarray_controller/3rdparty/CherryUSB/class/cdc/usbd_cdc_acm.c new file mode 100644 index 0000000..cf7c3c0 --- /dev/null +++ b/ch32v103_hallarray_controller/3rdparty/CherryUSB/class/cdc/usbd_cdc_acm.c @@ -0,0 +1,134 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_cdc_acm.h" + +const char *stop_name[] = { "1", "1.5", "2" }; +const char *parity_name[] = { "N", "O", "E", "M", "S" }; + +static int cdc_acm_class_interface_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + USB_LOG_DBG("CDC Class request: " + "bRequest 0x%02x\r\n", + setup->bRequest); + + struct cdc_line_coding line_coding; + bool dtr, rts; + uint8_t intf_num = LO_BYTE(setup->wIndex); + + switch (setup->bRequest) { + case CDC_REQUEST_SET_LINE_CODING: + + /*******************************************************************************/ + /* Line Coding Structure */ + /*-----------------------------------------------------------------------------*/ + /* Offset | Field | Size | Value | Description */ + /* 0 | dwDTERate | 4 | Number |Data terminal rate, in bits per second*/ + /* 4 | bCharFormat | 1 | Number | Stop bits */ + /* 0 - 1 Stop bit */ + /* 1 - 1.5 Stop bits */ + /* 2 - 2 Stop bits */ + /* 5 | bParityType | 1 | Number | Parity */ + /* 0 - None */ + /* 1 - Odd */ + /* 2 - Even */ + /* 3 - Mark */ + /* 4 - Space */ + /* 6 | bDataBits | 1 | Number Data bits (5, 6, 7, 8 or 16). */ + /*******************************************************************************/ + memcpy(&line_coding, *data, setup->wLength); + USB_LOG_DBG("Set intf:%d linecoding <%d %d %s %s>\r\n", + intf_num, + line_coding.dwDTERate, + line_coding.bDataBits, + parity_name[line_coding.bParityType], + stop_name[line_coding.bCharFormat]); + + usbd_cdc_acm_set_line_coding(busid, intf_num, &line_coding); + break; + + case CDC_REQUEST_SET_CONTROL_LINE_STATE: + dtr = (setup->wValue & 0x0001); + rts = (setup->wValue & 0x0002); + USB_LOG_DBG("Set intf:%d DTR 0x%x,RTS 0x%x\r\n", + intf_num, + dtr, + rts); + usbd_cdc_acm_set_dtr(busid, intf_num, dtr); + usbd_cdc_acm_set_rts(busid, intf_num, rts); + break; + + case CDC_REQUEST_GET_LINE_CODING: + usbd_cdc_acm_get_line_coding(busid, intf_num, &line_coding); + memcpy(*data, &line_coding, 7); + *len = 7; + USB_LOG_DBG("Get intf:%d linecoding %d %d %d %d\r\n", + intf_num, + line_coding.dwDTERate, + line_coding.bCharFormat, + line_coding.bParityType, + line_coding.bDataBits); + break; + case CDC_REQUEST_SEND_BREAK: + usbd_cdc_acm_send_break(busid, intf_num); + break; + default: + USB_LOG_WRN("Unhandled CDC Class bRequest 0x%02x\r\n", setup->bRequest); + return -1; + } + + return 0; +} + +struct usbd_interface *usbd_cdc_acm_init_intf(uint8_t busid, struct usbd_interface *intf) +{ + (void)busid; + + intf->class_interface_handler = cdc_acm_class_interface_request_handler; + intf->class_endpoint_handler = NULL; + intf->vendor_handler = NULL; + intf->notify_handler = NULL; + + return intf; +} + +__WEAK void usbd_cdc_acm_set_line_coding(uint8_t busid, uint8_t intf, struct cdc_line_coding *line_coding) +{ + (void)busid; + (void)intf; + (void)line_coding; +} + +__WEAK void usbd_cdc_acm_get_line_coding(uint8_t busid, uint8_t intf, struct cdc_line_coding *line_coding) +{ + (void)busid; + (void)intf; + + line_coding->dwDTERate = 2000000; + line_coding->bDataBits = 8; + line_coding->bParityType = 0; + line_coding->bCharFormat = 0; +} + +__WEAK void usbd_cdc_acm_set_dtr(uint8_t busid, uint8_t intf, bool dtr) +{ + (void)busid; + (void)intf; + (void)dtr; +} + +__WEAK void usbd_cdc_acm_set_rts(uint8_t busid, uint8_t intf, bool rts) +{ + (void)busid; + (void)intf; + (void)rts; +} + +__WEAK void usbd_cdc_acm_send_break(uint8_t busid, uint8_t intf) +{ + (void)busid; + (void)intf; +} diff --git a/ch32v103_hallarray_controller/3rdparty/CherryUSB/class/cdc/usbd_cdc_acm.h b/ch32v103_hallarray_controller/3rdparty/CherryUSB/class/cdc/usbd_cdc_acm.h new file mode 100644 index 0000000..662c238 --- /dev/null +++ b/ch32v103_hallarray_controller/3rdparty/CherryUSB/class/cdc/usbd_cdc_acm.h @@ -0,0 +1,29 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBD_CDC_ACM_H +#define USBD_CDC_ACM_H + +#include "usb_cdc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Init cdc acm interface driver */ +struct usbd_interface *usbd_cdc_acm_init_intf(uint8_t busid, struct usbd_interface *intf); + +/* Setup request command callback api */ +void usbd_cdc_acm_set_line_coding(uint8_t busid, uint8_t intf, struct cdc_line_coding *line_coding); +void usbd_cdc_acm_get_line_coding(uint8_t busid, uint8_t intf, struct cdc_line_coding *line_coding); +void usbd_cdc_acm_set_dtr(uint8_t busid, uint8_t intf, bool dtr); +void usbd_cdc_acm_set_rts(uint8_t busid, uint8_t intf, bool rts); +void usbd_cdc_acm_send_break(uint8_t busid, uint8_t intf); + +#ifdef __cplusplus +} +#endif + +#endif /* USBD_CDC_ACM_H */ diff --git a/ch32v103_hallarray_controller/3rdparty/CherryUSB/class/cdc/usbd_cdc_ecm.c b/ch32v103_hallarray_controller/3rdparty/CherryUSB/class/cdc/usbd_cdc_ecm.c new file mode 100644 index 0000000..5ae10a2 --- /dev/null +++ b/ch32v103_hallarray_controller/3rdparty/CherryUSB/class/cdc/usbd_cdc_ecm.c @@ -0,0 +1,284 @@ +/* + * Copyright (c) 2023, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_cdc_ecm.h" + +#define CDC_ECM_OUT_EP_IDX 0 +#define CDC_ECM_IN_EP_IDX 1 +#define CDC_ECM_INT_EP_IDX 2 + +/* Ethernet Maximum Segment size, typically 1514 bytes */ +#define CONFIG_CDC_ECM_ETH_MAX_SEGSZE 1536U + +/* Describe EndPoints configuration */ +static struct usbd_endpoint cdc_ecm_ep_data[3]; + +#ifdef CONFIG_USBDEV_CDC_ECM_USING_LWIP +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_cdc_ecm_rx_buffer[CONFIG_CDC_ECM_ETH_MAX_SEGSZE]; +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_cdc_ecm_tx_buffer[CONFIG_CDC_ECM_ETH_MAX_SEGSZE]; +#endif +static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_cdc_ecm_notify_buf[16]; + +volatile uint32_t g_cdc_ecm_rx_data_length = 0; +volatile uint32_t g_cdc_ecm_tx_data_length = 0; + +static volatile uint8_t g_current_net_status = 0; +static volatile uint8_t g_cmd_intf = 0; + +static uint32_t g_connect_speed_table[2] = { CDC_ECM_CONNECT_SPEED_UPSTREAM, + CDC_ECM_CONNECT_SPEED_DOWNSTREAM }; + +void usbd_cdc_ecm_send_notify(uint8_t notifycode, uint8_t value, uint32_t *speed) +{ + struct cdc_eth_notification *notify = (struct cdc_eth_notification *)g_cdc_ecm_notify_buf; + uint8_t bytes2send = 0; + + notify->bmRequestType = CDC_ECM_BMREQUEST_TYPE_ECM; + notify->bNotificationType = notifycode; + + switch (notifycode) { + case CDC_ECM_NOTIFY_CODE_NETWORK_CONNECTION: + notify->wValue = value; + notify->wIndex = g_cmd_intf; + notify->wLength = 0U; + + for (uint8_t i = 0U; i < 8U; i++) { + notify->data[i] = 0U; + } + bytes2send = 8U; + break; + case CDC_ECM_NOTIFY_CODE_RESPONSE_AVAILABLE: + notify->wValue = 0U; + notify->wIndex = g_cmd_intf; + notify->wLength = 0U; + for (uint8_t i = 0U; i < 8U; i++) { + notify->data[i] = 0U; + } + bytes2send = 8U; + break; + case CDC_ECM_NOTIFY_CODE_CONNECTION_SPEED_CHANGE: + notify->wValue = 0U; + notify->wIndex = g_cmd_intf; + notify->wLength = 0x0008U; + bytes2send = 16U; + + memcpy(notify->data, speed, 8); + break; + + default: + break; + } + + if (usb_device_is_configured(0)) { + if (bytes2send) { + usbd_ep_start_write(0, cdc_ecm_ep_data[CDC_ECM_INT_EP_IDX].ep_addr, g_cdc_ecm_notify_buf, bytes2send); + } + } +} + +static int cdc_ecm_class_interface_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + USB_LOG_DBG("CDC ECM Class request: " + "bRequest 0x%02x\r\n", + setup->bRequest); + + (void)busid; + (void)data; + (void)len; + + g_cmd_intf = LO_BYTE(setup->wIndex); + + switch (setup->bRequest) { + case CDC_REQUEST_SET_ETHERNET_PACKET_FILTER: + /* bit0 Promiscuous + * bit1 ALL Multicast + * bit2 Directed + * bit3 Broadcast + * bit4 Multicast + */ +#ifdef CONFIG_USBDEV_CDC_ECM_USING_LWIP + g_connect_speed_table[0] = 100000000; /* 100 Mbps */ + g_connect_speed_table[1] = 100000000; /* 100 Mbps */ + usbd_cdc_ecm_set_connect(true, g_connect_speed_table); +#endif + break; + default: + USB_LOG_WRN("Unhandled CDC ECM Class bRequest 0x%02x\r\n", setup->bRequest); + return -1; + } + + return 0; +} + +void cdc_ecm_notify_handler(uint8_t busid, uint8_t event, void *arg) +{ + (void)busid; + (void)arg; + + switch (event) { + case USBD_EVENT_RESET: + g_current_net_status = 0; + g_cdc_ecm_rx_data_length = 0; + g_cdc_ecm_tx_data_length = 0; + break; + case USBD_EVENT_CONFIGURED: +#ifdef CONFIG_USBDEV_CDC_ECM_USING_LWIP + usbd_cdc_ecm_start_read(g_cdc_ecm_rx_buffer, CONFIG_CDC_ECM_ETH_MAX_SEGSZE); +#endif + break; + + default: + break; + } +} + +void cdc_ecm_bulk_out(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + (void)busid; + + g_cdc_ecm_rx_data_length = nbytes; + usbd_cdc_ecm_data_recv_done(g_cdc_ecm_rx_data_length); +} + +void cdc_ecm_bulk_in(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + (void)busid; + + if ((nbytes % usbd_get_ep_mps(0, ep)) == 0 && nbytes) { + /* send zlp */ + usbd_ep_start_write(0, ep, NULL, 0); + } else { + usbd_cdc_ecm_data_send_done(g_cdc_ecm_tx_data_length); + g_cdc_ecm_tx_data_length = 0; + } +} + +void cdc_ecm_int_in(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + (void)busid; + (void)ep; + (void)nbytes; + + if (g_current_net_status == 2) { + g_current_net_status = 3; + usbd_cdc_ecm_send_notify(CDC_ECM_NOTIFY_CODE_CONNECTION_SPEED_CHANGE, 0, g_connect_speed_table); + } else { + g_current_net_status = 0; + } +} + +int usbd_cdc_ecm_start_write(uint8_t *buf, uint32_t len) +{ + if (!usb_device_is_configured(0)) { + return -USB_ERR_NODEV; + } + + if (g_cdc_ecm_tx_data_length > 0) { + return -USB_ERR_BUSY; + } + + g_cdc_ecm_tx_data_length = len; + + USB_LOG_DBG("txlen:%d\r\n", g_cdc_ecm_tx_data_length); + return usbd_ep_start_write(0, cdc_ecm_ep_data[CDC_ECM_IN_EP_IDX].ep_addr, buf, len); +} + +int usbd_cdc_ecm_start_read(uint8_t *buf, uint32_t len) +{ + if (!usb_device_is_configured(0)) { + return -USB_ERR_NODEV; + } + + g_cdc_ecm_rx_data_length = 0; + return usbd_ep_start_read(0, cdc_ecm_ep_data[CDC_ECM_OUT_EP_IDX].ep_addr, buf, len); +} + +#ifdef CONFIG_USBDEV_CDC_ECM_USING_LWIP +struct pbuf *usbd_cdc_ecm_eth_rx(void) +{ + struct pbuf *p; + + if (g_cdc_ecm_rx_data_length == 0) { + return NULL; + } + p = pbuf_alloc(PBUF_RAW, g_cdc_ecm_rx_data_length, PBUF_POOL); + if (p == NULL) { + usbd_cdc_ecm_start_read(g_cdc_ecm_rx_buffer, CONFIG_CDC_ECM_ETH_MAX_SEGSZE); + return NULL; + } + usb_memcpy(p->payload, (uint8_t *)g_cdc_ecm_rx_buffer, g_cdc_ecm_rx_data_length); + p->len = g_cdc_ecm_rx_data_length; + + USB_LOG_DBG("rxlen:%d\r\n", g_cdc_ecm_rx_data_length); + usbd_cdc_ecm_start_read(g_cdc_ecm_rx_buffer, CONFIG_CDC_ECM_ETH_MAX_SEGSZE); + return p; +} + +int usbd_cdc_ecm_eth_tx(struct pbuf *p) +{ + struct pbuf *q; + uint8_t *buffer; + + if (g_cdc_ecm_tx_data_length > 0) { + return -USB_ERR_BUSY; + } + + if (p->tot_len > sizeof(g_cdc_ecm_tx_buffer)) { + p->tot_len = sizeof(g_cdc_ecm_tx_buffer); + } + + buffer = g_cdc_ecm_tx_buffer; + for (q = p; q != NULL; q = q->next) { + usb_memcpy(buffer, q->payload, q->len); + buffer += q->len; + } + + return usbd_cdc_ecm_start_write(g_cdc_ecm_tx_buffer, p->tot_len); +} +#endif + +struct usbd_interface *usbd_cdc_ecm_init_intf(struct usbd_interface *intf, const uint8_t int_ep, const uint8_t out_ep, const uint8_t in_ep) +{ + intf->class_interface_handler = cdc_ecm_class_interface_request_handler; + intf->class_endpoint_handler = NULL; + intf->vendor_handler = NULL; + intf->notify_handler = cdc_ecm_notify_handler; + + cdc_ecm_ep_data[CDC_ECM_OUT_EP_IDX].ep_addr = out_ep; + cdc_ecm_ep_data[CDC_ECM_OUT_EP_IDX].ep_cb = cdc_ecm_bulk_out; + cdc_ecm_ep_data[CDC_ECM_IN_EP_IDX].ep_addr = in_ep; + cdc_ecm_ep_data[CDC_ECM_IN_EP_IDX].ep_cb = cdc_ecm_bulk_in; + cdc_ecm_ep_data[CDC_ECM_INT_EP_IDX].ep_addr = int_ep; + cdc_ecm_ep_data[CDC_ECM_INT_EP_IDX].ep_cb = cdc_ecm_int_in; + + usbd_add_endpoint(0, &cdc_ecm_ep_data[CDC_ECM_OUT_EP_IDX]); + usbd_add_endpoint(0, &cdc_ecm_ep_data[CDC_ECM_IN_EP_IDX]); + usbd_add_endpoint(0, &cdc_ecm_ep_data[CDC_ECM_INT_EP_IDX]); + + return intf; +} + +void usbd_cdc_ecm_set_connect(bool connect, uint32_t speed[2]) +{ + if (connect) { + g_current_net_status = 2; + memcpy(g_connect_speed_table, speed, 8); + usbd_cdc_ecm_send_notify(CDC_ECM_NOTIFY_CODE_NETWORK_CONNECTION, CDC_ECM_NET_CONNECTED, NULL); + } else { + g_current_net_status = 1; + usbd_cdc_ecm_send_notify(CDC_ECM_NOTIFY_CODE_NETWORK_CONNECTION, CDC_ECM_NET_DISCONNECTED, NULL); + } +} + +__WEAK void usbd_cdc_ecm_data_recv_done(uint32_t len) +{ + (void)len; +} + +__WEAK void usbd_cdc_ecm_data_send_done(uint32_t len) +{ + (void)len; +} diff --git a/ch32v103_hallarray_controller/3rdparty/CherryUSB/class/cdc/usbd_cdc_ecm.h b/ch32v103_hallarray_controller/3rdparty/CherryUSB/class/cdc/usbd_cdc_ecm.h new file mode 100644 index 0000000..3e0284e --- /dev/null +++ b/ch32v103_hallarray_controller/3rdparty/CherryUSB/class/cdc/usbd_cdc_ecm.h @@ -0,0 +1,36 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBD_CDC_ECM_H +#define USBD_CDC_ECM_H + +#include "usb_cdc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Init cdc ecm interface driver */ +struct usbd_interface *usbd_cdc_ecm_init_intf(struct usbd_interface *intf, const uint8_t int_ep, const uint8_t out_ep, const uint8_t in_ep); + +void usbd_cdc_ecm_set_connect(bool connect, uint32_t speed[2]); + +void usbd_cdc_ecm_data_recv_done(uint32_t len); +void usbd_cdc_ecm_data_send_done(uint32_t len); +int usbd_cdc_ecm_start_write(uint8_t *buf, uint32_t len); +int usbd_cdc_ecm_start_read(uint8_t *buf, uint32_t len); + +#ifdef CONFIG_USBDEV_CDC_ECM_USING_LWIP +#include "lwip/netif.h" +#include "lwip/pbuf.h" +struct pbuf *usbd_cdc_ecm_eth_rx(void); +int usbd_cdc_ecm_eth_tx(struct pbuf *p); +#endif + +#ifdef __cplusplus +} +#endif + +#endif /* USBD_CDC_ECM_H */ diff --git a/ch32v103_hallarray_controller/3rdparty/CherryUSB/class/hid/usb_hid.h b/ch32v103_hallarray_controller/3rdparty/CherryUSB/class/hid/usb_hid.h new file mode 100644 index 0000000..62525a7 --- /dev/null +++ b/ch32v103_hallarray_controller/3rdparty/CherryUSB/class/hid/usb_hid.h @@ -0,0 +1,669 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_HID_H +#define USB_HID_H + +/* Subclass codes (HID 4.2) */ +#define HID_SUBCLASS_NONE 0 /* No subclass */ +#define HID_SUBCLASS_BOOTIF 1 /* Boot Interface Subclass */ + +/* HID Protocol Codes (HID 4.3) */ +#define HID_PROTOCOL_NONE 0x00 +#define HID_PROTOCOL_BOOT 0x00 +#define HID_PROTOCOL_KEYBOARD 0x01 +#define HID_PROTOCOL_REPORT 0x01 +#define HID_PROTOCOL_MOUSE 0x02 + +/* HID Class Descriptor Types (HID 7.1) */ +#define HID_DESCRIPTOR_TYPE_HID 0x21 +#define HID_DESCRIPTOR_TYPE_HID_REPORT 0x22 +#define HID_DESCRIPTOR_TYPE_HID_PHYSICAL 0x23 + +/* HID Class Specific Requests (HID 7.2) */ +#define HID_REQUEST_GET_REPORT 0x01 +#define HID_REQUEST_GET_IDLE 0x02 +#define HID_REQUEST_GET_PROTOCOL 0x03 +#define HID_REQUEST_SET_REPORT 0x09 +#define HID_REQUEST_SET_IDLE 0x0A +#define HID_REQUEST_SET_PROTOCOL 0x0B + +/* Report Type (MS byte of wValue for GET_REPORT) (HID 7.2.1) */ +#define HID_REPORT_INPUT 0x01 +#define HID_REPORT_OUTPUT 0x02 +#define HID_REPORT_FEATURE 0x03 + +/* HID Descriptor ***********************************************************/ + +#define HID_COUNTRY_NONE 0x00 /* Not Supported */ +#define HID_COUNTRY_ARABIC 0x01 /* Arabic */ +#define HID_COUNTRY_BELGIAN 0x02 /* Belgian */ +#define HID_COUNTRY_CANADA 0x03 /* Canadian-Bilingual */ +#define HID_COUNTRY_CANADRFR 0x04 /* Canadian-French */ +#define HID_COUNTRY_CZECH 0x05 /* Czech Republic */ +#define HID_COUNTRY_DANISH 0x06 /* Danish */ +#define HID_COUNTRY_FINNISH 0x07 /* Finnish */ +#define HID_COUNTRY_FRENCH 0x08 /* French */ +#define HID_COUNTRY_GERMAN 0x09 /* German */ +#define HID_COUNTRY_GREEK 0x10 /* Greek */ +#define HID_COUNTRY_HEBREW 0x11 /* Hebrew */ +#define HID_COUNTRY_HUNGARY 0x12 /* Hungary */ +#define HID_COUNTRY_ISO 0x13 /* International (ISO) */ +#define HID_COUNTRY_ITALIAN 0x14 /* Italian */ +#define HID_COUNTRY_JAPAN 0x15 /* Japan (Katakana) */ +#define HID_COUNTRY_KOREAN 0x16 /* Korean */ +#define HID_COUNTRY_LATINAM 0x17 /* Latin American */ +#define HID_COUNTRY_DUTCH 0x18 /* Netherlands/Dutch */ +#define HID_COUNTRY_NORWEGIAN 0x19 /* Norwegian */ +#define HID_COUNTRY_PERSIAN 0x20 /* Persian (Farsi) */ +#define HID_COUNTRY_POLAND 0x21 /* Poland */ +#define HID_COUNTRY_PORTUGUESE 0x22 /* Portuguese */ +#define HID_COUNTRY_RUSSIA 0x23 /* Russia */ +#define HID_COUNTRY_SLOVAKIA 0x24 /* Slovakia */ +#define HID_COUNTRY_SPANISH 0x25 /* Spanish */ +#define HID_COUNTRY_SWEDISH 0x26 /* Swedish */ +#define HID_COUNTRY_SWISSFR 0x27 /* Swiss/French */ +#define HID_COUNTRY_SWISSGR 0x28 /* Swiss/German */ +#define HID_COUNTRY_SWITZERLAND 0x29 /* Switzerland */ +#define HID_COUNTRY_TAIWAN 0x30 /* Taiwan */ +#define HID_COUNTRY_TURKISHQ 0x31 /* Turkish-Q */ +#define HID_COUNTRY_UK 0x32 /* UK */ +#define HID_COUNTRY_US 0x33 /* US */ +#define HID_COUNTRY_YUGOSLAVIA 0x34 /* Yugoslavia */ +#define HID_COUNTRY_TURKISHF 0x35 /* Turkish-F */ + +/* HID report items */ +#define HID_REPORT_ITEM_SIZE_MASK 0x03 +#define HID_REPORT_ITEM_SIZE_0 0x00 /* No data follows */ +#define HID_REPORT_ITEM_SIZE_1 0x01 /* 1 byte of data follows */ +#define HID_REPORT_ITEM_SIZE_2 0x02 /* 2 bytes of data follow */ +#define HID_REPORT_ITEM_SIZE_4 0x03 /* 4 bytes of data follow */ +#define HID_REPORT_ITEM_TYPE_MASK 0x0c +#define HID_REPORT_ITEM_TYPE_MAIN 0x00 +#define HID_REPORT_ITEM_TYPE_GLOBAL 0x04 +#define HID_REPORT_ITEM_TYPE_LOCAL 0x08 +#define HID_REPORT_ITEM_TAG_MASK 0xf0 + +/* Main Items (HID 6.2.2.4) */ +#define HID_MAIN_ITEM_CONSTANT (1 << 0) /* Constant(1) vs Data(0) */ +#define HID_MAIN_ITEM_VARIABLE (1 << 1) /* Variable(1) vs Array(0) */ +#define HID_MAIN_ITEM_RELATIVE (1 << 2) /* Relative(1) vs Absolute(0) */ +#define HID_MAIN_ITEM_WRAP (1 << 3) /* Wrap(1) vs No Wrap(0) */ +#define HID_MAIN_ITEM_NONLINEAR (1 << 4) /* Non Linear(1) vs Linear(0) */ +#define HID_MAIN_ITEM_NOPREFERRED (1 << 5) /* No Preferred (1) vs Preferred State(0) */ +#define HID_MAIN_ITEM_NULLSTATE (1 << 6) /* Null state(1) vs No Null position(0) */ +#define HID_MAIN_ITEM_VOLATILE (1 << 7) /* Volatile(1) vs Non volatile(0) */ +#define HID_MAIN_ITEM_BUFFEREDBYTES (1 << 8) /* Buffered Bytes(1) vs Bit Field(0) */ + +#define HID_MAIN_ITEM_SIZE(pfx) ((pfx)&HID_REPORT_ITEM_SIZE_MASK) +#define HID_MAIN_ITEM_INPUT_PREFIX 0x80 +#define HID_MAIN_ITEM_INPUT_CONSTANT HID_MAIN_ITEM_CONSTANT +#define HID_MAIN_ITEM_INPUT_VARIABLE HID_MAIN_ITEM_VARIABLE +#define HID_MAIN_ITEM_INPUT_RELATIVE HID_MAIN_ITEM_RELATIVE +#define HID_MAIN_ITEM_INPUT_WRAP HID_MAIN_ITEM_WRAP +#define HID_MAIN_ITEM_INPUT_NONLINEAR HID_MAIN_ITEM_NONLINEAR +#define HID_MAIN_ITEM_INPUT_NOPREFERRED HID_MAIN_ITEM_NOPREFERRED +#define HID_MAIN_ITEM_INPUT_NULLSTATE HID_MAIN_ITEM_NULLSTATE +#define HID_MAIN_ITEM_INPUT_BUFFEREDBYTES HID_MAIN_ITEM_BUFFEREDBYTES + +#define HID_MAIN_ITEM_OUTPUT_PREFIX 0x90 +#define HID_MAIN_ITEM_OUTPUT_CONSTANT HID_MAIN_ITEM_CONSTANT +#define HID_MAIN_ITEM_OUTPUT_VARIABLE HID_MAIN_ITEM_VARIABLE +#define HID_MAIN_ITEM_OUTPUT_RELATIVE HID_MAIN_ITEM_RELATIVE +#define HID_MAIN_ITEM_OUTPUT_WRAP HID_MAIN_ITEM_WRAP +#define HID_MAIN_ITEM_OUTPUT_NONLINEAR HID_MAIN_ITEM_NONLINEAR +#define HID_MAIN_ITEM_OUTPUT_NOPREFERRED HID_MAIN_ITEM_NOPREFERRED +#define HID_MAIN_ITEM_OUTPUT_NULLSTATE HID_MAIN_ITEM_NULLSTATE +#define HID_MAIN_ITEM_OUTPUT_VOLATILE HID_MAIN_ITEM_VOLATILE +#define HID_MAIN_ITEM_OUTPUT_BUFFEREDBYTES HID_MAIN_ITEM_BUFFEREDBYTES + +#define HID_MAIN_ITEM_FEATURE_PREFIX 0xb0 +#define HID_MAIN_ITEM_FEATURE_CONSTANT HID_MAIN_ITEM_CONSTANT +#define HID_MAIN_ITEM_FEATURE_VARIABLE HID_MAIN_ITEM_VARIABLE +#define HID_MAIN_ITEM_FEATURE_RELATIVE HID_MAIN_ITEM_RELATIVE +#define HID_MAIN_ITEM_FEATURE_WRAP HID_MAIN_ITEM_WRAP +#define HID_MAIN_ITEM_FEATURE_NONLINEAR HID_MAIN_ITEM_NONLINEAR +#define HID_MAIN_ITEM_FEATURE_NOPREFERRED HID_MAIN_ITEM_NOPREFERRED +#define HID_MAIN_ITEM_FEATURE_NULLSTATE HID_MAIN_ITEM_NULLSTATE +#define HID_MAIN_ITEM_FEATURE_VOLATILE HID_MAIN_ITEM_VOLATILE +#define HID_MAIN_ITEM_FEATURE_BUFFEREDBYTES HID_MAIN_ITEM_BUFFEREDBYTES + +#define HID_MAIN_ITEM_COLLECTION_PREFIX 0xa0 +#define HID_MAIN_ITEM_COLLECTION_PHYSICAL 0x00 /* Physical (group of axes) */ +#define HID_MAIN_ITEM_COLLECTION_APPL 0x01 /* Application (mouse, keyboard) */ +#define HID_MAIN_ITEM_COLLECTION_LOGICAL 0x02 /* Logical (interrelated data) */ +#define HID_MAIN_ITEM_COLLECTION_REPORT 0x03 /* Report */ +#define HID_MAIN_ITEM_COLLECTION_ARRAY 0x04 /* Named Array */ +#define HID_MAIN_ITEM_COLLECTION_SWITCH 0x05 /* Usage Switch */ +#define HID_MAIN_ITEM_COLLECTION_MODIFIER 0x06 /* Usage Modifier */ +#define HID_MAIN_ITEM_ENDCOLLECTION_PREFIX 0xc0 + +/* Global Items (HID 6.2.2.7) */ +#define HID_GLOBAL_ITEM_SIZE(pfx) ((pfx)&HID_REPORT_ITEM_SIZE_MASK) +#define HID_GLOBAL_ITEM_USAGEPAGE_PREFIX 0x04 /* Usage Page */ +#define HID_GLOBAL_ITEM_LOGICALMIN_PREFIX 0x14 /* Logical Minimum */ +#define HID_GLOBAL_ITEM_LOGICALMAX_PREFIX 0x24 /* Logical Maximum */ +#define HID_GLOBAL_ITEM_PHYSICALMIN_PREFIX 0x34 /* Physical Minimum */ +#define HID_GLOBAL_ITEM_PHYSMICALAX_PREFIX 0x44 /* Physical Maximum */ +#define HID_GLOBAL_ITEM_UNITEXP_PREFIX 0x54 /* Unit Exponent */ +#define HID_GLOBAL_ITEM_UNIT_PREFIX 0x64 /* Unit */ +#define HID_GLOBAL_ITEM_REPORTSIZE_PREFIX 0x74 /* Report Size */ +#define HID_GLOBAL_ITEM_REPORTID_PREFIX 0x84 /* Report ID */ +#define HID_GLOBAL_ITEM_REPORTCOUNT_PREFIX 0x94 /* Report Count */ +#define HID_GLOBAL_ITEM_PUSH_PREFIX 0xa4 /* Push */ +#define HID_GLOBAL_ITEM_POP_PREFIX 0xb4 /* Pop */ + +/* Local Items (HID 6.2.2.8) */ +#define HID_LOCAL_ITEM_SIZE(pfx) ((pfx)&HID_REPORT_ITEM_SIZE_MASK) +#define HID_LOCAL_ITEM_USAGE_PREFIX 0x08 /* Usage */ +#define HID_LOCAL_ITEM_USAGEMIN_PREFIX 0x18 /* Usage Minimum */ +#define HID_LOCAL_ITEM_USAGEMAX_PREFIX 0x28 /* Usage Maximum */ +#define HID_LOCAL_ITEM_DESIGNATORIDX_PREFIX 0x38 /* Designator Index */ +#define HID_LOCAL_ITEM_DESIGNATORMIN_PREFIX 0x48 /* Designator Minimum */ +#define HID_LOCAL_ITEM_DESIGNATORMAX_PREFIX 0x58 /* Designator Maximum */ +#define HID_LOCAL_ITEM_STRINGIDX_PREFIX 0x78 /* String Index */ +#define HID_LOCAL_ITEM_STRINGMIN_PREFIX 0x88 /* String Minimum */ +#define HID_LOCAL_ITEM_STRINGMAX_PREFIX 0x98 /* xx */ +#define HID_LOCAL_ITEM_DELIMITER_PREFIX 0xa8 /* Delimiter */ + +/* Modifier Keys (HID 8.3) */ +#define HID_MODIFER_LCTRL (1 << 0) /* Left Ctrl */ +#define HID_MODIFER_LSHIFT (1 << 1) /* Left Shift */ +#define HID_MODIFER_LALT (1 << 2) /* Left Alt */ +#define HID_MODIFER_LGUI (1 << 3) /* Left GUI */ +#define HID_MODIFER_RCTRL (1 << 4) /* Right Ctrl */ +#define HID_MODIFER_RSHIFT (1 << 5) /* Right Shift */ +#define HID_MODIFER_RALT (1 << 6) /* Right Alt */ +#define HID_MODIFER_RGUI (1 << 7) /* Right GUI */ + +/* Keyboard output report (1 byte) (HID B.1) */ +#define HID_KBD_OUTPUT_REPORT_NUMLOCK (1 << 0) +#define HID_KBD_OUTPUT_REPORT_CAPSLOCK (1 << 1) +#define HID_KBD_OUTPUT_REPORT_SCROLLLOCK (1 << 2) +#define HID_KBD_OUTPUT_REPORT_COMPOSE (1 << 3) +#define HID_KBD_OUTPUT_REPORT_KANA (1 << 4) + +/* Mouse input report (HID B.2) */ +#define HID_MOUSE_INPUT_REPORT_BUTTON1 (1 << 0) +#define HID_MOUSE_INPUT_REPORT_BUTTON2 (1 << 1) +#define HID_MOUSE_INPUT_REPORT_BUTTON3 (1 << 2) +#define HID_MOUSE_INPUT_REPORT_BUTTON_MASK (7) + +#define HID_MOUSE_INPUT_BUTTON_LEFT (1 << 0) +#define HID_MOUSE_INPUT_BUTTON_RIGHT (1 << 1) +#define HID_MOUSE_INPUT_BUTTON_MIDDLE (1 << 2) +#define HID_MOUSE_INPUT_BUTTON_BACKWARD (1 << 3) +#define HID_MOUSE_INPUT_BUTTON_FORWARD (1 << 4) + +/* Joystick input report (4 bytes) (HID D.1) */ +#define HID_JS_INPUT_REPORT_HATSWITCH_SHIFT (0) +#define HID_JS_INPUT_REPORT_HATSWITCH_MASK (15 << HID_JSIN_HATSWITCH_SHIFT) +#define HID_JS_INPUT_REPORT_BUTTON1 (1 << 4) +#define HID_JS_INPUT_REPORT_BUTTON2 (1 << 5) +#define HID_JS_INPUT_REPORT_BUTTON3 (1 << 6) +#define HID_JS_INPUT_REPORT_BUTTON4 (1 << 7) + +/* Usage pages (HuT 3) */ +#define HID_USAGE_PAGE_UNDEFINED 0x00 /* Undefined */ +#define HID_USAGE_PAGE_GENERIC_DCTRL 0x01 /* Generic Desktop Controls */ +#define HID_USAGE_PAGE_SIMCTRL 0x02 /* Simulation Controls */ +#define HID_USAGE_PAGE_VRCTRL 0x03 /* VR Controls */ +#define HID_USAGE_PAGE_SPORTCTRL 0x04 /* Sport Controls */ +#define HID_USAGE_PAGE_GAMECTRL 0x05 /* Game Controls */ +#define HID_USAGE_PAGE_GENERIC_DEVCTRL 0x06 /* Generic Device Controls */ +#define HID_USAGE_PAGE_KBD 0x07 /* Keyboard/Keypad */ +#define HID_USAGE_PAGE_LEDS 0x08 /* LEDs */ +#define HID_USAGE_PAGE_BUTTON 0x09 /* Button */ +#define HID_USAGE_PAGE_ORDINAL 0x0a /* Ordinal */ +#define HID_USAGE_PAGE_TELEPHONY 0x0b /* Telephony */ +#define HID_USAGE_PAGE_CONSUMER 0x0c /* Consumer */ +#define HID_USAGE_PAGE_DIGITIZER 0x0d /* Digitizer */ + /* 0x0e Reserved */ +#define HID_USAGE_PAGE_PIDPAGE 0x0f /* PID Page Physical Interface Device */ +#define HID_USAGE_PAGE_UNICODE 0x10 /* Unicode */ + /* 0x11-13 Reserved */ +#define HID_USAGE_PAGE_ALPHA_DISPLAY 0x14 /* Alphanumeric Display */ + /* 0x15-3f Reserved */ +#define HID_USAGE_PAGE_MEDICAL 0x40 /* Medical Instruments */ + /* 0x41-7f Reserved */ + /* 0x80-83 Monitor Devices */ + /* 0x84-87 Power Devices */ + /* 0x88-8b Reserved */ +#define HID_USAGE_PAGE_BARCODE_SCANNER 0x8c /* Bar Code Scanner page */ +#define HID_USAGE_PAGE_SCALE 0x8d /* Scale page */ +#define HID_USAGE_PAGE_MSR 0x8e /* Magnetic Stripe Reading (MSR) Devices */ +#define HID_USAGE_PAGE_POS 0x8f /* Point of Sale devices */ +#define HID_USAGE_PAGE_CAMERA_CTRL 0x90 /* Camera Control Page */ + +/* Generic Desktop Page Usage IDs (HuT 4) */ +#define HID_DESKTOP_USAGE_UNDEFINED 0x00 /* Undefined */ +#define HID_DESKTOP_USAGE_POINTER 0x01 /* Pointer */ +#define HID_DESKTOP_USAGE_MOUSE 0x02 /* Mouse */ + /* 0x03 Reserved */ +#define HID_DESKTOP_USAGE_JOYSTICK 0x04 /* Joystick */ +#define HID_DESKTOP_USAGE_GAMEPAD 0x05 /* Game Pad */ +#define HID_DESKTOP_USAGE_KEYBOARD 0x06 /* Keyboard */ +#define HID_DESKTOP_USAGE_KEYPAD 0x07 /* Keypad */ +#define HID_DESKTOP_USAGE_MULTIAXIS 0x08 /* Multi-axis Controller */ +#define HID_DESKTOP_USAGE_TABLET 0x09 /* Tablet PC System Controls */ + /* 0x0a-2f Reserved */ +#define HID_DESKTOP_USAGE_X 0x30 /* X */ +#define HID_DESKTOP_USAGE_Y 0x31 /* Y */ +#define HID_DESKTOP_USAGE_Z 0x32 /* Z */ +#define HID_DESKTOP_USAGE_RX 0x33 /* Rx */ +#define HID_DESKTOP_USAGE_RY 0x34 /* Ry */ +#define HID_DESKTOP_USAGE_RZ 0x35 /* Rz */ +#define HID_DESKTOP_USAGE_SLIDER 0x36 /* Slider */ +#define HID_DESKTOP_USAGE_DIAL 0x37 /* Dial */ +#define HID_DESKTOP_USAGE_WHEEL 0x38 /* Wheel */ +#define HID_DESKTOP_USAGE_HATSWITCH 0x39 /* Hat switch */ +#define HID_DESKTOP_USAGE_COUNTED 0x3a /* Counted Buffer */ +#define HID_DESKTOP_USAGE_BYTECOUNT 0x3b /* Byte Count */ +#define HID_DESKTOP_USAGE_MOTION 0x3c /* Motion Wakeup */ +#define HID_DESKTOP_USAGE_START 0x3d /* Start */ +#define HID_DESKTOP_USAGE_SELECT 0x3e /* Select */ + /* 0x3f Reserved */ +#define HID_DESKTOP_USAGE_VX 0x40 /* Vx */ +#define HID_DESKTOP_USAGE_VY 0x41 /* Vy */ +#define HID_DESKTOP_USAGE_VZ 0x42 /* Vz */ +#define HID_DESKTOP_USAGE_VBRX 0x43 /* Vbrx */ +#define HID_DESKTOP_USAGE_VBRY 0x44 /* Vbry */ +#define HID_DESKTOP_USAGE_VBRZ 0x45 /* Vbrz */ +#define HID_DESKTOP_USAGE_VNO 0x46 /* Vno */ +#define HID_DESKTOP_USAGE_FEATURE 0x47 /* Feature Notification */ +#define HID_DESKTOP_USAGE_RESOLUTION 0x48 /* Resolution Multiplier */ + /* 0x49-7f Reserved */ +#define HID_DESKTOP_USAGE_CONTROL 0x80 /* System Control */ +#define HID_DESKTOP_USAGE_POWERDOWN 0x81 /* System Power Down */ +#define HID_DESKTOP_USAGE_SLEEP 0x82 /* System Sleep */ +#define HID_DESKTOP_USAGE_WAKEUP 0x83 /* System Wake Up */ +#define HID_DESKTOP_USAGE_CONTEXT_MENU 0x84 /* System Context Menu */ +#define HID_DESKTOP_USAGE_MAIN_MENU 0x85 /* System Main Menu */ +#define HID_DESKTOP_USAGE_APP_MENU 0x86 /* System App Menu */ +#define HID_DESKTOP_USAGE_MENU_HELP 0x87 /* System Menu Help */ +#define HID_DESKTOP_USAGE_MENU_EXIT 0x88 /* System Menu Exit */ +#define HID_DESKTOP_USAGE_MENU_SELECT 0x89 /* System Menu Select */ +#define HID_DESKTOP_USAGE_MENU_RIGHT 0x8a /* System Menu Right */ +#define HID_DESKTOP_USAGE_MENU_LEFT 0x8b /* System Menu Left */ +#define HID_DESKTOP_USAGE_MENU_UP 0x8c /* System Menu Up */ +#define HID_DESKTOP_USAGE_MENU_DOWN 0x8d /* System Menu Down */ +#define HID_DESKTOP_USAGE_COLD_RESTART 0x8e /* System Cold Restart */ +#define HID_DESKTOP_USAGE_WARM_RESTART 0x8f /* System Warm Restart */ +#define HID_DESKTOP_USAGE_DPAD_UP 0x90 /* D-pad Up */ +#define HID_DESKTOP_USAGE_DPAD_DOWN 0x91 /* D-pad Down */ +#define HID_DESKTOP_USAGE_DPAD_RIGHT 0x92 /* D-pad Right */ +#define HID_DESKTOP_USAGE_DPAD_LEFT 0x93 /* D-pad Left */ + /* 0x94-9f Reserved */ +#define HID_DESKTOP_USAGE_DOCK 0xa0 /* System Dock */ +#define HID_DESKTOP_USAGE_UNDOCK 0xa1 /* System Undock */ +#define HID_DESKTOP_USAGE_SETUP 0xa2 /* System Setup */ +#define HID_DESKTOP_USAGE_BREAK 0xa3 /* System Break */ +#define HID_DESKTOP_USAGE_DEBUG_BREAK 0xa4 /* System Debugger Break */ +#define HID_DESKTOP_USAGE_APP_BREAK 0xa5 /* Application Break */ +#define HID_DESKTOP_USAGE_APP_DEBUG_BREAK 0xa6 /* Application Debugger Break */ +#define HID_DESKTOP_USAGE_MUTE 0xa7 /* System Speaker Mute */ +#define HID_DESKTOP_USAGE_HIBERNATE 0xa8 /* System Hibernate */ + /* 0xa9-af Reserved */ +#define HID_DESKTOP_USAGE_DISPLAY_INVERT 0xb0 /* System Display Invert */ +#define HID_DESKTOP_USAGE_DISPALY_INTERNAL 0xb1 /* System Display Internal */ +#define HID_DESKTOP_USAGE_DISPLAY_EXTERNAL 0xb2 /* System Display External */ +#define HID_DESKTOP_USAGE_DISPLAY_BOTH 0xb3 /* System Display Both */ +#define HID_DESKTOP_USAGE_DISPLAY_DUAL 0xb4 /* System Display Dual */ +#define HID_DESKTOP_USAGE_DISPLAY_TOGGLE 0xb5 /* System Display Toggle Int/Ext */ +#define HID_DESKTOP_USAGE_DISPLAY_SWAP 0xb6 /* System Display Swap */ +#define HID_DESKTOP_USAGE_ 0xb7 /* System Display LCD Autoscale */ + /* 0xb8-ffff Reserved */ + +/* Keyboard usage IDs (HuT 10) */ +#define HID_KBD_USAGE_NONE 0x00 /* Reserved (no event indicated) */ +#define HID_KBD_USAGE_ERRORROLLOVER 0x01 /* Keyboard ErrorRollOver */ +#define HID_KBD_USAGE_POSTFAIL 0x02 /* Keyboard POSTFail */ +#define HID_KBD_USAGE_ERRUNDEF 0x03 /* Keyboard ErrorUndefined */ +#define HID_KBD_USAGE_A 0x04 /* Keyboard a or A (B-Z follow) */ +#define HID_KBD_USAGE_1 0x1e /* Keyboard 1 (2-9 follow) */ +#define HID_KBD_USAGE_EXCLAM 0x1e /* Keyboard 1 and ! */ +#define HID_KBD_USAGE_AT 0x1f /* Keyboard 2 and @ */ +#define HID_KBD_USAGE_POUND 0x20 /* Keyboard 3 and # */ +#define HID_KBD_USAGE_DOLLAR 0x21 /* Keyboard 4 and $ */ +#define HID_KBD_USAGE_PERCENT 0x22 /* Keyboard 5 and % */ +#define HID_KBD_USAGE_CARAT 0x23 /* Keyboard 6 and ^ */ +#define HID_KBD_USAGE_AMPERSAND 0x24 /* Keyboard 7 and & */ +#define HID_KBD_USAGE_ASTERISK 0x25 /* Keyboard 8 and * */ +#define HID_KBD_USAGE_LPAREN 0x26 /* Keyboard 9 and ( */ +#define HID_KBD_USAGE_0 0x27 /* Keyboard 0 and ) */ +#define HID_KBD_USAGE_RPAREN 0x27 /* Keyboard 0 and ) */ +#define HID_KBD_USAGE_ENTER 0x28 /* Keyboard Return (ENTER) */ +#define HID_KBD_USAGE_ESCAPE 0x29 /* Keyboard ESCAPE */ +#define HID_KBD_USAGE_DELETE 0x2a /* Keyboard DELETE (Backspace) */ +#define HID_KBD_USAGE_TAB 0x2b /* Keyboard Tab */ +#define HID_KBD_USAGE_SPACE 0x2c /* Keyboard Spacebar */ +#define HID_KBD_USAGE_HYPHEN 0x2d /* Keyboard - and (underscore) */ +#define HID_KBD_USAGE_UNDERSCORE 0x2d /* Keyboard - and (underscore) */ +#define HID_KBD_USAGE_EQUAL 0x2e /* Keyboard = and + */ +#define HID_KBD_USAGE_PLUS 0x2e /* Keyboard = and + */ +#define HID_KBD_USAGE_LBRACKET 0x2f /* Keyboard [ and { */ +#define HID_KBD_USAGE_LBRACE 0x2f /* Keyboard [ and { */ +#define HID_KBD_USAGE_RBRACKET 0x30 /* Keyboard ] and } */ +#define HID_KBD_USAGE_RBRACE 0x30 /* Keyboard ] and } */ +#define HID_KBD_USAGE_BSLASH 0x31 /* Keyboard \ and | */ +#define HID_KBD_USAGE_VERTBAR 0x31 /* Keyboard \ and | */ +#define HID_KBD_USAGE_NONUSPOUND 0x32 /* Keyboard Non-US # and ~ */ +#define HID_KBD_USAGE_TILDE 0x32 /* Keyboard Non-US # and ~ */ +#define HID_KBD_USAGE_SEMICOLON 0x33 /* Keyboard ; and : */ +#define HID_KBD_USAGE_COLON 0x33 /* Keyboard ; and : */ +#define HID_KBD_USAGE_SQUOTE 0x34 /* Keyboard ' and " */ +#define HID_KBD_USAGE_DQUOUTE 0x34 /* Keyboard ' and " */ +#define HID_KBD_USAGE_GACCENT 0x35 /* Keyboard Grave Accent and Tilde */ +#define HID_KBD_USAGE_GTILDE 0x35 /* Keyboard Grave Accent and Tilde */ +#define HID_KBD_USAGE_COMMON 0x36 /* Keyboard , and < */ +#define HID_KBD_USAGE_LT 0x36 /* Keyboard , and < */ +#define HID_KBD_USAGE_PERIOD 0x37 /* Keyboard . and > */ +#define HID_KBD_USAGE_GT 0x37 /* Keyboard . and > */ +#define HID_KBD_USAGE_DIV 0x38 /* Keyboard / and ? */ +#define HID_KBD_USAGE_QUESTION 0x38 /* Keyboard / and ? */ +#define HID_KBD_USAGE_CAPSLOCK 0x39 /* Keyboard Caps Lock */ +#define HID_KBD_USAGE_F1 0x3a /* Keyboard F1 */ +#define HID_KBD_USAGE_F2 0x3b /* Keyboard F2 */ +#define HID_KBD_USAGE_F3 0x3c /* Keyboard F3 */ +#define HID_KBD_USAGE_F4 0x3d /* Keyboard F4 */ +#define HID_KBD_USAGE_F5 0x3e /* Keyboard F5 */ +#define HID_KBD_USAGE_F6 0x3f /* Keyboard F6 */ +#define HID_KBD_USAGE_F7 0x40 /* Keyboard F7 */ +#define HID_KBD_USAGE_F8 0x41 /* Keyboard F8 */ +#define HID_KBD_USAGE_F9 0x42 /* Keyboard F9 */ +#define HID_KBD_USAGE_F10 0x43 /* Keyboard F10 */ +#define HID_KBD_USAGE_F11 0x44 /* Keyboard F11 */ +#define HID_KBD_USAGE_F12 0x45 /* Keyboard F12 */ +#define HID_KBD_USAGE_PRINTSCN 0x46 /* Keyboard PrintScreen */ +#define HID_KBD_USAGE_SCROLLLOCK 0x47 /* Keyboard Scroll Lock */ +#define HID_KBD_USAGE_PAUSE 0x48 /* Keyboard Pause */ +#define HID_KBD_USAGE_INSERT 0x49 /* Keyboard Insert */ +#define HID_KBD_USAGE_HOME 0x4a /* Keyboard Home */ +#define HID_KBD_USAGE_PAGEUP 0x4b /* Keyboard PageUp */ +#define HID_KBD_USAGE_DELFWD 0x4c /* Keyboard Delete Forward */ +#define HID_KBD_USAGE_END 0x4d /* Keyboard End */ +#define HID_KBD_USAGE_PAGEDOWN 0x4e /* Keyboard PageDown */ +#define HID_KBD_USAGE_RIGHT 0x4f /* eyboard RightArrow */ +#define HID_KBD_USAGE_LEFT 0x50 /* Keyboard LeftArrow */ +#define HID_KBD_USAGE_DOWN 0x51 /* Keyboard DownArrow */ +#define HID_KBD_USAGE_UP 0x52 /* Keyboard UpArrow */ +#define HID_KBD_USAGE_KPDNUMLOCK 0x53 /* Keypad Num Lock and Clear */ +#define HID_KBD_USAGE_KPDNUMLOCKCLEAR 0x53 /* Keypad Num Lock and Clear */ +#define HID_KBD_USAGE_KPDDIV 0x54 /* Keypad / */ +#define HID_KBD_USAGE_KPDMUL 0x55 /* Keypad * */ +#define HID_KBD_USAGE_KPDHMINUS 0x56 /* Keypad - */ +#define HID_KBD_USAGE_KPDPLUS 0x57 /* Keypad + */ +#define HID_KBD_USAGE_KPDEMTER 0x58 /* Keypad ENTER */ +#define HID_KBD_USAGE_KPD1 0x59 /* Keypad 1 (2-9 follow) */ +#define HID_KBD_USAGE_KPDEND 0x59 /* Keypad 1 and End */ +#define HID_KBD_USAGE_KPDDOWN 0x5a /* Keypad 2 and Down Arrow */ +#define HID_KBD_USAGE_KPDPAGEDN 0x5b /* Keypad 3 and PageDn */ +#define HID_KBD_USAGE_KPDLEFT 0x5c /* Keypad 4 and Left Arrow */ +#define HID_KBD_USAGE_KPDRIGHT 0x5e /* Keypad 6 and Right Arrow */ +#define HID_KBD_USAGE_KPDHOME 0x5f /* Keypad 7 and Home */ +#define HID_KBD_USAGE_KPDUP 0x60 /* Keypad 8 and Up Arrow */ +#define HID_KBD_USAGE_KPDPAGEUP 0x61 /* Keypad 9 and PageUp */ +#define HID_KBD_USAGE_KPD0 0x62 /* Keypad 0 and Insert */ +#define HID_KBD_USAGE_KPDINSERT 0x62 /* Keypad 0 and Insert */ +#define HID_KBD_USAGE_KPDDECIMALPT 0x63 /* Keypad . and Delete */ +#define HID_KBD_USAGE_KPDDELETE 0x63 /* Keypad . and Delete */ +#define HID_KBD_USAGE_NONSLASH 0x64 /* Keyboard Non-US \ and | */ +#define HID_KBD_USAGE_NONUSVERT 0x64 /* Keyboard Non-US \ and | */ +#define HID_KBD_USAGE_APPLICATION 0x65 /* Keyboard Application */ +#define HID_KBD_USAGE_POWER 0x66 /* Keyboard Power */ +#define HID_KBD_USAGE_KPDEQUAL 0x67 /* Keypad = */ +#define HID_KBD_USAGE_F13 0x68 /* Keyboard F13 */ +#define HID_KBD_USAGE_F14 0x69 /* Keyboard F14 */ +#define HID_KBD_USAGE_F15 0x6a /* Keyboard F15 */ +#define HID_KBD_USAGE_F16 0x6b /* Keyboard F16 */ +#define HID_KBD_USAGE_F17 0x6c /* Keyboard F17 */ +#define HID_KBD_USAGE_F18 0x6d /* Keyboard F18 */ +#define HID_KBD_USAGE_F19 0x6e /* Keyboard F19 */ +#define HID_KBD_USAGE_F20 0x6f /* Keyboard F20 */ +#define HID_KBD_USAGE_F21 0x70 /* Keyboard F21 */ +#define HID_KBD_USAGE_F22 0x71 /* Keyboard F22 */ +#define HID_KBD_USAGE_F23 0x72 /* Keyboard F23 */ +#define HID_KBD_USAGE_F24 0x73 /* Keyboard F24 */ +#define HID_KBD_USAGE_EXECUTE 0x74 /* Keyboard Execute */ +#define HID_KBD_USAGE_HELP 0x75 /* Keyboard Help */ +#define HID_KBD_USAGE_MENU 0x76 /* Keyboard Menu */ +#define HID_KBD_USAGE_SELECT 0x77 /* Keyboard Select */ +#define HID_KBD_USAGE_STOP 0x78 /* Keyboard Stop */ +#define HID_KBD_USAGE_AGAIN 0x79 /* Keyboard Again */ +#define HID_KBD_USAGE_UNDO 0x7a /* Keyboard Undo */ +#define HID_KBD_USAGE_CUT 0x7b /* Keyboard Cut */ +#define HID_KBD_USAGE_COPY 0x7c /* Keyboard Copy */ +#define HID_KBD_USAGE_PASTE 0x7d /* Keyboard Paste */ +#define HID_KBD_USAGE_FIND 0x7e /* Keyboard Find */ +#define HID_KBD_USAGE_MUTE 0x7f /* Keyboard Mute */ +#define HID_KBD_USAGE_VOLUP 0x80 /* Keyboard Volume Up */ +#define HID_KBD_USAGE_VOLDOWN 0x81 /* Keyboard Volume Down */ +#define HID_KBD_USAGE_LCAPSLOCK 0x82 /* Keyboard Locking Caps Lock */ +#define HID_KBD_USAGE_LNUMLOCK 0x83 /* Keyboard Locking Num Lock */ +#define HID_KBD_USAGE_LSCROLLLOCK 0x84 /* Keyboard Locking Scroll Lock */ +#define HID_KBD_USAGE_KPDCOMMA 0x85 /* Keypad Comma */ +#define HID_KBD_USAGE_KPDEQUALSIGN 0x86 /* Keypad Equal Sign */ +#define HID_KBD_USAGE_INTERNATIONAL1 0x87 /* Keyboard International 1 */ +#define HID_KBD_USAGE_INTERNATIONAL2 0x88 /* Keyboard International 2 */ +#define HID_KBD_USAGE_INTERNATIONAL3 0x89 /* Keyboard International 3 */ +#define HID_KBD_USAGE_INTERNATIONAL4 0x8a /* Keyboard International 4 */ +#define HID_KBD_USAGE_INTERNATIONAL5 0x8b /* Keyboard International 5 */ +#define HID_KBD_USAGE_INTERNATIONAL6 0x8c /* Keyboard International 6 */ +#define HID_KBD_USAGE_INTERNATIONAL7 0x8d /* Keyboard International 7 */ +#define HID_KBD_USAGE_INTERNATIONAL8 0x8e /* Keyboard International 8 */ +#define HID_KBD_USAGE_INTERNATIONAL9 0x8f /* Keyboard International 9 */ +#define HID_KBD_USAGE_LANG1 0x90 /* Keyboard LANG1 */ +#define HID_KBD_USAGE_LANG2 0x91 /* Keyboard LANG2 */ +#define HID_KBD_USAGE_LANG3 0x92 /* Keyboard LANG3 */ +#define HID_KBD_USAGE_LANG4 0x93 /* Keyboard LANG4 */ +#define HID_KBD_USAGE_LANG5 0x94 /* Keyboard LANG5 */ +#define HID_KBD_USAGE_LANG6 0x95 /* Keyboard LANG6 */ +#define HID_KBD_USAGE_LANG7 0x96 /* Keyboard LANG7 */ +#define HID_KBD_USAGE_LANG8 0x97 /* Keyboard LANG8 */ +#define HID_KBD_USAGE_LANG9 0x98 /* Keyboard LANG9 */ +#define HID_KBD_USAGE_ALTERASE 0x99 /* Keyboard Alternate Erase */ +#define HID_KBD_USAGE_SYSREQ 0x9a /* Keyboard SysReq/Attention */ +#define HID_KBD_USAGE_CANCEL 0x9b /* Keyboard Cancel */ +#define HID_KBD_USAGE_CLEAR 0x9c /* Keyboard Clear */ +#define HID_KBD_USAGE_PRIOR 0x9d /* Keyboard Prior */ +#define HID_KBD_USAGE_RETURN 0x9e /* Keyboard Return */ +#define HID_KBD_USAGE_SEPARATOR 0x9f /* Keyboard Separator */ +#define HID_KBD_USAGE_OUT 0xa0 /* Keyboard Out */ +#define HID_KBD_USAGE_OPER 0xa1 /* Keyboard Oper */ +#define HID_KBD_USAGE_CLEARAGAIN 0xa2 /* Keyboard Clear/Again */ +#define HID_KBD_USAGE_CLRSEL 0xa3 /* Keyboard CrSel/Props */ +#define HID_KBD_USAGE_EXSEL 0xa4 /* Keyboard ExSel */ +#define HID_KBD_USAGE_KPD00 0xb0 /* Keypad 00 */ +#define HID_KBD_USAGE_KPD000 0xb1 /* Keypad 000 */ +#define HID_KBD_USAGE_THOUSEPARATOR 0xb2 /* Thousands Separator */ +#define HID_KBD_USAGE_DECSEPARATOR 0xb3 /* Decimal Separator */ +#define HID_KBD_USAGE_CURRUNIT 0xb4 /* Currency Unit */ +#define HID_KBD_USAGE_CURRSUBUNIT 0xb5 /* Currency Sub-unit */ +#define HID_KBD_USAGE_KPDLPAREN 0xb6 /* Keypad ( */ +#define HID_KBD_USAGE_KPDRPAREN 0xb7 /* Keypad ) */ +#define HID_KBD_USAGE_KPDLBRACE 0xb8 /* Keypad { */ +#define HID_KBD_USAGE_KPDRBRACE 0xb9 /* Keypad } */ +#define HID_KBD_USAGE_KPDTAB 0xba /* Keypad Tab */ +#define HID_KBD_USAGE_KPDBACKSPACE 0xbb /* Keypad Backspace */ +#define HID_KBD_USAGE_KPDA 0xbc /* Keypad A (B-F follow) */ +#define HID_KBD_USAGE_KPDXOR 0xc2 /* Keypad XOR */ +#define HID_KBD_USAGE_KPDEXP 0xc3 /* Keypad ^ */ +#define HID_KBD_USAGE_KPDPERCENT 0xc4 /* Keypad % */ +#define HID_KBD_USAGE_KPDLT 0xc5 /* Keypad < */ +#define HID_KBD_USAGE_KPDGT 0xc6 /* Keypad > */ +#define HID_KBD_USAGE_KPDAMPERSAND 0xc7 /* Keypad & */ +#define HID_KBD_USAGE_KPDAND 0xc8 /* Keypad && */ +#define HID_KBD_USAGE_KPDVERT 0xc9 /* Keypad | */ +#define HID_KBD_USAGE_KPDOR 0xca /* Keypad || */ +#define HID_KBD_USAGE_KPDCOLON 0xcb /* Keypad : */ +#define HID_KBD_USAGE_KPDPOUND 0xcc /* Keypad # */ +#define HID_KBD_USAGE_KPDSPACE 0xcd /* Keypad Space */ +#define HID_KBD_USAGE_KPDAT 0xce /* Keypad @ */ +#define HID_KBD_USAGE_KPDEXCLAM 0xcf /* Keypad ! */ +#define HID_KBD_USAGE_KPDMEMSTORE 0xd0 /* Keypad Memory Store */ +#define HID_KBD_USAGE_KPDMEMRECALL 0xd1 /* Keypad Memory Recall */ +#define HID_KBD_USAGE_KPDMEMCLEAR 0xd2 /* Keypad Memory Clear */ +#define HID_KBD_USAGE_KPDMEMADD 0xd3 /* Keypad Memory Add */ +#define HID_KBD_USAGE_KPDMEMSUB 0xd4 /* Keypad Memory Subtract */ +#define HID_KBD_USAGE_KPDMEMMULT 0xd5 /* Keypad Memory Multiply */ +#define HID_KBD_USAGE_KPDMEMDIV 0xd6 /* Keypad Memory Divide */ +#define HID_KBD_USAGE_KPDPLUSMINUS 0xd7 /* Keypad +/- */ +#define HID_KBD_USAGE_KPDCLEAR 0xd8 /* Keypad Clear */ +#define HID_KBD_USAGE_KPDCLEARENTRY 0xd9 /* Keypad Clear Entry */ +#define HID_KBD_USAGE_KPDBINARY 0xda /* Keypad Binary */ +#define HID_KBD_USAGE_KPDOCTAL 0xdb /* Keypad Octal */ +#define HID_KBD_USAGE_KPDDECIMAL 0xdc /* Keypad Decimal */ +#define HID_KBD_USAGE_KPDHEXADECIMAL 0xdd /* Keypad Hexadecimal */ +#define HID_KBD_USAGE_LCTRL 0xe0 /* Keyboard LeftControl */ +#define HID_KBD_USAGE_LSHIFT 0xe1 /* Keyboard LeftShift */ +#define HID_KBD_USAGE_LALT 0xe2 /* Keyboard LeftAlt */ +#define HID_KBD_USAGE_LGUI 0xe3 /* Keyboard Left GUI */ +#define HID_KBD_USAGE_RCTRL 0xe4 /* Keyboard RightControl */ +#define HID_KBD_USAGE_RSHIFT 0xe5 /* Keyboard RightShift */ +#define HID_KBD_USAGE_RALT 0xe6 /* Keyboard RightAlt */ +#define HID_KBD_USAGE_RGUI 0xe7 /* Keyboard Right GUI */ + +#define HID_KBD_USAGE_MAX 0xe7 + +/* HID Report Definitions */ +struct usb_hid_class_subdescriptor { + uint8_t bDescriptorType; /* Class descriptor type (See 7.1) */ + uint16_t wDescriptorLength; /* Size of the report descriptor */ +} __PACKED; + +struct usb_hid_descriptor { + uint8_t bLength; /* Size of the HID descriptor */ + uint8_t bDescriptorType; /* HID descriptor type */ + uint16_t bcdHID; /* HID class specification release */ + uint8_t bCountryCode; /* Country code */ + uint8_t bNumDescriptors; /* Number of descriptors (>=1) */ + + /* + * Specification says at least one Class Descriptor needs to + * be present (Report Descriptor). + */ + struct usb_hid_class_subdescriptor subdesc[1]; +} __PACKED; + +/* Standard Reports *********************************************************/ + +/* Keyboard input report (8 bytes) (HID B.1) */ +struct usb_hid_kbd_report { + uint8_t modifier; /* Modifier keys. See HID_MODIFER_* definitions */ + uint8_t reserved; + uint8_t key[6]; /* Keycode 1-6 */ +}; + +/* Keyboard output report (1 byte) (HID B.1), + * see HID_KBD_OUTPUT_* definitions + */ + +/* Mouse input report (HID B.2) */ +struct usb_hid_mouse_report { + uint8_t buttons; /* See HID_MOUSE_INPUT_BUTTON_* definitions */ + int8_t xdisp; /* X displacement */ + int8_t ydisp; /* y displacement */ + /* Device specific additional bytes may follow */ + uint8_t wdisp; /* Wheel displacement */ +}; + +/* Joystick input report (1 bytes) (HID D.1) */ +struct usb_hid_js_report { + int8_t xpos; /* X position */ + int8_t ypos; /* X position */ + uint8_t buttons; /* See USBHID_JSIN_* definitions */ + uint8_t throttle; /* Throttle */ +}; + +// clang-format off +#define HID_MOUSE_DESCRIPTOR_LEN (9 + 9 + 7) + +#define HID_MOUSE_DESCRIPTOR_INIT(bInterfaceNumber, bInterfaceSubClass, wItemLength, int_ep, wMaxPacketSize, bInterval) \ + 0x09, /* bLength: Interface Descriptor size */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ \ + bInterfaceNumber, /* bInterfaceNumber: Number of Interface */ \ + 0x00, /* bAlternateSetting: Alternate setting */ \ + 0x01, /* bNumEndpoints */ \ + 0x03, /* bInterfaceClass: HID */ \ + bInterfaceSubClass, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ \ + 0x02, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ \ + 0x00, /* iInterface: Index of string descriptor */ \ + 0x09, /* bLength: HID Descriptor size */ \ + HID_DESCRIPTOR_TYPE_HID, /* bDescriptorType: HID */ \ + 0x11, /* bcdHID: HID Class Spec release number */ \ + 0x01, \ + 0x00, /* bCountryCode: Hardware target country */ \ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ \ + 0x22, /* bDescriptorType */ \ + WBVAL(wItemLength), /* wItemLength: Total length of Report descriptor */ \ + 0x07, /* bLength: Endpoint Descriptor size */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */ \ + int_ep, /* bEndpointAddress: Endpoint Address (IN) */ \ + 0x03, /* bmAttributes: Interrupt endpoint */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize: x Byte max */ \ + bInterval /* bInterval: Polling Interval */ + +#define HID_KEYBOARD_DESCRIPTOR_LEN (9 + 9 + 7) + +#define HID_KEYBOARD_DESCRIPTOR_INIT(bInterfaceNumber, bInterfaceSubClass, wItemLength, int_ep, wMaxPacketSize, bInterval) \ + 0x09, /* bLength: Interface Descriptor size */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ \ + bInterfaceNumber, /* bInterfaceNumber: Number of Interface */ \ + 0x00, /* bAlternateSetting: Alternate setting */ \ + 0x01, /* bNumEndpoints */ \ + 0x03, /* bInterfaceClass: HID */ \ + bInterfaceSubClass, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ \ + 0x01, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ \ + 0x00, /* iInterface: Index of string descriptor */ \ + 0x09, /* bLength: HID Descriptor size */ \ + HID_DESCRIPTOR_TYPE_HID, /* bDescriptorType: HID */ \ + 0x11, /* bcdHID: HID Class Spec release number */ \ + 0x01, \ + 0x00, /* bCountryCode: Hardware target country */ \ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ \ + 0x22, /* bDescriptorType */ \ + WBVAL(wItemLength), /* wItemLength: Total length of Report descriptor */ \ + 0x07, /* bLength: Endpoint Descriptor size */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */ \ + int_ep, /* bEndpointAddress: Endpoint Address (IN) */ \ + 0x03, /* bmAttributes: Interrupt endpoint */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize: x Byte max */ \ + bInterval /* bInterval: Polling Interval */ + +#define HID_CUSTOM_INOUT_DESCRIPTOR_LEN (9 + 9 + 7 + 7) + +#define HID_CUSTOM_INOUT_DESCRIPTOR_INIT(bInterfaceNumber, bInterfaceSubClass, wItemLength, in_ep, out_ep,wMaxPacketSize, bInterval) \ + 0x09, /* bLength: Interface Descriptor size */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType: Interface descriptor type */ \ + bInterfaceNumber, /* bInterfaceNumber: Number of Interface */ \ + 0x00, /* bAlternateSetting: Alternate setting */ \ + 0x02, /* bNumEndpoints */ \ + 0x03, /* bInterfaceClass: HID */ \ + bInterfaceSubClass, /* bInterfaceSubClass : 1=BOOT, 0=no boot */ \ + 0x00, /* nInterfaceProtocol : 0=none, 1=keyboard, 2=mouse */ \ + 0x00, /* iInterface: Index of string descriptor */ \ + 0x09, /* bLength: HID Descriptor size */ \ + HID_DESCRIPTOR_TYPE_HID, /* bDescriptorType: HID */ \ + 0x11, /* bcdHID: HID Class Spec release number */ \ + 0x01, \ + 0x00, /* bCountryCode: Hardware target country */ \ + 0x01, /* bNumDescriptors: Number of HID class descriptors to follow */ \ + 0x22, /* bDescriptorType */ \ + WBVAL(wItemLength), /* wItemLength: Total length of Report descriptor */ \ + 0x07, /* bLength: Endpoint Descriptor size */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */ \ + in_ep, /* bEndpointAddress: Endpoint Address (IN) */ \ + 0x03, /* bmAttributes: Interrupt endpoint */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize: x Byte max */ \ + bInterval, /* bInterval: Polling Interval */ \ + 0x07, /* bLength: Endpoint Descriptor size */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: */ \ + out_ep, /* bEndpointAddress: Endpoint Address (IN) */ \ + 0x03, /* bmAttributes: Interrupt endpoint */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize: x Byte max */ \ + bInterval /* bInterval: Polling Interval */ +// clang-format on + +#endif /* USB_HID_H */ diff --git a/ch32v103_hallarray_controller/3rdparty/CherryUSB/class/hid/usbd_hid.c b/ch32v103_hallarray_controller/3rdparty/CherryUSB/class/hid/usbd_hid.c new file mode 100644 index 0000000..fed749f --- /dev/null +++ b/ch32v103_hallarray_controller/3rdparty/CherryUSB/class/hid/usbd_hid.c @@ -0,0 +1,126 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usbd_hid.h" + +static int hid_class_interface_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + USB_LOG_DBG("HID Class request: " + "bRequest 0x%02x\r\n", + setup->bRequest); + + uint8_t intf_num = LO_BYTE(setup->wIndex); + + switch (setup->bRequest) { + case HID_REQUEST_GET_REPORT: + /* report id ,report type */ + usbd_hid_get_report(busid, intf_num, LO_BYTE(setup->wValue), HI_BYTE(setup->wValue), data, len); + break; + case HID_REQUEST_GET_IDLE: + (*data)[0] = usbd_hid_get_idle(busid, intf_num, LO_BYTE(setup->wValue)); + *len = 1; + break; + case HID_REQUEST_GET_PROTOCOL: + (*data)[0] = usbd_hid_get_protocol(busid, intf_num); + *len = 1; + break; + case HID_REQUEST_SET_REPORT: + /* report id ,report type, report, report len */ + usbd_hid_set_report(busid, intf_num, LO_BYTE(setup->wValue), HI_BYTE(setup->wValue), *data, *len); + break; + case HID_REQUEST_SET_IDLE: + /* report id, duration */ + usbd_hid_set_idle(busid, intf_num, LO_BYTE(setup->wValue), HI_BYTE(setup->wValue)); + break; + case HID_REQUEST_SET_PROTOCOL: + /* protocol */ + usbd_hid_set_protocol(busid, intf_num, LO_BYTE(setup->wValue)); + break; + + default: + USB_LOG_WRN("Unhandled HID Class bRequest 0x%02x\r\n", setup->bRequest); + return -1; + } + + return 0; +} + +struct usbd_interface *usbd_hid_init_intf(uint8_t busid, struct usbd_interface *intf, const uint8_t *desc, uint32_t desc_len) +{ + (void)busid; + + intf->class_interface_handler = hid_class_interface_request_handler; + intf->class_endpoint_handler = NULL; + intf->vendor_handler = NULL; + intf->notify_handler = NULL; + + intf->hid_report_descriptor = desc; + intf->hid_report_descriptor_len = desc_len; + return intf; +} + +/* + * Appendix G: HID Request Support Requirements + * + * The following table enumerates the requests that need to be supported by various types of HID class devices. + * Device type GetReport SetReport GetIdle SetIdle GetProtocol SetProtocol + * ------------------------------------------------------------------------------------------ + * Boot Mouse Required Optional Optional Optional Required Required + * Non-Boot Mouse Required Optional Optional Optional Optional Optional + * Boot Keyboard Required Optional Required Required Required Required + * Non-Boot Keybrd Required Optional Required Required Optional Optional + * Other Device Required Optional Optional Optional Optional Optional + */ + +__WEAK void usbd_hid_get_report(uint8_t busid, uint8_t intf, uint8_t report_id, uint8_t report_type, uint8_t **data, uint32_t *len) +{ + (void)busid; + (void)intf; + (void)report_id; + (void)report_type; + (*data[0]) = 0; + *len = 1; +} + +__WEAK uint8_t usbd_hid_get_idle(uint8_t busid, uint8_t intf, uint8_t report_id) +{ + (void)busid; + (void)intf; + (void)report_id; + return 0; +} + +__WEAK uint8_t usbd_hid_get_protocol(uint8_t busid, uint8_t intf) +{ + (void)busid; + (void)intf; + return 0; +} + +__WEAK void usbd_hid_set_report(uint8_t busid, uint8_t intf, uint8_t report_id, uint8_t report_type, uint8_t *report, uint32_t report_len) +{ + (void)busid; + (void)intf; + (void)report_id; + (void)report_type; + (void)report; + (void)report_len; +} + +__WEAK void usbd_hid_set_idle(uint8_t busid, uint8_t intf, uint8_t report_id, uint8_t duration) +{ + (void)busid; + (void)intf; + (void)report_id; + (void)duration; +} + +__WEAK void usbd_hid_set_protocol(uint8_t busid, uint8_t intf, uint8_t protocol) +{ + (void)busid; + (void)intf; + (void)protocol; +} \ No newline at end of file diff --git a/ch32v103_hallarray_controller/3rdparty/CherryUSB/class/hid/usbd_hid.h b/ch32v103_hallarray_controller/3rdparty/CherryUSB/class/hid/usbd_hid.h new file mode 100644 index 0000000..d5c3484 --- /dev/null +++ b/ch32v103_hallarray_controller/3rdparty/CherryUSB/class/hid/usbd_hid.h @@ -0,0 +1,34 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBD_HID_H +#define USBD_HID_H + +#include "usb_hid.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/* Init hid interface driver */ +struct usbd_interface *usbd_hid_init_intf(uint8_t busid, struct usbd_interface *intf, const uint8_t *desc, uint32_t desc_len); + +/* Register desc api */ +void usbd_hid_descriptor_register(uint8_t busid, uint8_t intf_num, const uint8_t *desc); +void usbd_hid_report_descriptor_register(uint8_t busid, uint8_t intf_num, const uint8_t *desc, uint32_t desc_len); + +/* Setup request command callback api */ +void usbd_hid_get_report(uint8_t busid, uint8_t intf, uint8_t report_id, uint8_t report_type, uint8_t **data, uint32_t *len); +uint8_t usbd_hid_get_idle(uint8_t busid, uint8_t intf, uint8_t report_id); +uint8_t usbd_hid_get_protocol(uint8_t busid, uint8_t intf); +void usbd_hid_set_report(uint8_t busid, uint8_t intf, uint8_t report_id, uint8_t report_type, uint8_t *report, uint32_t report_len); +void usbd_hid_set_idle(uint8_t busid, uint8_t intf, uint8_t report_id, uint8_t duration); +void usbd_hid_set_protocol(uint8_t busid, uint8_t intf, uint8_t protocol); + +#ifdef __cplusplus +} +#endif + +#endif /* USBD_HID_H */ diff --git a/ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_dc.h b/ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_dc.h new file mode 100644 index 0000000..dd85d7c --- /dev/null +++ b/ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_dc.h @@ -0,0 +1,204 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_DC_H +#define USB_DC_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief init device controller registers. + * @return On success will return 0, and others indicate fail. + */ +int usb_dc_init(uint8_t busid); + +/** + * @brief deinit device controller registers. + * @return On success will return 0, and others indicate fail. + */ +int usb_dc_deinit(uint8_t busid); + +/** + * @brief Set USB device address + * + * @param[in] addr Device address + * + * @return On success will return 0, and others indicate fail. + */ +int usbd_set_address(uint8_t busid, const uint8_t addr); + +/** + * @brief Set remote wakeup feature + * + * @return On success will return 0, and others indicate fail. + */ +int usbd_set_remote_wakeup(uint8_t busid); + +/** + * @brief Get USB device speed + * + * @param[in] busid bus index + * + * @return port speed, USB_SPEED_LOW or USB_SPEED_FULL or USB_SPEED_HIGH + */ +uint8_t usbd_get_port_speed(uint8_t busid); + +/** + * @brief configure and enable endpoint. + * + * @param [in] ep_cfg Endpoint config. + * + * @return On success will return 0, and others indicate fail. + */ +int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep); + +/** + * @brief Disable the selected endpoint + * + * @param[in] ep Endpoint address + * + * @return On success will return 0, and others indicate fail. + */ +int usbd_ep_close(uint8_t busid, const uint8_t ep); + +/** + * @brief Set stall condition for the selected endpoint + * + * @param[in] ep Endpoint address + * + * + * @return On success will return 0, and others indicate fail. + */ +int usbd_ep_set_stall(uint8_t busid, const uint8_t ep); + +/** + * @brief Clear stall condition for the selected endpoint + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * + * @return On success will return 0, and others indicate fail. + */ +int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep); + +/** + * @brief Check if the selected endpoint is stalled + * + * @param[in] ep Endpoint address + * + * @param[out] stalled Endpoint stall status + * + * @return On success will return 0, and others indicate fail. + */ +int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled); + +/** + * @brief Setup in ep transfer setting and start transfer. + * + * This function is asynchronous. + * This function is similar to uart with tx dma. + * + * This function is called to write data to the specified endpoint. The + * supplied usbd_endpoint_callback function will be called when data is transmitted + * out. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] data Pointer to data to write + * @param[in] data_len Length of the data requested to write. This may + * be zero for a zero length status packet. + * @return 0 on success, negative errno code on fail. + */ +int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, uint32_t data_len); + +/** + * @brief Setup out ep transfer setting and start transfer. + * + * This function is asynchronous. + * This function is similar to uart with rx dma. + * + * This function is called to read data to the specified endpoint. The + * supplied usbd_endpoint_callback function will be called when data is received + * in. + * + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] data Pointer to data to read + * @param[in] data_len Max length of the data requested to read. + * + * @return 0 on success, negative errno code on fail. + */ +int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t data_len); + +/* usb dcd irq callback, called by user */ + +/** + * @brief Usb connect irq callback. + */ +void usbd_event_connect_handler(uint8_t busid); + +/** + * @brief Usb disconnect irq callback. + */ +void usbd_event_disconnect_handler(uint8_t busid); + +/** + * @brief Usb resume irq callback. + */ +void usbd_event_resume_handler(uint8_t busid); + +/** + * @brief Usb suspend irq callback. + */ +void usbd_event_suspend_handler(uint8_t busid); + +/** + * @brief Usb reset irq callback. + */ +void usbd_event_reset_handler(uint8_t busid); + +/** + * @brief Usb setup packet recv irq callback. + * @param[in] psetup setup packet. + */ +void usbd_event_ep0_setup_complete_handler(uint8_t busid, uint8_t *psetup); + +/** + * @brief In ep transfer complete irq callback. + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] nbytes How many nbytes have transferred. + */ +void usbd_event_ep_in_complete_handler(uint8_t busid, uint8_t ep, uint32_t nbytes); + +/** + * @brief Out ep transfer complete irq callback. + * @param[in] ep Endpoint address corresponding to the one + * listed in the device configuration table + * @param[in] nbytes How many nbytes have transferred. + */ +void usbd_event_ep_out_complete_handler(uint8_t busid, uint8_t ep, uint32_t nbytes); + +#ifdef CONFIG_USBDEV_TEST_MODE +/** + * @brief Usb execute test mode + * @param[in] busid device busid + * @param[in] test_mode usb test mode + */ +void usbd_execute_test_mode(uint8_t busid, uint8_t test_mode); +#endif + +/* called by user */ +void USBD_IRQHandler(uint8_t busid); + +#ifdef __cplusplus +} +#endif + +#endif /* USB_DC_H */ diff --git a/ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_dcache.h b/ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_dcache.h new file mode 100644 index 0000000..60fbb7e --- /dev/null +++ b/ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_dcache.h @@ -0,0 +1,19 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_DCACHE_H +#define USB_DCACHE_H + +#ifdef CONFIG_USB_DCACHE_ENABLE +#if CONFIG_USB_ALIGN_SIZE % 32 +#error "CONFIG_USB_ALIGN_SIZE must be multiple of 32" +#endif +#else +#define usb_dcache_clean(addr, size) +#define usb_dcache_invalidate(addr, size) +#define usb_dcache_flush(addr, size) +#endif + +#endif /* USB_DCACHE_H */ diff --git a/ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_def.h b/ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_def.h new file mode 100644 index 0000000..27b4d82 --- /dev/null +++ b/ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_def.h @@ -0,0 +1,724 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_DEF_H +#define USB_DEF_H + +/* Useful define */ +#define USB_1_1 0x0110 +#define USB_2_0 0x0200 +/* Set USB version to 2.1 so that the host will request the BOS descriptor */ +#define USB_2_1 0x0210 +#define USB_3_0 0x0300 +#define USB_3_1 0x0310 +#define USB_3_2 0x0320 + +/* Device speeds */ +#define USB_SPEED_UNKNOWN 0 /* Transfer rate not yet set */ +#define USB_SPEED_LOW 1 /* USB 1.1 */ +#define USB_SPEED_FULL 2 /* USB 1.1 */ +#define USB_SPEED_HIGH 3 /* USB 2.0 */ +#define USB_SPEED_WIRELESS 4 /* Wireless USB 2.5 */ +#define USB_SPEED_SUPER 5 /* USB 3.0 */ +#define USB_SPEED_SUPER_PLUS 6 /* USB 3.1 */ + +/* Maximum number of devices per controller */ +#define USB_MAX_DEVICES (127) + +/* Default USB control EP, always 0 and 0x80 */ +#define USB_CONTROL_OUT_EP0 0 +#define USB_CONTROL_IN_EP0 0x80 + +/**< maximum packet size (MPS) for EP 0 */ +#define USB_CTRL_EP_MPS 64 + +/**< maximum packet size (MPS) for bulk EP */ +#define USB_BULK_EP_MPS_HS 512 +#define USB_BULK_EP_MPS_FS 64 + +/* USB PID Types */ +#define USB_PID_OUT (0x01) /* Tokens */ +#define USB_PID_IN (0x09) +#define USB_PID_SOF (0x05) +#define USB_PID_SETUP (0x0d) + +#define USB_PID_DATA0 (0x03) /* Data */ +#define USB_PID_DATA1 (0x0b) +#define USB_PID_DATA2 (0x07) +#define USB_PID_MDATA (0x0f) + +#define USB_PID_ACK (0x02) /* Handshake */ +#define USB_PID_NAK (0x0a) +#define USB_PID_STALL (0x0e) +#define USB_PID_NYET (0x06) + +#define USB_PID_PRE (0x0c) /* Special */ +#define USB_PID_ERR (0x0c) +#define USB_PID_SPLIT (0x08) +#define USB_PID_PING (0x04) +#define USB_PID_RESERVED (0x00) + +#define USB_REQUEST_DIR_SHIFT 7U /* Bits 7: Request dir */ +#define USB_REQUEST_DIR_OUT (0U << USB_REQUEST_DIR_SHIFT) /* Bit 7=0: Host-to-device */ +#define USB_REQUEST_DIR_IN (1U << USB_REQUEST_DIR_SHIFT) /* Bit 7=1: Device-to-host */ +#define USB_REQUEST_DIR_MASK (1U << USB_REQUEST_DIR_SHIFT) /* Bit 7=1: Direction bit */ + +#define USB_REQUEST_TYPE_SHIFT 5U /* Bits 5:6: Request type */ +#define USB_REQUEST_STANDARD (0U << USB_REQUEST_TYPE_SHIFT) +#define USB_REQUEST_CLASS (1U << USB_REQUEST_TYPE_SHIFT) +#define USB_REQUEST_VENDOR (2U << USB_REQUEST_TYPE_SHIFT) +#define USB_REQUEST_RESERVED (3U << USB_REQUEST_TYPE_SHIFT) +#define USB_REQUEST_TYPE_MASK (3U << USB_REQUEST_TYPE_SHIFT) + +#define USB_REQUEST_RECIPIENT_SHIFT 0U /* Bits 0:4: Recipient */ +#define USB_REQUEST_RECIPIENT_DEVICE (0U << USB_REQUEST_RECIPIENT_SHIFT) +#define USB_REQUEST_RECIPIENT_INTERFACE (1U << USB_REQUEST_RECIPIENT_SHIFT) +#define USB_REQUEST_RECIPIENT_ENDPOINT (2U << USB_REQUEST_RECIPIENT_SHIFT) +#define USB_REQUEST_RECIPIENT_OTHER (3U << USB_REQUEST_RECIPIENT_SHIFT) +#define USB_REQUEST_RECIPIENT_MASK (3U << USB_REQUEST_RECIPIENT_SHIFT) + +/* USB Standard Request Codes */ +#define USB_REQUEST_GET_STATUS 0x00 +#define USB_REQUEST_CLEAR_FEATURE 0x01 +#define USB_REQUEST_SET_FEATURE 0x03 +#define USB_REQUEST_SET_ADDRESS 0x05 +#define USB_REQUEST_GET_DESCRIPTOR 0x06 +#define USB_REQUEST_SET_DESCRIPTOR 0x07 +#define USB_REQUEST_GET_CONFIGURATION 0x08 +#define USB_REQUEST_SET_CONFIGURATION 0x09 +#define USB_REQUEST_GET_INTERFACE 0x0A +#define USB_REQUEST_SET_INTERFACE 0x0B +#define USB_REQUEST_SYNCH_FRAME 0x0C +#define USB_REQUEST_SET_ENCRYPTION 0x0D +#define USB_REQUEST_GET_ENCRYPTION 0x0E +#define USB_REQUEST_RPIPE_ABORT 0x0E +#define USB_REQUEST_SET_HANDSHAKE 0x0F +#define USB_REQUEST_RPIPE_RESET 0x0F +#define USB_REQUEST_GET_HANDSHAKE 0x10 +#define USB_REQUEST_SET_CONNECTION 0x11 +#define USB_REQUEST_SET_SECURITY_DATA 0x12 +#define USB_REQUEST_GET_SECURITY_DATA 0x13 +#define USB_REQUEST_SET_WUSB_DATA 0x14 +#define USB_REQUEST_LOOPBACK_DATA_WRITE 0x15 +#define USB_REQUEST_LOOPBACK_DATA_READ 0x16 +#define USB_REQUEST_SET_INTERFACE_DS 0x17 + +/* USB Standard Feature selectors */ +#define USB_FEATURE_ENDPOINT_HALT 0 +#define USB_FEATURE_SELF_POWERED 0 +#define USB_FEATURE_REMOTE_WAKEUP 1 +#define USB_FEATURE_TEST_MODE 2 +#define USB_FEATURE_BATTERY 2 +#define USB_FEATURE_BHNPENABLE 3 +#define USB_FEATURE_WUSBDEVICE 3 +#define USB_FEATURE_AHNPSUPPORT 4 +#define USB_FEATURE_AALTHNPSUPPORT 5 +#define USB_FEATURE_DEBUGMODE 6 + +/* USB GET_STATUS Bit Values */ +#define USB_GETSTATUS_ENDPOINT_HALT 0x01 +#define USB_GETSTATUS_SELF_POWERED 0x01 +#define USB_GETSTATUS_REMOTE_WAKEUP 0x02 + +/* USB Descriptor Types */ +#define USB_DESCRIPTOR_TYPE_DEVICE 0x01U +#define USB_DESCRIPTOR_TYPE_CONFIGURATION 0x02U +#define USB_DESCRIPTOR_TYPE_STRING 0x03U +#define USB_DESCRIPTOR_TYPE_INTERFACE 0x04U +#define USB_DESCRIPTOR_TYPE_ENDPOINT 0x05U +#define USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER 0x06U +#define USB_DESCRIPTOR_TYPE_OTHER_SPEED 0x07U +#define USB_DESCRIPTOR_TYPE_INTERFACE_POWER 0x08U +#define USB_DESCRIPTOR_TYPE_OTG 0x09U +#define USB_DESCRIPTOR_TYPE_DEBUG 0x0AU +#define USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION 0x0BU +#define USB_DESCRIPTOR_TYPE_BINARY_OBJECT_STORE 0x0FU +#define USB_DESCRIPTOR_TYPE_DEVICE_CAPABILITY 0x10U +#define USB_DESCRIPTOR_TYPE_WIRELESS_ENDPOINTCOMP 0x11U + +/* Class Specific Descriptor */ +#define USB_CS_DESCRIPTOR_TYPE_DEVICE 0x21U +#define USB_CS_DESCRIPTOR_TYPE_CONFIGURATION 0x22U +#define USB_CS_DESCRIPTOR_TYPE_STRING 0x23U +#define USB_CS_DESCRIPTOR_TYPE_INTERFACE 0x24U +#define USB_CS_DESCRIPTOR_TYPE_ENDPOINT 0x25U + +#define USB_DESCRIPTOR_TYPE_SUPERSPEED_ENDPOINT_COMPANION 0x30U +#define USB_DESCRIPTOR_TYPE_SUPERSPEED_ISO_ENDPOINT_COMPANION 0x31U + +/* USB Device Classes */ +#define USB_DEVICE_CLASS_RESERVED 0x00 +#define USB_DEVICE_CLASS_AUDIO 0x01 +#define USB_DEVICE_CLASS_CDC 0x02 +#define USB_DEVICE_CLASS_HID 0x03 +#define USB_DEVICE_CLASS_MONITOR 0x04 +#define USB_DEVICE_CLASS_PHYSICAL 0x05 +#define USB_DEVICE_CLASS_IMAGE 0x06 +#define USB_DEVICE_CLASS_PRINTER 0x07 +#define USB_DEVICE_CLASS_MASS_STORAGE 0x08 +#define USB_DEVICE_CLASS_HUB 0x09 +#define USB_DEVICE_CLASS_CDC_DATA 0x0a +#define USB_DEVICE_CLASS_SMART_CARD 0x0b +#define USB_DEVICE_CLASS_SECURITY 0x0d +#define USB_DEVICE_CLASS_VIDEO 0x0e +#define USB_DEVICE_CLASS_HEALTHCARE 0x0f +#define USB_DEVICE_CLASS_DIAG_DEVICE 0xdc +#define USB_DEVICE_CLASS_WIRELESS 0xe0 +#define USB_DEVICE_CLASS_MISC 0xef +#define USB_DEVICE_CLASS_APP_SPECIFIC 0xfe +#define USB_DEVICE_CLASS_VEND_SPECIFIC 0xff + +/* usb string index define */ +#define USB_STRING_LANGID_INDEX 0x00 +#define USB_STRING_MFC_INDEX 0x01 +#define USB_STRING_PRODUCT_INDEX 0x02 +#define USB_STRING_SERIAL_INDEX 0x03 +#define USB_STRING_CONFIG_INDEX 0x04 +#define USB_STRING_INTERFACE_INDEX 0x05 +#define USB_STRING_OS_INDEX 0x06 +#define USB_STRING_MAX USB_STRING_OS_INDEX +/* + * Devices supporting Microsoft OS Descriptors store special string + * descriptor at fixed index (0xEE). It is read when a new device is + * attached to a computer for the first time. + */ +#define USB_OSDESC_STRING_DESC_INDEX 0xEE + +/* bmAttributes in Configuration Descriptor */ +#define USB_CONFIG_REMOTE_WAKEUP 0x20 +#define USB_CONFIG_POWERED_MASK 0x40 +#define USB_CONFIG_BUS_POWERED 0x80 +#define USB_CONFIG_SELF_POWERED 0xC0 + +/* bMaxPower in Configuration Descriptor */ +#define USB_CONFIG_POWER_MA(mA) ((mA) / 2) + +/* bEndpointAddress in Endpoint Descriptor */ +#define USB_ENDPOINT_DIRECTION_MASK 0x80 +#define USB_ENDPOINT_OUT(addr) ((addr) | 0x00) +#define USB_ENDPOINT_IN(addr) ((addr) | 0x80) + +/** + * USB endpoint direction and number. + */ +#define USB_EP_DIR_MASK 0x80U +#define USB_EP_DIR_IN 0x80U +#define USB_EP_DIR_OUT 0x00U + +/** Get endpoint index (number) from endpoint address */ +#define USB_EP_GET_IDX(ep) ((ep) & ~USB_EP_DIR_MASK) +/** Get direction from endpoint address */ +#define USB_EP_GET_DIR(ep) ((ep)&USB_EP_DIR_MASK) +/** Get endpoint address from endpoint index and direction */ +#define USB_EP_GET_ADDR(idx, dir) ((idx) | ((dir)&USB_EP_DIR_MASK)) +/** True if the endpoint is an IN endpoint */ +#define USB_EP_DIR_IS_IN(ep) (USB_EP_GET_DIR(ep) == USB_EP_DIR_IN) +/** True if the endpoint is an OUT endpoint */ +#define USB_EP_DIR_IS_OUT(ep) (USB_EP_GET_DIR(ep) == USB_EP_DIR_OUT) + +/* bmAttributes in Endpoint Descriptor */ +#define USB_ENDPOINT_TYPE_SHIFT 0 +#define USB_ENDPOINT_TYPE_CONTROL (0 << USB_ENDPOINT_TYPE_SHIFT) +#define USB_ENDPOINT_TYPE_ISOCHRONOUS (1 << USB_ENDPOINT_TYPE_SHIFT) +#define USB_ENDPOINT_TYPE_BULK (2 << USB_ENDPOINT_TYPE_SHIFT) +#define USB_ENDPOINT_TYPE_INTERRUPT (3 << USB_ENDPOINT_TYPE_SHIFT) +#define USB_ENDPOINT_TYPE_MASK (3 << USB_ENDPOINT_TYPE_SHIFT) +#define USB_GET_ENDPOINT_TYPE(x) ((x & USB_ENDPOINT_TYPE_MASK) >> USB_ENDPOINT_TYPE_SHIFT) + +#define USB_ENDPOINT_SYNC_SHIFT 2 +#define USB_ENDPOINT_SYNC_NO_SYNCHRONIZATION (0 << USB_ENDPOINT_SYNC_SHIFT) +#define USB_ENDPOINT_SYNC_ASYNCHRONOUS (1 << USB_ENDPOINT_SYNC_SHIFT) +#define USB_ENDPOINT_SYNC_ADAPTIVE (2 << USB_ENDPOINT_SYNC_SHIFT) +#define USB_ENDPOINT_SYNC_SYNCHRONOUS (3 << USB_ENDPOINT_SYNC_SHIFT) +#define USB_ENDPOINT_SYNC_MASK (3 << USB_ENDPOINT_SYNC_SHIFT) + +#define USB_ENDPOINT_USAGE_SHIFT 4 +#define USB_ENDPOINT_USAGE_DATA (0 << USB_ENDPOINT_USAGE_SHIFT) +#define USB_ENDPOINT_USAGE_FEEDBACK (1 << USB_ENDPOINT_USAGE_SHIFT) +#define USB_ENDPOINT_USAGE_IMPLICIT_FEEDBACK (2 << USB_ENDPOINT_USAGE_SHIFT) +#define USB_ENDPOINT_USAGE_MASK (3 << USB_ENDPOINT_USAGE_SHIFT) + +#define USB_ENDPOINT_MAX_ADJUSTABLE (1 << 7) + +/* wMaxPacketSize in Endpoint Descriptor */ +#define USB_MAXPACKETSIZE_SHIFT 0 +#define USB_MAXPACKETSIZE_MASK (0x7ff << USB_MAXPACKETSIZE_SHIFT) +#define USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT 11 +#define USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_NONE (0 << USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT) +#define USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_ONE (1 << USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT) +#define USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_TWO (2 << USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT) +#define USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_MASK (3 << USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT) +#define USB_GET_MAXPACKETSIZE(x) ((x & USB_MAXPACKETSIZE_MASK) >> USB_MAXPACKETSIZE_SHIFT) +#define USB_GET_MULT(x) ((x & USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_MASK) >> USB_MAXPACKETSIZE_ADDITIONAL_TRANSCATION_SHIFT) + +/* bDevCapabilityType in Device Capability Descriptor */ +#define USB_DEVICE_CAPABILITY_WIRELESS_USB 1 +#define USB_DEVICE_CAPABILITY_USB_2_0_EXTENSION 2 +#define USB_DEVICE_CAPABILITY_SUPERSPEED_USB 3 +#define USB_DEVICE_CAPABILITY_CONTAINER_ID 4 +#define USB_DEVICE_CAPABILITY_PLATFORM 5 +#define USB_DEVICE_CAPABILITY_POWER_DELIVERY_CAPABILITY 6 +#define USB_DEVICE_CAPABILITY_BATTERY_INFO_CAPABILITY 7 +#define USB_DEVICE_CAPABILITY_PD_CONSUMER_PORT_CAPABILITY 8 +#define USB_DEVICE_CAPABILITY_PD_PROVIDER_PORT_CAPABILITY 9 +#define USB_DEVICE_CAPABILITY_SUPERSPEED_PLUS 10 +#define USB_DEVICE_CAPABILITY_PRECISION_TIME_MEASUREMENT 11 +#define USB_DEVICE_CAPABILITY_WIRELESS_USB_EXT 12 + +#define USB_BOS_CAPABILITY_EXTENSION 0x02 +#define USB_BOS_CAPABILITY_PLATFORM 0x05 + +/* OTG SET FEATURE Constants */ +#define USB_OTG_FEATURE_B_HNP_ENABLE 3 /* Enable B device to perform HNP */ +#define USB_OTG_FEATURE_A_HNP_SUPPORT 4 /* A device supports HNP */ +#define USB_OTG_FEATURE_A_ALT_HNP_SUPPORT 5 /* Another port on the A device supports HNP */ + +/* WinUSB Microsoft OS 2.0 descriptor request codes */ +#define WINUSB_REQUEST_GET_DESCRIPTOR_SET 0x07 +#define WINUSB_REQUEST_SET_ALT_ENUM 0x08 + +/* WinUSB Microsoft OS 2.0 descriptor sizes */ +#define WINUSB_DESCRIPTOR_SET_HEADER_SIZE 10 +#define WINUSB_FUNCTION_SUBSET_HEADER_SIZE 8 +#define WINUSB_FEATURE_COMPATIBLE_ID_SIZE 20 + +/* WinUSB Microsoft OS 2.0 Descriptor Types */ +#define WINUSB_SET_HEADER_DESCRIPTOR_TYPE 0x00 +#define WINUSB_SUBSET_HEADER_CONFIGURATION_TYPE 0x01 +#define WINUSB_SUBSET_HEADER_FUNCTION_TYPE 0x02 +#define WINUSB_FEATURE_COMPATIBLE_ID_TYPE 0x03 +#define WINUSB_FEATURE_REG_PROPERTY_TYPE 0x04 +#define WINUSB_FEATURE_MIN_RESUME_TIME_TYPE 0x05 +#define WINUSB_FEATURE_MODEL_ID_TYPE 0x06 +#define WINUSB_FEATURE_CCGP_DEVICE_TYPE 0x07 + +#define WINUSB_PROP_DATA_TYPE_REG_SZ 0x01 +#define WINUSB_PROP_DATA_TYPE_REG_MULTI_SZ 0x07 + +/* WebUSB Descriptor Types */ +#define WEBUSB_DESCRIPTOR_SET_HEADER_TYPE 0x00 +#define WEBUSB_CONFIGURATION_SUBSET_HEADER_TYPE 0x01 +#define WEBUSB_FUNCTION_SUBSET_HEADER_TYPE 0x02 +#define WEBUSB_URL_TYPE 0x03 + +/* WebUSB Request Codes */ +#define WEBUSB_REQUEST_GET_URL 0x02 + +/* bScheme in URL descriptor */ +#define WEBUSB_URL_SCHEME_HTTP 0x00 +#define WEBUSB_URL_SCHEME_HTTPS 0x01 + +/* WebUSB Descriptor sizes */ +#define WEBUSB_DESCRIPTOR_SET_HEADER_SIZE 5 +#define WEBUSB_CONFIGURATION_SUBSET_HEADER_SIZE 4 +#define WEBUSB_FUNCTION_SUBSET_HEADER_SIZE 3 + +/* Setup packet definition used to read raw data from USB line */ +struct usb_setup_packet { + /** Request type. Bits 0:4 determine recipient, see + * \ref usb_request_recipient. Bits 5:6 determine type, see + * \ref usb_request_type. Bit 7 determines data transfer direction, see + * \ref usb_endpoint_direction. + */ + uint8_t bmRequestType; + + /** Request. If the type bits of bmRequestType are equal to + * \ref usb_request_type::LIBUSB_REQUEST_TYPE_STANDARD + * "USB_REQUEST_TYPE_STANDARD" then this field refers to + * \ref usb_standard_request. For other cases, use of this field is + * application-specific. */ + uint8_t bRequest; + + /** Value. Varies according to request */ + uint16_t wValue; + + /** Index. Varies according to request, typically used to pass an index + * or offset */ + uint16_t wIndex; + + /** Number of bytes to transfer */ + uint16_t wLength; +} __PACKED; + +#define USB_SIZEOF_SETUP_PACKET 8 + +/** Standard Device Descriptor */ +struct usb_device_descriptor { + uint8_t bLength; /* Descriptor size in bytes = 18 */ + uint8_t bDescriptorType; /* DEVICE descriptor type = 1 */ + uint16_t bcdUSB; /* USB spec in BCD, e.g. 0x0200 */ + uint8_t bDeviceClass; /* Class code, if 0 see interface */ + uint8_t bDeviceSubClass; /* Sub-Class code, 0 if class = 0 */ + uint8_t bDeviceProtocol; /* Protocol, if 0 see interface */ + uint8_t bMaxPacketSize0; /* Endpoint 0 max. size */ + uint16_t idVendor; /* Vendor ID per USB-IF */ + uint16_t idProduct; /* Product ID per manufacturer */ + uint16_t bcdDevice; /* Device release # in BCD */ + uint8_t iManufacturer; /* Index to manufacturer string */ + uint8_t iProduct; /* Index to product string */ + uint8_t iSerialNumber; /* Index to serial number string */ + uint8_t bNumConfigurations; /* Number of possible configurations */ +} __PACKED; + +#define USB_SIZEOF_DEVICE_DESC 18 + +/** Standard Configuration Descriptor */ +struct usb_configuration_descriptor { + uint8_t bLength; /* Descriptor size in bytes = 9 */ + uint8_t bDescriptorType; /* CONFIGURATION type = 2 or 7 */ + uint16_t wTotalLength; /* Length of concatenated descriptors */ + uint8_t bNumInterfaces; /* Number of interfaces, this config. */ + uint8_t bConfigurationValue; /* Value to set this config. */ + uint8_t iConfiguration; /* Index to configuration string */ + uint8_t bmAttributes; /* Config. characteristics */ + uint8_t bMaxPower; /* Max.power from bus, 2mA units */ +} __PACKED; + +#define USB_SIZEOF_CONFIG_DESC 9 + +/** Standard Interface Descriptor */ +struct usb_interface_descriptor { + uint8_t bLength; /* Descriptor size in bytes = 9 */ + uint8_t bDescriptorType; /* INTERFACE descriptor type = 4 */ + uint8_t bInterfaceNumber; /* Interface no.*/ + uint8_t bAlternateSetting; /* Value to select this IF */ + uint8_t bNumEndpoints; /* Number of endpoints excluding 0 */ + uint8_t bInterfaceClass; /* Class code, 0xFF = vendor */ + uint8_t bInterfaceSubClass; /* Sub-Class code, 0 if class = 0 */ + uint8_t bInterfaceProtocol; /* Protocol, 0xFF = vendor */ + uint8_t iInterface; /* Index to interface string */ +} __PACKED; + +#define USB_SIZEOF_INTERFACE_DESC 9 + +/** Standard Endpoint Descriptor */ +struct usb_endpoint_descriptor { + uint8_t bLength; /* Descriptor size in bytes = 7 */ + uint8_t bDescriptorType; /* ENDPOINT descriptor type = 5 */ + uint8_t bEndpointAddress; /* Endpoint # 0 - 15 | IN/OUT */ + uint8_t bmAttributes; /* Transfer type */ + uint16_t wMaxPacketSize; /* Bits 10:0 = max. packet size */ + uint8_t bInterval; /* Polling interval in (micro) frames */ +} __PACKED; + +#define USB_SIZEOF_ENDPOINT_DESC 7 + +/** Unicode (UTF16LE) String Descriptor */ +struct usb_string_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t bString; +} __PACKED; + +#define USB_SIZEOF_STRING_LANGID_DESC 4 + +/* USB Interface Association Descriptor */ +struct usb_interface_association_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bFirstInterface; + uint8_t bInterfaceCount; + uint8_t bFunctionClass; + uint8_t bFunctionSubClass; + uint8_t bFunctionProtocol; + uint8_t iFunction; +} __PACKED; + +#define USB_SIZEOF_IAD_DESC 8 + +/** USB device_qualifier descriptor */ +struct usb_device_qualifier_descriptor { + uint8_t bLength; /* Descriptor size in bytes = 10 */ + uint8_t bDescriptorType; /* DEVICE QUALIFIER type = 6 */ + uint16_t bcdUSB; /* USB spec in BCD, e.g. 0x0200 */ + uint8_t bDeviceClass; /* Class code, if 0 see interface */ + uint8_t bDeviceSubClass; /* Sub-Class code, 0 if class = 0 */ + uint8_t bDeviceProtocol; /* Protocol, if 0 see interface */ + uint8_t bMaxPacketSize; /* Endpoint 0 max. size */ + uint8_t bNumConfigurations; /* Number of possible configurations */ + uint8_t bReserved; /* Reserved = 0 */ +} __PACKED; + +#define USB_SIZEOF_DEVICE_QUALIFIER_DESC 10 + +/* Microsoft OS function descriptor. + * This can be used to request a specific driver (such as WINUSB) to be + * loaded on Windows. Unlike other descriptors, it is requested by a special + * request USB_REQ_GETMSFTOSDESCRIPTOR. + * More details: + * https://msdn.microsoft.com/en-us/windows/hardware/gg463179 + * And excellent explanation: + * https://github.com/pbatard/libwdi/wiki/WCID-Devices + * + * The device will have exactly one "Extended Compat ID Feature Descriptor", + * which may contain multiple "Function Descriptors" associated with + * different interfaces. + */ + +/* MS OS 1.0 string descriptor */ +struct usb_msosv1_string_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bString[14]; + uint8_t bMS_VendorCode; /* Vendor Code, used for a control request */ + uint8_t bPad; /* Padding byte for VendorCode look as UTF16 */ +} __PACKED; + +/* MS OS 1.0 Header descriptor */ +struct usb_msosv1_compat_id_header_descriptor { + uint32_t dwLength; + uint16_t bcdVersion; + uint16_t wIndex; + uint8_t bCount; + uint8_t reserved[7]; +} __PACKED; + +/* MS OS 1.0 Function descriptor */ +struct usb_msosv1_comp_id_function_descriptor { + uint8_t bFirstInterfaceNumber; + uint8_t reserved1; + uint8_t compatibleID[8]; + uint8_t subCompatibleID[8]; + uint8_t reserved2[6]; +} __PACKED; + +#define usb_msosv1_comp_id_create(x) \ + struct usb_msosv1_comp_id { \ + struct usb_msosv1_compat_id_header_descriptor compat_id_header; \ + struct usb_msosv1_comp_id_function_descriptor compat_id_function[x]; \ + }; + +struct usb_msosv1_descriptor { + const uint8_t *string; + uint8_t vendor_code; + const uint8_t *compat_id; + const uint8_t **comp_id_property; +}; + +/* MS OS 2.0 Header descriptor */ +struct usb_msosv2_header_descriptor { + uint32_t dwLength; + uint16_t bcdVersion; + uint16_t wIndex; + uint8_t bCount; +} __PACKED; + +/*Microsoft OS 2.0 set header descriptor*/ +struct usb_msosv2_set_header_descriptor { + uint16_t wLength; + uint16_t wDescriptorType; + uint32_t dwWindowsVersion; + uint16_t wDescriptorSetTotalLength; +} __PACKED; + +/* Microsoft OS 2.0 compatibleID descriptor*/ +struct usb_msosv2_comp_id_descriptor { + uint16_t wLength; + uint16_t wDescriptorType; + uint8_t compatibleID[8]; + uint8_t subCompatibleID[8]; +} __PACKED; + +/* MS OS 2.0 property descriptor */ +struct usb_msosv2_property_descriptor { + uint16_t wLength; + uint16_t wDescriptorType; + uint32_t dwPropertyDataType; + uint16_t wPropertyNameLength; + const char *bPropertyName; + uint32_t dwPropertyDataLength; + const char *bPropertyData; +}; + +/* Microsoft OS 2.0 subset function descriptor */ +struct usb_msosv2_subset_function_descriptor { + uint16_t wLength; + uint16_t wDescriptorType; + uint8_t bFirstInterface; + uint8_t bReserved; + uint16_t wSubsetLength; +} __PACKED; + +struct usb_msosv2_descriptor { + const uint8_t *compat_id; + uint16_t compat_id_len; + uint8_t vendor_code; +}; + +/* BOS header Descriptor */ +struct usb_bos_header_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint16_t wTotalLength; + uint8_t bNumDeviceCaps; +} __PACKED; + +/* BOS Capability platform Descriptor */ +struct usb_bos_capability_platform_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDevCapabilityType; + uint8_t bReserved; + uint8_t PlatformCapabilityUUID[16]; +} __PACKED; + +/* BOS Capability MS OS Descriptors version 2 */ +struct usb_bos_capability_msosv2_descriptor { + uint32_t dwWindowsVersion; + uint16_t wMSOSDescriptorSetTotalLength; + uint8_t bVendorCode; + uint8_t bAltEnumCode; +} __PACKED; + +/* BOS Capability webusb */ +struct usb_bos_capability_webusb_descriptor { + uint16_t bcdVersion; + uint8_t bVendorCode; + uint8_t iLandingPage; +} __PACKED; + +/* BOS Capability extension Descriptor*/ +struct usb_bos_capability_extension_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDevCapabilityType; + uint32_t bmAttributes; +} __PACKED; + +/* Microsoft OS 2.0 Platform Capability Descriptor +* See https://docs.microsoft.com/en-us/windows-hardware/drivers/usbcon/ +* microsoft-defined-usb-descriptors +* Adapted from the source: +* https://github.com/sowbug/weblight/blob/master/firmware/webusb.c +* (BSD-2) Thanks http://janaxelson.com/files/ms_os_20_descriptors.c +*/ +struct usb_bos_capability_platform_msosv2_descriptor { + struct usb_bos_capability_platform_descriptor platform_msos; + struct usb_bos_capability_msosv2_descriptor data_msosv2; +} __PACKED; + +/* WebUSB Platform Capability Descriptor: +* https://wicg.github.io/webusb/#webusb-platform-capability-descriptor +*/ +struct usb_bos_capability_platform_webusb_descriptor { + struct usb_bos_capability_platform_descriptor platform_webusb; + struct usb_bos_capability_webusb_descriptor data_webusb; +} __PACKED; + +struct usb_webusb_url_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bScheme; + char URL[]; +} __PACKED; + +struct usb_webusb_descriptor { + uint8_t vendor_code; + const uint8_t *string; + uint32_t string_len; +} __PACKED; + +struct usb_bos_descriptor { + const uint8_t *string; + uint32_t string_len; +}; + +/* USB Device Capability Descriptor */ +struct usb_device_capability_descriptor { + uint8_t bLength; + uint8_t bDescriptorType; + uint8_t bDevCapabilityType; +} __PACKED; + +/** USB descriptor header */ +struct usb_desc_header { + uint8_t bLength; /**< descriptor length */ + uint8_t bDescriptorType; /**< descriptor type */ +}; +// clang-format off +#define USB_DEVICE_DESCRIPTOR_INIT(bcdUSB, bDeviceClass, bDeviceSubClass, bDeviceProtocol, idVendor, idProduct, bcdDevice, bNumConfigurations) \ + 0x12, /* bLength */ \ + USB_DESCRIPTOR_TYPE_DEVICE, /* bDescriptorType */ \ + WBVAL(bcdUSB), /* bcdUSB */ \ + bDeviceClass, /* bDeviceClass */ \ + bDeviceSubClass, /* bDeviceSubClass */ \ + bDeviceProtocol, /* bDeviceProtocol */ \ + 0x40, /* bMaxPacketSize */ \ + WBVAL(idVendor), /* idVendor */ \ + WBVAL(idProduct), /* idProduct */ \ + WBVAL(bcdDevice), /* bcdDevice */ \ + USB_STRING_MFC_INDEX, /* iManufacturer */ \ + USB_STRING_PRODUCT_INDEX, /* iProduct */ \ + USB_STRING_SERIAL_INDEX, /* iSerial */ \ + bNumConfigurations /* bNumConfigurations */ + +#define USB_CONFIG_DESCRIPTOR_INIT(wTotalLength, bNumInterfaces, bConfigurationValue, bmAttributes, bMaxPower) \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_CONFIGURATION, /* bDescriptorType */ \ + WBVAL(wTotalLength), /* wTotalLength */ \ + bNumInterfaces, /* bNumInterfaces */ \ + bConfigurationValue, /* bConfigurationValue */ \ + 0x00, /* iConfiguration */ \ + bmAttributes, /* bmAttributes */ \ + USB_CONFIG_POWER_MA(bMaxPower) /* bMaxPower */ + +#define USB_DEVICE_QUALIFIER_DESCRIPTOR_INIT(bcdUSB, bDeviceClass, bDeviceSubClass, bDeviceProtocol, bNumConfigurations) \ + 0x0A, /* bLength */ \ + USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, /* bDescriptorType */ \ + WBVAL(bcdUSB), /* bcdUSB */ \ + bDeviceClass, /* bDeviceClass */ \ + bDeviceSubClass, /* bDeviceSubClass */ \ + bDeviceProtocol, /* bDeviceProtocol */ \ + 0x40, /* bMaxPacketSize */ \ + bNumConfigurations, /* bNumConfigurations */ \ + 0x00 /* bReserved */ + +#define USB_OTHER_SPEED_CONFIG_DESCRIPTOR_INIT(wTotalLength, bNumInterfaces, bConfigurationValue, bmAttributes, bMaxPower) \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_OTHER_SPEED, /* bDescriptorType */ \ + WBVAL(wTotalLength), /* wTotalLength */ \ + bNumInterfaces, /* bNumInterfaces */ \ + bConfigurationValue, /* bConfigurationValue */ \ + 0x00, /* iConfiguration */ \ + bmAttributes, /* bmAttributes */ \ + USB_CONFIG_POWER_MA(bMaxPower) /* bMaxPower */ + +#define USB_INTERFACE_DESCRIPTOR_INIT(bInterfaceNumber, bAlternateSetting, bNumEndpoints, \ + bInterfaceClass, bInterfaceSubClass, bInterfaceProtocol, iInterface) \ + 0x09, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE, /* bDescriptorType */ \ + bInterfaceNumber, /* bInterfaceNumber */ \ + bAlternateSetting, /* bAlternateSetting */ \ + bNumEndpoints, /* bNumEndpoints */ \ + bInterfaceClass, /* bInterfaceClass */ \ + bInterfaceSubClass, /* bInterfaceSubClass */ \ + bInterfaceProtocol, /* bInterfaceProtocol */ \ + iInterface /* iInterface */ + +#define USB_ENDPOINT_DESCRIPTOR_INIT(bEndpointAddress, bmAttributes, wMaxPacketSize, bInterval) \ + 0x07, /* bLength */ \ + USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType */ \ + bEndpointAddress, /* bEndpointAddress */ \ + bmAttributes, /* bmAttributes */ \ + WBVAL(wMaxPacketSize), /* wMaxPacketSize */ \ + bInterval /* bInterval */ + +#define USB_IAD_INIT(bFirstInterface, bInterfaceCount, bFunctionClass, bFunctionSubClass, bFunctionProtocol) \ + 0x08, /* bLength */ \ + USB_DESCRIPTOR_TYPE_INTERFACE_ASSOCIATION, /* bDescriptorType */ \ + bFirstInterface, /* bFirstInterface */ \ + bInterfaceCount, /* bInterfaceCount */ \ + bFunctionClass, /* bFunctionClass */ \ + bFunctionSubClass, /* bFunctionSubClass */ \ + bFunctionProtocol, /* bFunctionProtocol */ \ + 0x00 /* iFunction */ + +#define USB_LANGID_INIT(id) \ + 0x04, /* bLength */ \ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ \ + WBVAL(id) /* wLangID0 */ +// clang-format on + +#endif /* USB_DEF_H */ diff --git a/ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_errno.h b/ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_errno.h new file mode 100644 index 0000000..57f37c1 --- /dev/null +++ b/ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_errno.h @@ -0,0 +1,24 @@ +/* + * Copyright (c) 2023, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_ERRNO_H +#define USB_ERRNO_H + +#define USB_ERR_NOMEM 1 +#define USB_ERR_INVAL 2 +#define USB_ERR_NODEV 3 +#define USB_ERR_NOTCONN 4 +#define USB_ERR_NOTSUPP 5 +#define USB_ERR_BUSY 6 +#define USB_ERR_RANGE 7 +#define USB_ERR_STALL 8 +#define USB_ERR_BABBLE 9 +#define USB_ERR_NAK 10 +#define USB_ERR_DT 11 +#define USB_ERR_IO 12 +#define USB_ERR_SHUTDOWN 13 +#define USB_ERR_TIMEOUT 14 + +#endif /* USB_ERRNO_H */ diff --git a/ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_hc.h b/ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_hc.h new file mode 100644 index 0000000..3335af2 --- /dev/null +++ b/ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_hc.h @@ -0,0 +1,118 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_HC_H +#define USB_HC_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef void (*usbh_complete_callback_t)(void *arg, int nbytes); + +struct usbh_bus; + +/** + * @brief USB Iso Configuration. + * + * Structure containing the USB Iso configuration. + */ +struct usbh_iso_frame_packet { + uint8_t *transfer_buffer; + uint32_t transfer_buffer_length; + uint32_t actual_length; + int errorcode; +}; + +/** + * @brief USB Urb Configuration. + * + * Structure containing the USB Urb configuration. + */ +struct usbh_urb { + usb_slist_t list; + void *hcpriv; + struct usbh_hubport *hport; + struct usb_endpoint_descriptor *ep; + uint8_t data_toggle; + uint8_t interval; + struct usb_setup_packet *setup; + uint8_t *transfer_buffer; + uint32_t transfer_buffer_length; + int transfer_flags; + uint32_t actual_length; + uint32_t timeout; + int errorcode; + uint32_t num_of_iso_packets; + uint32_t start_frame; + usbh_complete_callback_t complete; + void *arg; +#if defined(__ICCARM__) || defined(__ICCRISCV__) || defined(__ICCRX__) + struct usbh_iso_frame_packet *iso_packet; +#else + struct usbh_iso_frame_packet iso_packet[0]; +#endif +}; + +/** + * @brief usb host controller hardware init. + * + * @return On success will return 0, and others indicate fail. + */ +int usb_hc_init(struct usbh_bus *bus); + +/** + * @brief usb host controller hardware deinit. + * + * @return On success will return 0, and others indicate fail. + */ +int usb_hc_deinit(struct usbh_bus *bus); + +/** + * @brief Get frame number. + * + * @return frame number. + */ +uint16_t usbh_get_frame_number(struct usbh_bus *bus); +/** + * @brief control roothub. + * + * @param setup setup request buffer. + * @param buf buf for reading response or write data. + * @return On success will return 0, and others indicate fail. + */ +int usbh_roothub_control(struct usbh_bus *bus, struct usb_setup_packet *setup, uint8_t *buf); + +/** + * @brief Submit a usb transfer request to an endpoint. + * + * If timeout is not zero, this function will be in poll transfer mode, + * otherwise will be in async transfer mode. + * + * @param urb Usb request block. + * @return On success will return 0, and others indicate fail. + */ +int usbh_submit_urb(struct usbh_urb *urb); + +/** + * @brief Cancel a transfer request. + * + * This function will call When calls usbh_submit_urb and return -USB_ERR_TIMEOUT or -USB_ERR_SHUTDOWN. + * + * @param urb Usb request block. + * @return On success will return 0, and others indicate fail. + */ +int usbh_kill_urb(struct usbh_urb *urb); + +/* called by user */ +void USBH_IRQHandler(uint8_t busid); + +#ifdef __cplusplus +} +#endif + +#endif /* USB_HC_H */ diff --git a/ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_list.h b/ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_list.h new file mode 100644 index 0000000..3078a1f --- /dev/null +++ b/ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_list.h @@ -0,0 +1,459 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_LIST_H +#define USB_LIST_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * usb_container_of - return the member address of ptr, if the type of ptr is the + * struct type. + */ +#define usb_container_of(ptr, type, member) \ + ((type *)((char *)(ptr) - (unsigned long)(&((type *)0)->member))) + +/** + * Single List structure + */ +struct usb_slist_node { + struct usb_slist_node *next; /**< point to next node. */ +}; +typedef struct usb_slist_node usb_slist_t; /**< Type for single list. */ + +/** + * @brief initialize a single list + * + * @param l the single list to be initialized + */ +static inline void usb_slist_init(usb_slist_t *l) +{ + l->next = NULL; +} + +static inline void usb_slist_add_head(usb_slist_t *l, usb_slist_t *n) +{ + n->next = l->next; + l->next = n; +} + +static inline void usb_slist_add_tail(usb_slist_t *l, usb_slist_t *n) +{ + usb_slist_t *tmp = l; + + while (tmp->next) { + tmp = tmp->next; + } + + /* append the node to the tail */ + tmp->next = n; + n->next = NULL; +} + +static inline void usb_slist_insert(usb_slist_t *l, usb_slist_t *next, usb_slist_t *n) +{ + if (!next) { + usb_slist_add_tail(next, l); + return; + } + + while (l->next) { + if (l->next == next) { + l->next = n; + n->next = next; + } + + l = l->next; + } +} + +static inline usb_slist_t *usb_slist_remove(usb_slist_t *l, usb_slist_t *n) +{ + usb_slist_t *tmp = l; + /* remove slist head */ + while (tmp->next && tmp->next != n) { + tmp = tmp->next; + } + + /* remove node */ + if (tmp->next != (usb_slist_t *)0) { + tmp->next = tmp->next->next; + } + + return l; +} + +static inline unsigned int usb_slist_len(const usb_slist_t *l) +{ + unsigned int len = 0; + const usb_slist_t *list = l->next; + + while (list != NULL) { + list = list->next; + len++; + } + + return len; +} + +static inline unsigned int usb_slist_contains(usb_slist_t *l, usb_slist_t *n) +{ + while (l->next) { + if (l->next == n) { + return 0; + } + + l = l->next; + } + + return 1; +} + +static inline usb_slist_t *usb_slist_head(usb_slist_t *l) +{ + return l->next; +} + +static inline usb_slist_t *usb_slist_tail(usb_slist_t *l) +{ + while (l->next) { + l = l->next; + } + + return l; +} + +static inline usb_slist_t *usb_slist_next(usb_slist_t *n) +{ + return n->next; +} + +static inline int usb_slist_isempty(usb_slist_t *l) +{ + return l->next == NULL; +} + +/** + * @brief initialize a slist object + */ +#define USB_SLIST_OBJECT_INIT(object) \ + { \ + NULL \ + } + +/** + * @brief initialize a slist object + */ +#define USB_SLIST_DEFINE(slist) \ + usb_slist_t slist = { NULL } + +/** + * @brief get the struct for this single list node + * @param node the entry point + * @param type the type of structure + * @param member the name of list in structure + */ +#define usb_slist_entry(node, type, member) \ + usb_container_of(node, type, member) + +/** + * usb_slist_first_entry - get the first element from a slist + * @ptr: the slist head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the slist_struct within the struct. + * + * Note, that slist is expected to be not empty. + */ +#define usb_slist_first_entry(ptr, type, member) \ + usb_slist_entry((ptr)->next, type, member) + +/** + * usb_slist_tail_entry - get the tail element from a slist + * @ptr: the slist head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the slist_struct within the struct. + * + * Note, that slist is expected to be not empty. + */ +#define usb_slist_tail_entry(ptr, type, member) \ + usb_slist_entry(usb_slist_tail(ptr), type, member) + +/** + * usb_slist_first_entry_or_null - get the first element from a slist + * @ptr: the slist head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the slist_struct within the struct. + * + * Note, that slist is expected to be not empty. + */ +#define usb_slist_first_entry_or_null(ptr, type, member) \ + (usb_slist_isempty(ptr) ? NULL : usb_slist_first_entry(ptr, type, member)) + +/** + * usb_slist_for_each - iterate over a single list + * @pos: the usb_slist_t * to use as a loop cursor. + * @head: the head for your single list. + */ +#define usb_slist_for_each(pos, head) \ + for (pos = (head)->next; pos != NULL; pos = pos->next) + +#define usb_slist_for_each_safe(pos, next, head) \ + for (pos = (head)->next, next = pos->next; pos; \ + pos = next, next = pos->next) + +/** + * usb_slist_for_each_entry - iterate over single list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your single list. + * @member: the name of the list_struct within the struct. + */ +#define usb_slist_for_each_entry(pos, head, member) \ + for (pos = usb_slist_entry((head)->next, typeof(*pos), member); \ + &pos->member != (NULL); \ + pos = usb_slist_entry(pos->member.next, typeof(*pos), member)) + +#define usb_slist_for_each_entry_safe(pos, n, head, member) \ + for (pos = usb_slist_entry((head)->next, typeof(*pos), member), \ + n = usb_slist_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (NULL); \ + pos = n, n = usb_slist_entry(pos->member.next, typeof(*pos), member)) + +/** + * Double List structure + */ +struct usb_dlist_node { + struct usb_dlist_node *next; /**< point to next node. */ + struct usb_dlist_node *prev; /**< point to prev node. */ +}; +typedef struct usb_dlist_node usb_dlist_t; /**< Type for lists. */ + +/** + * @brief initialize a list + * + * @param l list to be initialized + */ +static inline void usb_dlist_init(usb_dlist_t *l) +{ + l->next = l->prev = l; +} + +/** + * @brief insert a node after a list + * + * @param l list to insert it + * @param n new node to be inserted + */ +static inline void usb_dlist_insert_after(usb_dlist_t *l, usb_dlist_t *n) +{ + l->next->prev = n; + n->next = l->next; + + l->next = n; + n->prev = l; +} + +/** + * @brief insert a node before a list + * + * @param n new node to be inserted + * @param l list to insert it + */ +static inline void usb_dlist_insert_before(usb_dlist_t *l, usb_dlist_t *n) +{ + l->prev->next = n; + n->prev = l->prev; + + l->prev = n; + n->next = l; +} + +/** + * @brief remove node from list. + * @param n the node to remove from the list. + */ +static inline void usb_dlist_remove(usb_dlist_t *n) +{ + n->next->prev = n->prev; + n->prev->next = n->next; + + n->next = n->prev = n; +} + +/** + * @brief move node from list. + * @param n the node to remove from the list. + */ +static inline void usb_dlist_move_head(usb_dlist_t *l, usb_dlist_t *n) +{ + usb_dlist_remove(n); + usb_dlist_insert_after(l, n); +} + +/** + * @brief move node from list. + * @param n the node to remove from the list. + */ +static inline void usb_dlist_move_tail(usb_dlist_t *l, usb_dlist_t *n) +{ + usb_dlist_remove(n); + usb_dlist_insert_before(l, n); +} + +/** + * @brief tests whether a list is empty + * @param l the list to test. + */ +static inline int usb_dlist_isempty(const usb_dlist_t *l) +{ + return l->next == l; +} + +/** + * @brief get the list length + * @param l the list to get. + */ +static inline unsigned int usb_dlist_len(const usb_dlist_t *l) +{ + unsigned int len = 0; + const usb_dlist_t *p = l; + + while (p->next != l) { + p = p->next; + len++; + } + + return len; +} + +/** + * @brief initialize a dlist object + */ +#define USB_DLIST_OBJECT_INIT(object) \ + { \ + &(object), &(object) \ + } +/** + * @brief initialize a dlist object + */ +#define USB_DLIST_DEFINE(list) \ + usb_dlist_t list = { &(list), &(list) } + +/** + * @brief get the struct for this entry + * @param node the entry point + * @param type the type of structure + * @param member the name of list in structure + */ +#define usb_dlist_entry(node, type, member) \ + usb_container_of(node, type, member) + +/** + * dlist_first_entry - get the first element from a list + * @ptr: the list head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_struct within the struct. + * + * Note, that list is expected to be not empty. + */ +#define usb_dlist_first_entry(ptr, type, member) \ + usb_dlist_entry((ptr)->next, type, member) +/** + * dlist_first_entry_or_null - get the first element from a list + * @ptr: the list head to take the element from. + * @type: the type of the struct this is embedded in. + * @member: the name of the list_struct within the struct. + * + * Note, that list is expected to be not empty. + */ +#define usb_dlist_first_entry_or_null(ptr, type, member) \ + (usb_dlist_isempty(ptr) ? NULL : usb_dlist_first_entry(ptr, type, member)) + +/** + * usb_dlist_for_each - iterate over a list + * @pos: the usb_dlist_t * to use as a loop cursor. + * @head: the head for your list. + */ +#define usb_dlist_for_each(pos, head) \ + for (pos = (head)->next; pos != (head); pos = pos->next) + +/** + * usb_dlist_for_each_prev - iterate over a list + * @pos: the dlist_t * to use as a loop cursor. + * @head: the head for your list. + */ +#define usb_dlist_for_each_prev(pos, head) \ + for (pos = (head)->prev; pos != (head); pos = pos->prev) + +/** + * usb_dlist_for_each_safe - iterate over a list safe against removal of list entry + * @pos: the dlist_t * to use as a loop cursor. + * @n: another dlist_t * to use as temporary storage + * @head: the head for your list. + */ +#define usb_dlist_for_each_safe(pos, n, head) \ + for (pos = (head)->next, n = pos->next; pos != (head); \ + pos = n, n = pos->next) + +#define usb_dlist_for_each_prev_safe(pos, n, head) \ + for (pos = (head)->prev, n = pos->prev; pos != (head); \ + pos = n, n = pos->prev) +/** + * usb_dlist_for_each_entry - iterate over list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define usb_dlist_for_each_entry(pos, head, member) \ + for (pos = usb_dlist_entry((head)->next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = usb_dlist_entry(pos->member.next, typeof(*pos), member)) + +/** + * usb_usb_dlist_for_each_entry_reverse - iterate over list of given type + * @pos: the type * to use as a loop cursor. + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define usb_dlist_for_each_entry_reverse(pos, head, member) \ + for (pos = usb_dlist_entry((head)->prev, typeof(*pos), member); \ + &pos->member != (head); \ + pos = usb_dlist_entry(pos->member.prev, typeof(*pos), member)) + +/** + * usb_usb_dlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define usb_dlist_for_each_entry_safe(pos, n, head, member) \ + for (pos = usb_dlist_entry((head)->next, typeof(*pos), member), \ + n = usb_dlist_entry(pos->member.next, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = usb_dlist_entry(n->member.next, typeof(*n), member)) + +/** + * usb_usb_dlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry + * @pos: the type * to use as a loop cursor. + * @n: another type * to use as temporary storage + * @head: the head for your list. + * @member: the name of the list_struct within the struct. + */ +#define usb_dlist_for_each_entry_safe_reverse(pos, n, head, member) \ + for (pos = usb_dlist_entry((head)->prev, typeof(*pos), field), \ + n = usb_dlist_entry(pos->member.prev, typeof(*pos), member); \ + &pos->member != (head); \ + pos = n, n = usb_dlist_entry(pos->member.prev, typeof(*pos), member)) + +#ifdef __cplusplus +} +#endif + +#endif /* USB_LIST_H */ diff --git a/ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_log.h b/ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_log.h new file mode 100644 index 0000000..94eedfb --- /dev/null +++ b/ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_log.h @@ -0,0 +1,114 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_LOG_H +#define USB_LOG_H + +#include + +/* DEBUG level */ +#define USB_DBG_ERROR 0 +#define USB_DBG_WARNING 1 +#define USB_DBG_INFO 2 +#define USB_DBG_LOG 3 + +#ifndef USB_DBG_TAG +#define USB_DBG_TAG "USB" +#endif +/* + * The color for terminal (foreground) + * BLACK 30 + * RED 31 + * GREEN 32 + * YELLOW 33 + * BLUE 34 + * PURPLE 35 + * CYAN 36 + * WHITE 37 + */ + +#ifdef CONFIG_USB_PRINTF_COLOR_ENABLE +#define _USB_DBG_COLOR(n) CONFIG_USB_PRINTF("\033[" #n "m") +#define _USB_DBG_LOG_HDR(lvl_name, color_n) \ + CONFIG_USB_PRINTF("\033[" #color_n "m[" lvl_name "/" USB_DBG_TAG "] ") +#define _USB_DBG_LOG_X_END \ + CONFIG_USB_PRINTF("\033[0m") +#else +#define _USB_DBG_COLOR(n) +#define _USB_DBG_LOG_HDR(lvl_name, color_n) \ + CONFIG_USB_PRINTF("[" lvl_name "/" USB_DBG_TAG "] ") +#define _USB_DBG_LOG_X_END +#endif + +#define usb_dbg_log_line(lvl, color_n, fmt, ...) \ + do { \ + _USB_DBG_LOG_HDR(lvl, color_n); \ + CONFIG_USB_PRINTF(fmt, ##__VA_ARGS__); \ + _USB_DBG_LOG_X_END; \ + } while (0) + +#if (CONFIG_USB_DBG_LEVEL >= USB_DBG_LOG) +#define USB_LOG_DBG(fmt, ...) usb_dbg_log_line("D", 0, fmt, ##__VA_ARGS__) +#else +#define USB_LOG_DBG(...) {} +#endif + +#if (CONFIG_USB_DBG_LEVEL >= USB_DBG_INFO) +#define USB_LOG_INFO(fmt, ...) usb_dbg_log_line("I", 32, fmt, ##__VA_ARGS__) +#else +#define USB_LOG_INFO(...) {} +#endif + +#if (CONFIG_USB_DBG_LEVEL >= USB_DBG_WARNING) +#define USB_LOG_WRN(fmt, ...) usb_dbg_log_line("W", 33, fmt, ##__VA_ARGS__) +#else +#define USB_LOG_WRN(...) {} +#endif + +#if (CONFIG_USB_DBG_LEVEL >= USB_DBG_ERROR) +#define USB_LOG_ERR(fmt, ...) usb_dbg_log_line("E", 31, fmt, ##__VA_ARGS__) +#else +#define USB_LOG_ERR(...) {} +#endif + +#define USB_LOG_RAW(...) CONFIG_USB_PRINTF(__VA_ARGS__) + +void usb_assert(const char *filename, int linenum); +#define USB_ASSERT(f) \ + do { \ + if (!(f)) \ + usb_assert(__FILE__, __LINE__); \ + } while (0) + +#define ___is_print(ch) ((unsigned int)((ch) - ' ') < 127u - ' ') +static inline void usb_hexdump(const void *ptr, uint32_t buflen) +{ + unsigned char *buf = (unsigned char *)ptr; + unsigned int i, j; + + (void)buf; + + for (i = 0; i < buflen; i += 16) { + CONFIG_USB_PRINTF("%08x:", i); + + for (j = 0; j < 16; j++) + if (i + j < buflen) { + if ((j % 8) == 0) { + CONFIG_USB_PRINTF(" "); + } + + CONFIG_USB_PRINTF("%02X ", buf[i + j]); + } else + CONFIG_USB_PRINTF(" "); + CONFIG_USB_PRINTF(" "); + + for (j = 0; j < 16; j++) + if (i + j < buflen) + CONFIG_USB_PRINTF("%c", ___is_print(buf[i + j]) ? buf[i + j] : '.'); + CONFIG_USB_PRINTF("\n"); + } +} + +#endif /* USB_LOG_H */ diff --git a/ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_memcpy.h b/ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_memcpy.h new file mode 100644 index 0000000..85cac31 --- /dev/null +++ b/ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_memcpy.h @@ -0,0 +1,91 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_MEMCPY_H +#define USB_MEMCPY_H + +#include +#include + +#define ALIGN_UP_DWORD(x) ((uint32_t)(uintptr_t)(x) & (sizeof(uint32_t) - 1)) + +static inline void dword2array(char *addr, uint32_t w) +{ + addr[0] = w; + addr[1] = w >> 8; + addr[2] = w >> 16; + addr[3] = w >> 24; +} + +static inline void *usb_memcpy(void *s1, const void *s2, size_t n) +{ + char *b1 = (char *)s1; + const char *b2 = (const char *)s2; + uint32_t *w1; + const uint32_t *w2; + + if (ALIGN_UP_DWORD(b1) == ALIGN_UP_DWORD(b2)) { + while (ALIGN_UP_DWORD(b1) != 0 && n > 0) { + *b1++ = *b2++; + --n; + } + + w1 = (uint32_t *)b1; + w2 = (const uint32_t *)b2; + + while (n >= 4 * sizeof(uint32_t)) { + *w1++ = *w2++; + *w1++ = *w2++; + *w1++ = *w2++; + *w1++ = *w2++; + n -= 4 * sizeof(uint32_t); + } + + while (n >= sizeof(uint32_t)) { + *w1++ = *w2++; + n -= sizeof(uint32_t); + } + + b1 = (char *)w1; + b2 = (const char *)w2; + + while (n--) { + *b1++ = *b2++; + } + } else { + while (n > 0 && ALIGN_UP_DWORD(b2) != 0) { + *b1++ = *b2++; + --n; + } + + w2 = (const uint32_t *)b2; + + while (n >= 4 * sizeof(uint32_t)) { + dword2array(b1, *w2++); + b1 += sizeof(uint32_t); + dword2array(b1, *w2++); + b1 += sizeof(uint32_t); + dword2array(b1, *w2++); + b1 += sizeof(uint32_t); + dword2array(b1, *w2++); + b1 += sizeof(uint32_t); + n -= 4 * sizeof(uint32_t); + } + + while (n >= sizeof(uint32_t)) { + dword2array(b1, *w2++); + b1 += sizeof(uint32_t); + n -= sizeof(uint32_t); + } + + b2 = (const char *)w2; + + while (n--) { + *b1++ = *b2++; + } + } + return s1; +} +#endif diff --git a/ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_osal.h b/ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_osal.h new file mode 100644 index 0000000..aa2f133 --- /dev/null +++ b/ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_osal.h @@ -0,0 +1,72 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_OSAL_H +#define USB_OSAL_H + +#include +#include +#include + +#ifdef __INCLUDE_NUTTX_CONFIG_H +#define CONFIG_USB_OSAL_THREAD_SET_ARGV int argc, char **argv +#define CONFIG_USB_OSAL_THREAD_GET_ARGV ((uintptr_t)strtoul(argv[1], NULL, 16)) +#else +#define CONFIG_USB_OSAL_THREAD_SET_ARGV void *argument +#define CONFIG_USB_OSAL_THREAD_GET_ARGV ((uintptr_t)argument) +#endif + +#define USB_OSAL_WAITING_FOREVER (0xFFFFFFFFU) + +typedef void *usb_osal_thread_t; +typedef void *usb_osal_sem_t; +typedef void *usb_osal_mutex_t; +typedef void *usb_osal_mq_t; +typedef void (*usb_thread_entry_t)(CONFIG_USB_OSAL_THREAD_SET_ARGV); +typedef void (*usb_timer_handler_t)(void *argument); +struct usb_osal_timer { + usb_timer_handler_t handler; + void *argument; + bool is_period; + uint32_t ticks; + void *timer; +}; + +/* + * Task with smaller priority value indicates higher task priority +*/ +usb_osal_thread_t usb_osal_thread_create(const char *name, uint32_t stack_size, uint32_t prio, usb_thread_entry_t entry, void *args); +void usb_osal_thread_delete(usb_osal_thread_t thread); + +usb_osal_sem_t usb_osal_sem_create(uint32_t initial_count); +void usb_osal_sem_delete(usb_osal_sem_t sem); +int usb_osal_sem_take(usb_osal_sem_t sem, uint32_t timeout); +int usb_osal_sem_give(usb_osal_sem_t sem); +void usb_osal_sem_reset(usb_osal_sem_t sem); + +usb_osal_mutex_t usb_osal_mutex_create(void); +void usb_osal_mutex_delete(usb_osal_mutex_t mutex); +int usb_osal_mutex_take(usb_osal_mutex_t mutex); +int usb_osal_mutex_give(usb_osal_mutex_t mutex); + +usb_osal_mq_t usb_osal_mq_create(uint32_t max_msgs); +void usb_osal_mq_delete(usb_osal_mq_t mq); +int usb_osal_mq_send(usb_osal_mq_t mq, uintptr_t addr); +int usb_osal_mq_recv(usb_osal_mq_t mq, uintptr_t *addr, uint32_t timeout); + +struct usb_osal_timer *usb_osal_timer_create(const char *name, uint32_t timeout_ms, usb_timer_handler_t handler, void *argument, bool is_period); +void usb_osal_timer_delete(struct usb_osal_timer *timer); +void usb_osal_timer_start(struct usb_osal_timer *timer); +void usb_osal_timer_stop(struct usb_osal_timer *timer); + +size_t usb_osal_enter_critical_section(void); +void usb_osal_leave_critical_section(size_t flag); + +void usb_osal_msleep(uint32_t delay); + +void *usb_osal_malloc(size_t size); +void usb_osal_free(void *ptr); + +#endif /* USB_OSAL_H */ diff --git a/ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_otg.h b/ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_otg.h new file mode 100644 index 0000000..6adf545 --- /dev/null +++ b/ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_otg.h @@ -0,0 +1,41 @@ +/* + * Copyright (c) 2025, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_OTG_H +#define USB_OTG_H + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @brief usb otg controller hardware or gpio id simulator init. + * + * @return On success will return 0, and others indicate fail. + */ +int usb_otg_init(uint8_t busid); +/** + * @brief usb otg controller hardware or gpio id simulator deinit. + * + * @return On success will return 0, and others indicate fail. + */ +int usb_otg_deinit(uint8_t busid); +/** + * @brief get current role mode. + * + * @return return USBOTG_MODE_HOST or USBOTG_MODE_DEVICE. + */ +uint8_t usbotg_get_current_mode(uint8_t busid); + +/* called by user */ +void USBOTG_IRQHandler(uint8_t busid); + +#ifdef __cplusplus +} +#endif + +#endif /* USB_OTG_H */ \ No newline at end of file diff --git a/ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_util.h b/ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_util.h new file mode 100644 index 0000000..b2223b2 --- /dev/null +++ b/ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_util.h @@ -0,0 +1,218 @@ +/* + * Copyright (c) 2022-2023, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_UTIL_H +#define USB_UTIL_H + +#if defined(__CC_ARM) +#ifndef __USED +#define __USED __attribute__((used)) +#endif +#ifndef __WEAK +#define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED +#define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT +#define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION +#define __PACKED_UNION __packed union +#endif +#ifndef __ALIGNED +#define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#elif defined(__GNUC__) +#ifndef __USED +#define __USED __attribute__((used)) +#endif +#ifndef __WEAK +#define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED +#define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT +#define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION +#define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __ALIGNED +#define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#elif defined(__ICCARM__) || defined(__ICCRX__) || defined(__ICCRISCV__) +#ifndef __USED +#if defined(__ICCARM_V8) || defined(__ICCRISCV__) +#define __USED __attribute__((used)) +#else +#define __USED __root +#endif +#endif + +#ifndef __WEAK +#if defined(__ICCARM_V8) || defined(__ICCRISCV__) +#define __WEAK __attribute__((weak)) +#else +#define __WEAK _Pragma("__weak") +#endif +#endif + +#ifndef __PACKED +#if defined(__ICCARM_V8) || defined(__ICCRISCV__) +#define __PACKED __attribute__((packed, aligned(1))) +#else +/* Needs IAR language extensions */ +#define __PACKED __packed +#endif +#endif + +#ifndef __PACKED_STRUCT +#if defined(__ICCARM_V8) || defined(__ICCRISCV__) +#define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#else +/* Needs IAR language extensions */ +#define __PACKED_STRUCT __packed struct +#endif +#endif + +#ifndef __PACKED_UNION +#if defined(__ICCARM_V8) || defined(__ICCRISCV__) +#define __PACKED_UNION union __attribute__((packed, aligned(1))) +#else +/* Needs IAR language extensions */ +#define __PACKED_UNION __packed union +#endif +#endif + +#ifndef __ALIGNED +#if defined(__ICCARM_V8) || defined(__ICCRISCV__) +#define __ALIGNED(x) __attribute__((aligned(x))) +#elif (__VER__ >= 7080000) +/* Needs IAR language extensions */ +#define __ALIGNED(x) __attribute__((aligned(x))) +#else +#warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. +#define __ALIGNED(x) +#endif +#endif + +#endif + +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN +#endif +#ifndef __ALIGN_END +#define __ALIGN_END __attribute__((aligned(4))) +#endif + +#ifndef ARG_UNUSED +#define ARG_UNUSED(x) (void)(x) +#endif + +#ifndef LO_BYTE +#define LO_BYTE(x) ((uint8_t)(x & 0x00FF)) +#endif + +#ifndef HI_BYTE +#define HI_BYTE(x) ((uint8_t)((x & 0xFF00) >> 8)) +#endif + +#ifndef MAX +#define MAX(a, b) (((a) > (b)) ? (a) : (b)) +#endif + +#ifndef MIN +#define MIN(a, b) (((a) < (b)) ? (a) : (b)) +#endif + +#ifndef BCD +#define BCD(x) ((((x) / 10) << 4) | ((x) % 10)) +#endif + +#ifdef BIT +#undef BIT +#define BIT(n) (1UL << (n)) +#else +#define BIT(n) (1UL << (n)) +#endif + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(array) \ + ((int)((sizeof(array) / sizeof((array)[0])))) +#endif + +#ifndef BSWAP16 +#define BSWAP16(u16) (__builtin_bswap16(u16)) +#endif +#ifndef BSWAP32 +#define BSWAP32(u32) (__builtin_bswap32(u32)) +#endif + +#define GET_BE16(field) \ + (((uint16_t)(field)[0] << 8) | ((uint16_t)(field)[1])) + +#define GET_BE32(field) \ + (((uint32_t)(field)[0] << 24) | ((uint32_t)(field)[1] << 16) | ((uint32_t)(field)[2] << 8) | ((uint32_t)(field)[3] << 0)) + +#define SET_BE16(field, value) \ + do { \ + (field)[0] = (uint8_t)((value) >> 8); \ + (field)[1] = (uint8_t)((value) >> 0); \ + } while (0) + +#define SET_BE24(field, value) \ + do { \ + (field)[0] = (uint8_t)((value) >> 16); \ + (field)[1] = (uint8_t)((value) >> 8); \ + (field)[2] = (uint8_t)((value) >> 0); \ + } while (0) + +#define SET_BE32(field, value) \ + do { \ + (field)[0] = (uint8_t)((value) >> 24); \ + (field)[1] = (uint8_t)((value) >> 16); \ + (field)[2] = (uint8_t)((value) >> 8); \ + (field)[3] = (uint8_t)((value) >> 0); \ + } while (0) + +#define WBVAL(x) (x & 0xFF), ((x >> 8) & 0xFF) +#define DBVAL(x) (x & 0xFF), ((x >> 8) & 0xFF), ((x >> 16) & 0xFF), ((x >> 24) & 0xFF) + +#define PP_NARG(...) \ + PP_NARG_(__VA_ARGS__, PP_RSEQ_N()) +#define PP_NARG_(...) \ + PP_ARG_N(__VA_ARGS__) +#define PP_ARG_N( \ + _1, _2, _3, _4, _5, _6, _7, _8, _9, _10, \ + _11, _12, _13, _14, _15, _16, _17, _18, _19, _20, \ + _21, _22, _23, _24, _25, _26, _27, _28, _29, _30, \ + _31, _32, _33, _34, _35, _36, _37, _38, _39, _40, \ + _41, _42, _43, _44, _45, _46, _47, _48, _49, _50, \ + _51, _52, _53, _54, _55, _56, _57, _58, _59, _60, \ + _61, _62, _63, N, ...) N +#define PP_RSEQ_N() \ + 63, 62, 61, 60, \ + 59, 58, 57, 56, 55, 54, 53, 52, 51, 50, \ + 49, 48, 47, 46, 45, 44, 43, 42, 41, 40, \ + 39, 38, 37, 36, 35, 34, 33, 32, 31, 30, \ + 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, \ + 19, 18, 17, 16, 15, 14, 13, 12, 11, 10, \ + 9, 8, 7, 6, 5, 4, 3, 2, 1, 0 + +#define USB_MEM_ALIGNX __attribute__((aligned(CONFIG_USB_ALIGN_SIZE))) + +#define USB_ALIGN_UP(size, align) (((size) + (align)-1) & ~((align)-1)) + +#ifndef usb_phyaddr2ramaddr +#define usb_phyaddr2ramaddr(addr) (addr) +#endif + +#ifndef usb_ramaddr2phyaddr +#define usb_ramaddr2phyaddr(addr) (addr) +#endif + +#endif /* USB_UTIL_H */ diff --git a/ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_version.h b/ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_version.h new file mode 100644 index 0000000..1d3f93e --- /dev/null +++ b/ch32v103_hallarray_controller/3rdparty/CherryUSB/common/usb_version.h @@ -0,0 +1,21 @@ +/* + * Copyright (c) 2024, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USB_VERSION_H +#define USB_VERSION_H + +#ifdef CHERRYUSB_VERSION +#warning "Please do not define CHERRYUSB_VERSION in usb_config.h" +#undef CHERRYUSB_VERSION +#endif +#ifdef CHERRYUSB_VERSION_STR +#warning "Please do not define CHERRYUSB_VERSION_STR in usb_config.h" +#undef CHERRYUSB_VERSION_STR +#endif + +#define CHERRYUSB_VERSION 0x010403 +#define CHERRYUSB_VERSION_STR "v1.4.3" + +#endif \ No newline at end of file diff --git a/ch32v103_hallarray_controller/3rdparty/CherryUSB/core/usbd_core.c b/ch32v103_hallarray_controller/3rdparty/CherryUSB/core/usbd_core.c new file mode 100644 index 0000000..2a2fda4 --- /dev/null +++ b/ch32v103_hallarray_controller/3rdparty/CherryUSB/core/usbd_core.c @@ -0,0 +1,1527 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#ifdef CONFIG_USBDEV_EP0_THREAD +#include "usb_osal.h" + +#define USB_EP0_STATE_SETUP 0 +#define USB_EP0_STATE_IN 1 +#define USB_EP0_STATE_OUT 2 +#endif + +#undef USB_DBG_TAG +#define USB_DBG_TAG "usbd_core" +#include "usb_log.h" + +/* general descriptor field offsets */ +#define DESC_bLength 0 /** Length offset */ +#define DESC_bDescriptorType 1 /** Descriptor type offset */ + +/* config descriptor field offsets */ +#define CONF_DESC_wTotalLength 2 /** Total length offset */ +#define CONF_DESC_bConfigurationValue 5 /** Configuration value offset */ +#define CONF_DESC_bmAttributes 7 /** configuration characteristics */ + +/* interface descriptor field offsets */ +#define INTF_DESC_bInterfaceNumber 2 /** Interface number offset */ +#define INTF_DESC_bAlternateSetting 3 /** Alternate setting offset */ + +struct usbd_tx_rx_msg { + uint8_t ep; + uint8_t ep_mult; + uint16_t ep_mps; + uint32_t nbytes; + usbd_endpoint_callback cb; +}; + +USB_NOCACHE_RAM_SECTION struct usbd_core_priv { + /** Setup packet */ + USB_MEM_ALIGNX struct usb_setup_packet setup; + /** Pointer to data buffer */ + uint8_t *ep0_data_buf; + /** Remaining bytes in buffer */ + uint32_t ep0_data_buf_residue; + /** Total length of control transfer */ + uint32_t ep0_data_buf_len; + /** Zero length packet flag of control transfer */ + bool zlp_flag; + /** Pointer to registered descriptors */ +#ifdef CONFIG_USBDEV_ADVANCE_DESC + const struct usb_descriptor *descriptors; +#else + const uint8_t *descriptors; + struct usb_msosv1_descriptor *msosv1_desc; + struct usb_msosv2_descriptor *msosv2_desc; + struct usb_bos_descriptor *bos_desc; + struct usb_webusb_descriptor *webusb_url_desc; +#endif + /* Buffer used for storing standard, class and vendor request data */ + USB_MEM_ALIGNX uint8_t req_data[CONFIG_USBDEV_REQUEST_BUFFER_LEN]; + + /** Currently selected configuration */ + uint8_t configuration; + uint8_t device_address; + bool self_powered; + bool remote_wakeup_support; + bool remote_wakeup_enabled; + bool is_suspend; +#ifdef CONFIG_USBDEV_ADVANCE_DESC + uint8_t speed; +#endif +#ifdef CONFIG_USBDEV_TEST_MODE + bool test_req; +#endif +#ifdef CONFIG_USBDEV_EP0_THREAD + usb_osal_mq_t usbd_ep0_mq; + usb_osal_thread_t usbd_ep0_thread; +#endif + struct usbd_interface *intf[16]; + uint8_t intf_altsetting[16]; + uint8_t intf_offset; + + struct usbd_tx_rx_msg tx_msg[CONFIG_USBDEV_EP_NUM]; + struct usbd_tx_rx_msg rx_msg[CONFIG_USBDEV_EP_NUM]; + + void (*event_handler)(uint8_t busid, uint8_t event); +} g_usbd_core[CONFIG_USBDEV_MAX_BUS]; + +struct usbd_bus g_usbdev_bus[CONFIG_USBDEV_MAX_BUS]; + +static void usbd_class_event_notify_handler(uint8_t busid, uint8_t event, void *arg); + +static void usbd_print_setup(struct usb_setup_packet *setup) +{ + USB_LOG_INFO("Setup: " + "bmRequestType 0x%02x, bRequest 0x%02x, wValue 0x%04x, wIndex 0x%04x, wLength 0x%04x\r\n", + setup->bmRequestType, + setup->bRequest, + setup->wValue, + setup->wIndex, + setup->wLength); +} + +static bool is_device_configured(uint8_t busid) +{ + return (g_usbd_core[busid].configuration != 0); +} + +/** + * @brief configure and enable endpoint + * + * This function sets endpoint configuration according to one specified in USB + * endpoint descriptor and then enables it for data transfers. + * + * @param [in] busid busid + * @param [in] ep Endpoint descriptor byte array + * + * @return true if successfully configured and enabled + */ +static bool usbd_set_endpoint(uint8_t busid, const struct usb_endpoint_descriptor *ep) +{ + USB_LOG_DBG("Open ep:0x%02x type:%u mps:%u\r\n", + ep->bEndpointAddress, + USB_GET_ENDPOINT_TYPE(ep->bmAttributes), + USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize)); + + if (ep->bEndpointAddress & 0x80) { + g_usbd_core[busid].tx_msg[ep->bEndpointAddress & 0x7f].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_usbd_core[busid].tx_msg[ep->bEndpointAddress & 0x7f].ep_mult = USB_GET_MULT(ep->wMaxPacketSize); + } else { + g_usbd_core[busid].rx_msg[ep->bEndpointAddress & 0x7f].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_usbd_core[busid].rx_msg[ep->bEndpointAddress & 0x7f].ep_mult = USB_GET_MULT(ep->wMaxPacketSize); + } + + return usbd_ep_open(busid, ep) == 0 ? true : false; +} +/** + * @brief Disable endpoint for transferring data + * + * This function cancels transfers that are associated with endpoint and + * disabled endpoint itself. + * + * @param [in] busid busid + * @param [in] ep Endpoint descriptor byte array + * + * @return true if successfully deconfigured and disabled + */ +static bool usbd_reset_endpoint(uint8_t busid, const struct usb_endpoint_descriptor *ep) +{ + USB_LOG_DBG("Close ep:0x%02x type:%u\r\n", + ep->bEndpointAddress, + USB_GET_ENDPOINT_TYPE(ep->bmAttributes)); + + return usbd_ep_close(busid, ep->bEndpointAddress) == 0 ? true : false; +} + +/** + * @brief get specified USB descriptor + * + * This function parses the list of installed USB descriptors and attempts + * to find the specified USB descriptor. + * + * @param [in] busid busid + * @param [in] type_index Type and index of the descriptor + * @param [out] data Descriptor data + * @param [out] len Descriptor length + * + * @return true if the descriptor was found, false otherwise + */ +#ifdef CONFIG_USBDEV_ADVANCE_DESC +static bool usbd_get_descriptor(uint8_t busid, uint16_t type_index, uint8_t **data, uint32_t *len) +{ + uint8_t type = 0U; + uint8_t index = 0U; + bool found = true; + uint32_t desc_len = 0; + const char *string = NULL; + const uint8_t *desc = NULL; + + type = HI_BYTE(type_index); + index = LO_BYTE(type_index); + + switch (type) { + case USB_DESCRIPTOR_TYPE_DEVICE: + g_usbd_core[busid].speed = usbd_get_port_speed(busid); /* before we get device descriptor, we have known steady port speed */ + desc = g_usbd_core[busid].descriptors->device_descriptor_callback(g_usbd_core[busid].speed); + if (desc == NULL) { + found = false; + break; + } + desc_len = desc[0]; + break; + case USB_DESCRIPTOR_TYPE_CONFIGURATION: + desc = g_usbd_core[busid].descriptors->config_descriptor_callback(g_usbd_core[busid].speed); + if (desc == NULL) { + found = false; + break; + } + desc_len = ((desc[CONF_DESC_wTotalLength]) | (desc[CONF_DESC_wTotalLength + 1] << 8)); + + g_usbd_core[busid].self_powered = (desc[7] & USB_CONFIG_POWERED_MASK) ? true : false; + g_usbd_core[busid].remote_wakeup_support = (desc[7] & USB_CONFIG_REMOTE_WAKEUP) ? true : false; + break; + case USB_DESCRIPTOR_TYPE_STRING: + if (index == USB_OSDESC_STRING_DESC_INDEX) { + if (!g_usbd_core[busid].descriptors->msosv1_descriptor) { + found = false; + break; + } + + desc = (uint8_t *)g_usbd_core[busid].descriptors->msosv1_descriptor->string; + desc_len = g_usbd_core[busid].descriptors->msosv1_descriptor->string[0]; + } else { + string = g_usbd_core[busid].descriptors->string_descriptor_callback(g_usbd_core[busid].speed, index); + if (string == NULL) { + found = false; + break; + } + + if (index == USB_STRING_LANGID_INDEX) { + (*data)[0] = 4; + (*data)[1] = USB_DESCRIPTOR_TYPE_STRING; + (*data)[2] = string[0]; + (*data)[3] = string[1]; + + *len = 4; + return true; + } + + uint16_t str_size = strlen(string); + uint16_t total_size = 2 * str_size + 2; + if (total_size > CONFIG_USBDEV_REQUEST_BUFFER_LEN) { + USB_LOG_ERR("string size overflow\r\n"); + return false; + } + + (*data)[0] = total_size; + (*data)[1] = USB_DESCRIPTOR_TYPE_STRING; + + for (uint16_t i = 0; i < str_size; i++) { + (*data)[2 * i + 2] = string[i]; + (*data)[2 * i + 3] = 0x00; + } + + *len = total_size; + return true; + } + break; + case USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER: +#ifndef CONFIG_USB_HS + return false; +#else + desc = g_usbd_core[busid].descriptors->device_quality_descriptor_callback(g_usbd_core[busid].speed); + if (desc == NULL) { + found = false; + break; + } + desc_len = desc[0]; + break; +#endif + case USB_DESCRIPTOR_TYPE_OTHER_SPEED: + desc = g_usbd_core[busid].descriptors->other_speed_descriptor_callback(g_usbd_core[busid].speed); + if (desc == NULL) { + found = false; + break; + } + desc_len = ((desc[CONF_DESC_wTotalLength]) | (desc[CONF_DESC_wTotalLength + 1] << 8)); + break; + + case USB_DESCRIPTOR_TYPE_BINARY_OBJECT_STORE: + if (!g_usbd_core[busid].descriptors->bos_descriptor) { + found = false; + break; + } + + desc = (uint8_t *)g_usbd_core[busid].descriptors->bos_descriptor->string; + desc_len = g_usbd_core[busid].descriptors->bos_descriptor->string_len; + break; + + default: + found = false; + break; + } + + if (found == false) { + /* nothing found */ + USB_LOG_ERR("descriptor not found!\r\n", type, index); + } else { + *data = (uint8_t *)desc; + //memcpy(*data, desc, desc_len); + *len = desc_len; + } + return found; +} +#else +static bool usbd_get_descriptor(uint8_t busid, uint16_t type_index, uint8_t **data, uint32_t *len) +{ + uint8_t type = 0U; + uint8_t index = 0U; + uint8_t *p = NULL; + uint32_t cur_index = 0U; + bool found = false; + + type = HI_BYTE(type_index); + index = LO_BYTE(type_index); + + if ((type == USB_DESCRIPTOR_TYPE_STRING) && (index == USB_OSDESC_STRING_DESC_INDEX)) { + if (!g_usbd_core[busid].msosv1_desc) { + return false; + } + + *data = (uint8_t *)g_usbd_core[busid].msosv1_desc->string; + //memcpy(*data, (uint8_t *)g_usbd_core[busid].msosv1_desc->string, g_usbd_core[busid].msosv1_desc->string[0]); + *len = g_usbd_core[busid].msosv1_desc->string[0]; + + return true; + } else if (type == USB_DESCRIPTOR_TYPE_BINARY_OBJECT_STORE) { + if (!g_usbd_core[busid].bos_desc) { + return false; + } + + *data = (uint8_t *)g_usbd_core[busid].bos_desc->string; + //memcpy(*data, (uint8_t *)g_usbd_core[busid].bos_desc->string, g_usbd_core[busid].bos_desc->string_len); + *len = g_usbd_core[busid].bos_desc->string_len; + return true; + } + /* + * Invalid types of descriptors, + * see USB Spec. Revision 2.0, 9.4.3 Get Descriptor + */ + else if ((type == USB_DESCRIPTOR_TYPE_INTERFACE) || (type == USB_DESCRIPTOR_TYPE_ENDPOINT) || +#ifndef CONFIG_USB_HS + (type > USB_DESCRIPTOR_TYPE_ENDPOINT)) { +#else + (type > USB_DESCRIPTOR_TYPE_OTHER_SPEED)) { +#endif + return false; + } + + p = (uint8_t *)g_usbd_core[busid].descriptors; + + cur_index = 0U; + + while (p[DESC_bLength] != 0U) { + if (p[DESC_bDescriptorType] == type) { + if (cur_index == index) { + found = true; + break; + } + + cur_index++; + } + + /* skip to next descriptor */ + p += p[DESC_bLength]; + } + + if (found) { + if ((type == USB_DESCRIPTOR_TYPE_CONFIGURATION) || ((type == USB_DESCRIPTOR_TYPE_OTHER_SPEED))) { + /* configuration or other speed descriptor is an + * exception, length is at offset 2 and 3 + */ + *len = (p[CONF_DESC_wTotalLength]) | + (p[CONF_DESC_wTotalLength + 1] << 8); + + g_usbd_core[busid].self_powered = (p[7] & USB_CONFIG_POWERED_MASK) ? true : false; + g_usbd_core[busid].remote_wakeup_support = (p[7] & USB_CONFIG_REMOTE_WAKEUP) ? true : false; + } else { + /* normally length is at offset 0 */ + *len = p[DESC_bLength]; + } + *data = p; + //memcpy(*data, p, *len); + } else { + /* nothing found */ + USB_LOG_ERR("descriptor not found!\r\n", type, index); + } + + return found; +} +#endif + +/** + * @brief set USB configuration + * + * This function configures the device according to the specified configuration + * index and alternate setting by parsing the installed USB descriptor list. + * A configuration index of 0 unconfigures the device. + * + * @param [in] busid busid + * @param [in] config_index Configuration index + * @param [in] alt_setting Alternate setting number + * + * @return true if successfully configured false if error or unconfigured + */ +static bool usbd_set_configuration(uint8_t busid, uint8_t config_index, uint8_t alt_setting) +{ + uint8_t cur_alt_setting = 0xFF; + uint8_t cur_config = 0xFF; + bool found = false; + const uint8_t *p; + uint32_t desc_len = 0; + uint32_t current_desc_len = 0; + +#ifdef CONFIG_USBDEV_ADVANCE_DESC + p = g_usbd_core[busid].descriptors->config_descriptor_callback(g_usbd_core[busid].speed); +#else + p = (uint8_t *)g_usbd_core[busid].descriptors; +#endif + /* configure endpoints for this configuration/altsetting */ + while (p[DESC_bLength] != 0U) { + switch (p[DESC_bDescriptorType]) { + case USB_DESCRIPTOR_TYPE_CONFIGURATION: + /* remember current configuration index */ + cur_config = p[CONF_DESC_bConfigurationValue]; + + if (cur_config == config_index) { + found = true; + + current_desc_len = 0; + desc_len = (p[CONF_DESC_wTotalLength]) | + (p[CONF_DESC_wTotalLength + 1] << 8); + } + + break; + + case USB_DESCRIPTOR_TYPE_INTERFACE: + /* remember current alternate setting */ + cur_alt_setting = + p[INTF_DESC_bAlternateSetting]; + break; + + case USB_DESCRIPTOR_TYPE_ENDPOINT: + if ((cur_config != config_index) || + (cur_alt_setting != alt_setting)) { + break; + } + + found = usbd_set_endpoint(busid, (struct usb_endpoint_descriptor *)p); + break; + + default: + break; + } + + /* skip to next descriptor */ + current_desc_len += p[DESC_bLength]; + p += p[DESC_bLength]; + if (current_desc_len >= desc_len && desc_len) { + break; + } + } + + return found; +} + +/** + * @brief set USB interface + * + * @param [in] busid busid + * @param [in] iface Interface index + * @param [in] alt_setting Alternate setting number + * + * @return true if successfully configured false if error or unconfigured + */ +static bool usbd_set_interface(uint8_t busid, uint8_t iface, uint8_t alt_setting) +{ + const uint8_t *if_desc = NULL; + struct usb_endpoint_descriptor *ep_desc; + uint8_t cur_alt_setting = 0xFF; + uint8_t cur_iface = 0xFF; + bool ret = false; + const uint8_t *p; + uint32_t desc_len = 0; + uint32_t current_desc_len = 0; + +#ifdef CONFIG_USBDEV_ADVANCE_DESC + p = g_usbd_core[busid].descriptors->config_descriptor_callback(g_usbd_core[busid].speed); +#else + p = (uint8_t *)g_usbd_core[busid].descriptors; +#endif + USB_LOG_DBG("iface %u alt_setting %u\r\n", iface, alt_setting); + + while (p[DESC_bLength] != 0U) { + switch (p[DESC_bDescriptorType]) { + case USB_DESCRIPTOR_TYPE_CONFIGURATION: + current_desc_len = 0; + desc_len = (p[CONF_DESC_wTotalLength]) | + (p[CONF_DESC_wTotalLength + 1] << 8); + + break; + + case USB_DESCRIPTOR_TYPE_INTERFACE: + /* remember current alternate setting */ + cur_alt_setting = p[INTF_DESC_bAlternateSetting]; + cur_iface = p[INTF_DESC_bInterfaceNumber]; + + if (cur_iface == iface && + cur_alt_setting == alt_setting) { + if_desc = (void *)p; + } + + USB_LOG_DBG("Current iface %u alt setting %u", + cur_iface, cur_alt_setting); + break; + + case USB_DESCRIPTOR_TYPE_ENDPOINT: + if (cur_iface == iface) { + ep_desc = (struct usb_endpoint_descriptor *)p; + + if (alt_setting == 0) { + ret = usbd_reset_endpoint(busid, ep_desc); + } else if (cur_alt_setting == alt_setting) { + ret = usbd_set_endpoint(busid, ep_desc); + } else { + } + } + + break; + + default: + break; + } + + /* skip to next descriptor */ + current_desc_len += p[DESC_bLength]; + p += p[DESC_bLength]; + if (current_desc_len >= desc_len && desc_len) { + break; + } + } + + usbd_class_event_notify_handler(busid, USBD_EVENT_SET_INTERFACE, (void *)if_desc); + + return ret; +} + +/** + * @brief handle a standard device request + * + * @param [in] busid busid + * @param [in] setup The setup packet + * @param [in,out] data Data buffer + * @param [in,out] len Pointer to data length + * + * @return true if the request was handled successfully + */ +static bool usbd_std_device_req_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + uint16_t value = setup->wValue; + bool ret = true; + + switch (setup->bRequest) { + case USB_REQUEST_GET_STATUS: + /* bit 0: self-powered */ + /* bit 1: remote wakeup */ + (*data)[0] = 0x00; + if (g_usbd_core[busid].self_powered) { + (*data)[0] |= USB_GETSTATUS_SELF_POWERED; + } + if (g_usbd_core[busid].remote_wakeup_enabled) { + (*data)[0] |= USB_GETSTATUS_REMOTE_WAKEUP; + } + (*data)[1] = 0x00; + *len = 2; + break; + + case USB_REQUEST_CLEAR_FEATURE: + case USB_REQUEST_SET_FEATURE: + if (value == USB_FEATURE_REMOTE_WAKEUP) { + if (setup->bRequest == USB_REQUEST_SET_FEATURE) { + g_usbd_core[busid].remote_wakeup_enabled = true; + g_usbd_core[busid].event_handler(busid, USBD_EVENT_SET_REMOTE_WAKEUP); + } else { + g_usbd_core[busid].remote_wakeup_enabled = false; + g_usbd_core[busid].event_handler(busid, USBD_EVENT_CLR_REMOTE_WAKEUP); + } + } else if (value == USB_FEATURE_TEST_MODE) { +#ifdef CONFIG_USBDEV_TEST_MODE + g_usbd_core[busid].test_req = true; +#endif + } + *len = 0; + break; + + case USB_REQUEST_SET_ADDRESS: + g_usbd_core[busid].device_address = value; + usbd_set_address(busid, value); + *len = 0; + break; + + case USB_REQUEST_GET_DESCRIPTOR: + ret = usbd_get_descriptor(busid, value, data, len); + break; + + case USB_REQUEST_SET_DESCRIPTOR: + ret = false; + break; + + case USB_REQUEST_GET_CONFIGURATION: + (*data)[0] = g_usbd_core[busid].configuration; + *len = 1; + break; + + case USB_REQUEST_SET_CONFIGURATION: + value &= 0xFF; + + if (value == 0) { + g_usbd_core[busid].configuration = 0; + } else if (!usbd_set_configuration(busid, value, 0)) { + ret = false; + } else { + g_usbd_core[busid].configuration = value; + g_usbd_core[busid].is_suspend = false; + usbd_class_event_notify_handler(busid, USBD_EVENT_CONFIGURED, NULL); + g_usbd_core[busid].event_handler(busid, USBD_EVENT_CONFIGURED); + } + *len = 0; + break; + + case USB_REQUEST_GET_INTERFACE: + case USB_REQUEST_SET_INTERFACE: + ret = false; + break; + + default: + ret = false; + break; + } + + return ret; +} + +/** + * @brief handle a standard interface request + * + * @param [in] busid busid + * @param [in] setup The setup packet + * @param [in,out] data Data buffer + * @param [in,out] len Pointer to data length + * + * @return true if the request was handled successfully + */ +static bool usbd_std_interface_req_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + uint8_t type = HI_BYTE(setup->wValue); + uint8_t intf_num = LO_BYTE(setup->wIndex); + bool ret = true; + const uint8_t *p; + uint32_t desc_len = 0; + uint32_t current_desc_len = 0; + uint8_t cur_iface = 0xFF; + +#ifdef CONFIG_USBDEV_ADVANCE_DESC + p = g_usbd_core[busid].descriptors->config_descriptor_callback(g_usbd_core[busid].speed); +#else + p = (uint8_t *)g_usbd_core[busid].descriptors; +#endif + + /* Only when device is configured, then interface requests can be valid. */ + if (!is_device_configured(busid)) { + return false; + } + + switch (setup->bRequest) { + case USB_REQUEST_GET_STATUS: + (*data)[0] = 0x00; + (*data)[1] = 0x00; + *len = 2; + break; + + case USB_REQUEST_GET_DESCRIPTOR: + if (type == 0x21) { /* HID_DESCRIPTOR_TYPE_HID */ + while (p[DESC_bLength] != 0U) { + switch (p[DESC_bDescriptorType]) { + case USB_DESCRIPTOR_TYPE_CONFIGURATION: + current_desc_len = 0; + desc_len = (p[CONF_DESC_wTotalLength]) | + (p[CONF_DESC_wTotalLength + 1] << 8); + + break; + + case USB_DESCRIPTOR_TYPE_INTERFACE: + cur_iface = p[INTF_DESC_bInterfaceNumber]; + break; + case 0x21: + if (cur_iface == intf_num) { + *data = (uint8_t *)p; + //memcpy(*data, p, p[DESC_bLength]); + *len = p[DESC_bLength]; + return true; + } + break; + default: + break; + } + + /* skip to next descriptor */ + current_desc_len += p[DESC_bLength]; + p += p[DESC_bLength]; + if (current_desc_len >= desc_len && desc_len) { + break; + } + } + } else if (type == 0x22) { /* HID_DESCRIPTOR_TYPE_HID_REPORT */ + for (uint8_t i = 0; i < g_usbd_core[busid].intf_offset; i++) { + struct usbd_interface *intf = g_usbd_core[busid].intf[i]; + + if (intf && (intf->intf_num == intf_num)) { + *data = (uint8_t *)intf->hid_report_descriptor; + //memcpy(*data, intf->hid_report_descriptor, intf->hid_report_descriptor_len); + *len = intf->hid_report_descriptor_len; + return true; + } + } + } + ret = false; + break; + case USB_REQUEST_CLEAR_FEATURE: + case USB_REQUEST_SET_FEATURE: + ret = false; + break; + case USB_REQUEST_GET_INTERFACE: + (*data)[0] = g_usbd_core[busid].intf_altsetting[intf_num]; + *len = 1; + break; + + case USB_REQUEST_SET_INTERFACE: + g_usbd_core[busid].intf_altsetting[intf_num] = LO_BYTE(setup->wValue); + usbd_set_interface(busid, setup->wIndex, setup->wValue); + *len = 0; + break; + + default: + ret = false; + break; + } + + return ret; +} + +/** + * @brief handle a standard endpoint request + * + * @param [in] busid busid + * @param [in] setup The setup packet + * @param [in,out] data Data buffer + * @param [in,out] len Pointer to data length + * + * @return true if the request was handled successfully + */ +static bool usbd_std_endpoint_req_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + uint8_t ep = (uint8_t)setup->wIndex; + bool ret = true; + uint8_t stalled; + + /* Only when device is configured, then endpoint requests can be valid. */ + if (!is_device_configured(busid)) { + return false; + } + + switch (setup->bRequest) { + case USB_REQUEST_GET_STATUS: + usbd_ep_is_stalled(busid, ep, &stalled); + if (stalled) { + (*data)[0] = 0x01; + } else { + (*data)[0] = 0x00; + } + (*data)[1] = 0x00; + *len = 2; + break; + case USB_REQUEST_CLEAR_FEATURE: + if (setup->wValue == USB_FEATURE_ENDPOINT_HALT) { + USB_LOG_ERR("ep:%02x clear halt\r\n", ep); + + usbd_ep_clear_stall(busid, ep); + break; + } else { + ret = false; + } + *len = 0; + break; + case USB_REQUEST_SET_FEATURE: + if (setup->wValue == USB_FEATURE_ENDPOINT_HALT) { + USB_LOG_ERR("ep:%02x set halt\r\n", ep); + + usbd_ep_set_stall(busid, ep); + } else { + ret = false; + } + *len = 0; + break; + + case USB_REQUEST_SYNCH_FRAME: + ret = false; + break; + default: + ret = false; + break; + } + + return ret; +} + +/** + * @brief handle standard requests (list in chapter 9) + * + * @param [in] busid busid + * @param [in] setup The setup packet + * @param [in,out] data Data buffer + * @param [in,out] len Pointer to data length + * + * @return true if the request was handled successfully + */ +static int usbd_standard_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + int rc = 0; + + switch (setup->bmRequestType & USB_REQUEST_RECIPIENT_MASK) { + case USB_REQUEST_RECIPIENT_DEVICE: + if (usbd_std_device_req_handler(busid, setup, data, len) == false) { + rc = -1; + } + + break; + + case USB_REQUEST_RECIPIENT_INTERFACE: + if (usbd_std_interface_req_handler(busid, setup, data, len) == false) { + rc = -1; + } + + break; + + case USB_REQUEST_RECIPIENT_ENDPOINT: + if (usbd_std_endpoint_req_handler(busid, setup, data, len) == false) { + rc = -1; + } + + break; + + default: + rc = -1; + break; + } + + return rc; +} + +/** + * @brief handler for class requests + * + * @param [in] busid busid + * @param [in] setup The setup packet + * @param [in,out] data Data buffer + * @param [in,out] len Pointer to data length + * + * @return true if the request was handled successfully + */ +static int usbd_class_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + if ((setup->bmRequestType & USB_REQUEST_RECIPIENT_MASK) == USB_REQUEST_RECIPIENT_INTERFACE) { + for (uint8_t i = 0; i < g_usbd_core[busid].intf_offset; i++) { + struct usbd_interface *intf = g_usbd_core[busid].intf[i]; + + if (intf && intf->class_interface_handler && (intf->intf_num == (setup->wIndex & 0xFF))) { + return intf->class_interface_handler(busid, setup, data, len); + } + } + } else if ((setup->bmRequestType & USB_REQUEST_RECIPIENT_MASK) == USB_REQUEST_RECIPIENT_ENDPOINT) { + for (uint8_t i = 0; i < g_usbd_core[busid].intf_offset; i++) { + struct usbd_interface *intf = g_usbd_core[busid].intf[i]; + + if (intf && intf->class_endpoint_handler) { + return intf->class_endpoint_handler(busid, setup, data, len); + } + } + } + return -1; +} + +/** + * @brief handler for vendor requests + * + * @param [in] busid busid + * @param [in] setup The setup packet + * @param [in,out] data Data buffer + * @param [in,out] len Pointer to data length + * + * @return true if the request was handled successfully + */ +static int usbd_vendor_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + uint32_t desclen; +#ifdef CONFIG_USBDEV_ADVANCE_DESC + if (g_usbd_core[busid].descriptors->msosv1_descriptor) { + if (setup->bRequest == g_usbd_core[busid].descriptors->msosv1_descriptor->vendor_code) { + switch (setup->wIndex) { + case 0x04: + desclen = g_usbd_core[busid].descriptors->msosv1_descriptor->compat_id[0] + + (g_usbd_core[busid].descriptors->msosv1_descriptor->compat_id[1] << 8) + + (g_usbd_core[busid].descriptors->msosv1_descriptor->compat_id[2] << 16) + + (g_usbd_core[busid].descriptors->msosv1_descriptor->compat_id[3] << 24); + + *data = (uint8_t *)g_usbd_core[busid].descriptors->msosv1_descriptor->compat_id; + //memcpy(*data, g_usbd_core[busid].descriptors->msosv1_descriptor->compat_id, desclen); + *len = desclen; + return 0; + case 0x05: + desclen = g_usbd_core[busid].descriptors->msosv1_descriptor->comp_id_property[setup->wValue][0] + + (g_usbd_core[busid].descriptors->msosv1_descriptor->comp_id_property[setup->wValue][1] << 8) + + (g_usbd_core[busid].descriptors->msosv1_descriptor->comp_id_property[setup->wValue][2] << 16) + + (g_usbd_core[busid].descriptors->msosv1_descriptor->comp_id_property[setup->wValue][3] << 24); + + *data = (uint8_t *)g_usbd_core[busid].descriptors->msosv1_descriptor->comp_id_property[setup->wValue]; + //memcpy(*data, g_usbd_core[busid].descriptors->msosv1_descriptor->comp_id_property[setup->wValue], desclen); + *len = desclen; + return 0; + default: + USB_LOG_ERR("unknown vendor code\r\n"); + return -1; + } + } + } else if (g_usbd_core[busid].descriptors->msosv2_descriptor) { + if (setup->bRequest == g_usbd_core[busid].descriptors->msosv2_descriptor->vendor_code) { + switch (setup->wIndex) { + case WINUSB_REQUEST_GET_DESCRIPTOR_SET: + desclen = g_usbd_core[busid].descriptors->msosv2_descriptor->compat_id_len; + *data = (uint8_t *)g_usbd_core[busid].descriptors->msosv2_descriptor->compat_id; + //memcpy(*data, g_usbd_core[busid].descriptors->msosv2_descriptor->compat_id, desclen); + *len = g_usbd_core[busid].descriptors->msosv2_descriptor->compat_id_len; + return 0; + default: + USB_LOG_ERR("unknown vendor code\r\n"); + return -1; + } + } + } + + if (g_usbd_core[busid].descriptors->webusb_url_descriptor) { + if (setup->bRequest == g_usbd_core[busid].descriptors->webusb_url_descriptor->vendor_code) { + switch (setup->wIndex) { + case WEBUSB_REQUEST_GET_URL: + desclen = g_usbd_core[busid].descriptors->webusb_url_descriptor->string_len; + *data = (uint8_t *)g_usbd_core[busid].descriptors->webusb_url_descriptor->string; + //memcpy(*data, g_usbd_core[busid].descriptors->webusb_url_descriptor->string, desclen); + *len = desclen; + return 0; + default: + USB_LOG_ERR("unknown vendor code\r\n"); + return -1; + } + } + } +#else + if (g_usbd_core[busid].msosv1_desc) { + if (setup->bRequest == g_usbd_core[busid].msosv1_desc->vendor_code) { + switch (setup->wIndex) { + case 0x04: + *data = (uint8_t *)g_usbd_core[busid].msosv1_desc->compat_id; + desclen = g_usbd_core[busid].msosv1_desc->compat_id[0] + + (g_usbd_core[busid].msosv1_desc->compat_id[1] << 8) + + (g_usbd_core[busid].msosv1_desc->compat_id[2] << 16) + + (g_usbd_core[busid].msosv1_desc->compat_id[3] << 24); + //memcpy(*data, g_usbd_core[busid].msosv1_desc->compat_id, desclen); + *len = desclen; + return 0; + case 0x05: + *data = (uint8_t *)g_usbd_core[busid].msosv1_desc->comp_id_property[setup->wValue]; + desclen = g_usbd_core[busid].msosv1_desc->comp_id_property[setup->wValue][0] + + (g_usbd_core[busid].msosv1_desc->comp_id_property[setup->wValue][1] << 8) + + (g_usbd_core[busid].msosv1_desc->comp_id_property[setup->wValue][2] << 16) + + (g_usbd_core[busid].msosv1_desc->comp_id_property[setup->wValue][3] << 24); + //memcpy(*data, g_usbd_core[busid].msosv1_desc->comp_id_property[setup->wValue], desclen); + *len = desclen; + return 0; + default: + USB_LOG_ERR("unknown vendor code\r\n"); + return -1; + } + } + } else if (g_usbd_core[busid].msosv2_desc) { + if (setup->bRequest == g_usbd_core[busid].msosv2_desc->vendor_code) { + switch (setup->wIndex) { + case WINUSB_REQUEST_GET_DESCRIPTOR_SET: + *data = (uint8_t *)g_usbd_core[busid].msosv2_desc->compat_id; + //memcpy(*data, g_usbd_core[busid].msosv2_desc->compat_id, g_usbd_core[busid].msosv2_desc->compat_id_len); + *len = g_usbd_core[busid].msosv2_desc->compat_id_len; + return 0; + default: + USB_LOG_ERR("unknown vendor code\r\n"); + return -1; + } + } + } + + if (g_usbd_core[busid].webusb_url_desc) { + if (setup->bRequest == g_usbd_core[busid].webusb_url_desc->vendor_code) { + switch (setup->wIndex) { + case WEBUSB_REQUEST_GET_URL: + desclen = g_usbd_core[busid].webusb_url_desc->string_len; + *data = (uint8_t *)g_usbd_core[busid].webusb_url_desc->string; + //memcpy(*data, g_usbd_core[busid].webusb_url_desc->string, desclen); + *len = desclen; + return 0; + default: + USB_LOG_ERR("unknown vendor code\r\n"); + return -1; + } + } + } +#endif + for (uint8_t i = 0; i < g_usbd_core[busid].intf_offset; i++) { + struct usbd_interface *intf = g_usbd_core[busid].intf[i]; + + if (intf && intf->vendor_handler && (intf->vendor_handler(busid, setup, data, len) == 0)) { + return 0; + } + } + + return -1; +} + +/** + * @brief handle setup request( standard/class/vendor/other) + * + * @param [in] busid busid + * @param [in] setup The setup packet + * @param [in,out] data Data buffer + * @param [in,out] len Pointer to data length + * + * @return true if the request was handles successfully + */ +static bool usbd_setup_request_handler(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len) +{ + switch (setup->bmRequestType & USB_REQUEST_TYPE_MASK) { + case USB_REQUEST_STANDARD: + if (usbd_standard_request_handler(busid, setup, data, len) < 0) { + /* Ignore error log for getting Device Qualifier Descriptor request */ + if ((setup->bRequest == 0x06) && (setup->wValue == 0x0600)) { + //USB_LOG_DBG("Ignore DQD in fs\r\n"); + return false; + } + USB_LOG_ERR("standard request error\r\n"); + usbd_print_setup(setup); + return false; + } + break; + case USB_REQUEST_CLASS: + if (usbd_class_request_handler(busid, setup, data, len) < 0) { + USB_LOG_ERR("class request error\r\n"); + usbd_print_setup(setup); + return false; + } + break; + case USB_REQUEST_VENDOR: + if (usbd_vendor_request_handler(busid, setup, data, len) < 0) { + USB_LOG_ERR("vendor request error\r\n"); + usbd_print_setup(setup); + return false; + } + break; + + default: + return false; + } + + return true; +} + +static void usbd_class_event_notify_handler(uint8_t busid, uint8_t event, void *arg) +{ + for (uint8_t i = 0; i < g_usbd_core[busid].intf_offset; i++) { + struct usbd_interface *intf = g_usbd_core[busid].intf[i]; + + if (arg) { + struct usb_interface_descriptor *desc = (struct usb_interface_descriptor *)arg; + if (intf && intf->notify_handler && (desc->bInterfaceNumber == (intf->intf_num))) { + intf->notify_handler(busid, event, arg); + } + } else { + if (intf && intf->notify_handler) { + intf->notify_handler(busid, event, arg); + } + } + } +} + +void usbd_event_connect_handler(uint8_t busid) +{ + g_usbd_core[busid].event_handler(busid, USBD_EVENT_CONNECTED); +} + +void usbd_event_disconnect_handler(uint8_t busid) +{ + g_usbd_core[busid].event_handler(busid, USBD_EVENT_DISCONNECTED); +} + +void usbd_event_resume_handler(uint8_t busid) +{ + g_usbd_core[busid].is_suspend = false; + g_usbd_core[busid].event_handler(busid, USBD_EVENT_RESUME); +} + +void usbd_event_suspend_handler(uint8_t busid) +{ + if (g_usbd_core[busid].device_address > 0) { + g_usbd_core[busid].is_suspend = true; + g_usbd_core[busid].event_handler(busid, USBD_EVENT_SUSPEND); + } +} + +void usbd_event_reset_handler(uint8_t busid) +{ + usbd_set_address(busid, 0); + g_usbd_core[busid].device_address = 0; + g_usbd_core[busid].configuration = 0; +#ifdef CONFIG_USBDEV_ADVANCE_DESC + g_usbd_core[busid].speed = USB_SPEED_UNKNOWN; +#endif + struct usb_endpoint_descriptor ep0; + + ep0.bLength = 7; + ep0.bDescriptorType = USB_DESCRIPTOR_TYPE_ENDPOINT; + ep0.wMaxPacketSize = USB_CTRL_EP_MPS; + ep0.bmAttributes = USB_ENDPOINT_TYPE_CONTROL; + ep0.bEndpointAddress = USB_CONTROL_IN_EP0; + ep0.bInterval = 0; + usbd_ep_open(busid, &ep0); + + ep0.bEndpointAddress = USB_CONTROL_OUT_EP0; + usbd_ep_open(busid, &ep0); + + usbd_class_event_notify_handler(busid, USBD_EVENT_RESET, NULL); + g_usbd_core[busid].event_handler(busid, USBD_EVENT_RESET); +} + +static void __usbd_event_ep0_setup_complete_handler(uint8_t busid, struct usb_setup_packet *setup) +{ + uint8_t *buf; + +#ifdef CONFIG_USBDEV_SETUP_LOG_PRINT + usbd_print_setup(setup); +#endif + if (setup->wLength > CONFIG_USBDEV_REQUEST_BUFFER_LEN) { + if ((setup->bmRequestType & USB_REQUEST_DIR_MASK) == USB_REQUEST_DIR_OUT) { + USB_LOG_ERR("Request buffer too small\r\n"); + usbd_ep_set_stall(busid, USB_CONTROL_IN_EP0); + return; + } + } + + g_usbd_core[busid].ep0_data_buf = g_usbd_core[busid].req_data; + g_usbd_core[busid].ep0_data_buf_residue = setup->wLength; + g_usbd_core[busid].ep0_data_buf_len = setup->wLength; + g_usbd_core[busid].zlp_flag = false; + buf = g_usbd_core[busid].ep0_data_buf; + + /* handle class request when all the data is received */ + if (setup->wLength && ((setup->bmRequestType & USB_REQUEST_DIR_MASK) == USB_REQUEST_DIR_OUT)) { + USB_LOG_DBG("Start reading %d bytes from ep0\r\n", setup->wLength); + usbd_ep_start_read(busid, USB_CONTROL_OUT_EP0, g_usbd_core[busid].ep0_data_buf, setup->wLength); + return; + } + + /* Ask installed handler to process request */ + if (!usbd_setup_request_handler(busid, setup, &buf, &g_usbd_core[busid].ep0_data_buf_len)) { + usbd_ep_set_stall(busid, USB_CONTROL_IN_EP0); + return; + } + + /* Send smallest of requested and offered length */ + g_usbd_core[busid].ep0_data_buf_residue = MIN(g_usbd_core[busid].ep0_data_buf_len, setup->wLength); + if (g_usbd_core[busid].ep0_data_buf_residue > CONFIG_USBDEV_REQUEST_BUFFER_LEN) { + USB_LOG_ERR("Request buffer too small\r\n"); + usbd_ep_set_stall(busid, USB_CONTROL_IN_EP0); + return; + } + + /* use *data = xxx; g_usbd_core[busid].ep0_data_buf records real data address, we should copy data into ep0 buffer. + * Why we should copy once? because some chips are not access to flash with dma if real data address is in flash address(such as ch32). + */ + if (buf != g_usbd_core[busid].ep0_data_buf) { +#ifdef CONFIG_USBDEV_EP0_INDATA_NO_COPY + g_usbd_core[busid].ep0_data_buf = buf; +#else + usb_memcpy(g_usbd_core[busid].ep0_data_buf, buf, g_usbd_core[busid].ep0_data_buf_residue); +#endif + } else { + /* use memcpy(*data, xxx, len); has copied into ep0 buffer, we do nothing */ + } + + /* Send data or status to host */ + usbd_ep_start_write(busid, USB_CONTROL_IN_EP0, g_usbd_core[busid].ep0_data_buf, g_usbd_core[busid].ep0_data_buf_residue); + /* + * Set ZLP flag when host asks for a bigger length and the data size is + * multiplier of USB_CTRL_EP_MPS, to indicate the transfer done after zlp + * sent. + */ + if ((setup->wLength > g_usbd_core[busid].ep0_data_buf_len) && (!(g_usbd_core[busid].ep0_data_buf_len % USB_CTRL_EP_MPS))) { + g_usbd_core[busid].zlp_flag = true; + USB_LOG_DBG("EP0 Set zlp\r\n"); + } +} + +void usbd_event_ep0_setup_complete_handler(uint8_t busid, uint8_t *psetup) +{ + struct usb_setup_packet *setup = &g_usbd_core[busid].setup; + + memcpy(setup, psetup, 8); + +#ifdef CONFIG_USBDEV_EP0_THREAD + usb_osal_mq_send(g_usbd_core[busid].usbd_ep0_mq, USB_EP0_STATE_SETUP); +#else + __usbd_event_ep0_setup_complete_handler(busid, setup); +#endif +} + +static void usbd_event_ep0_in_complete_handler(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + struct usb_setup_packet *setup = &g_usbd_core[busid].setup; + + (void)ep; + + g_usbd_core[busid].ep0_data_buf += nbytes; + g_usbd_core[busid].ep0_data_buf_residue -= nbytes; + + USB_LOG_DBG("EP0 send %d bytes, %d remained\r\n", nbytes, g_usbd_core[busid].ep0_data_buf_residue); + + if (g_usbd_core[busid].ep0_data_buf_residue != 0) { + /* Start sending the remain data */ + usbd_ep_start_write(busid, USB_CONTROL_IN_EP0, g_usbd_core[busid].ep0_data_buf, g_usbd_core[busid].ep0_data_buf_residue); + } else { + if (g_usbd_core[busid].zlp_flag == true) { + g_usbd_core[busid].zlp_flag = false; + /* Send zlp to host */ + USB_LOG_DBG("EP0 Send zlp\r\n"); + usbd_ep_start_write(busid, USB_CONTROL_IN_EP0, NULL, 0); + } else { + /* Satisfying three conditions will jump here. + * 1. send status completely + * 2. send zlp completely + * 3. send last data completely. + */ + if (setup->wLength && ((setup->bmRequestType & USB_REQUEST_DIR_MASK) == USB_REQUEST_DIR_IN)) { + /* if all data has sent completely, start reading out status */ + usbd_ep_start_read(busid, USB_CONTROL_OUT_EP0, NULL, 0); + } + +#ifdef CONFIG_USBDEV_TEST_MODE + if (g_usbd_core[busid].test_req) { + usbd_execute_test_mode(busid, HI_BYTE(setup->wIndex)); + g_usbd_core[busid].test_req = false; + } +#endif + } + } +} + +static void usbd_event_ep0_out_complete_handler(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + struct usb_setup_packet *setup = &g_usbd_core[busid].setup; + + (void)ep; + (void)setup; + + if (nbytes > 0) { + g_usbd_core[busid].ep0_data_buf += nbytes; + g_usbd_core[busid].ep0_data_buf_residue -= nbytes; + + USB_LOG_DBG("EP0 recv %d bytes, %d remained\r\n", nbytes, g_usbd_core[busid].ep0_data_buf_residue); + + if (g_usbd_core[busid].ep0_data_buf_residue == 0) { +#ifdef CONFIG_USBDEV_EP0_THREAD + usb_osal_mq_send(g_usbd_core[busid].usbd_ep0_mq, USB_EP0_STATE_OUT); +#else + /* Received all, send data to handler */ + g_usbd_core[busid].ep0_data_buf = g_usbd_core[busid].req_data; + if (!usbd_setup_request_handler(busid, setup, &g_usbd_core[busid].ep0_data_buf, &g_usbd_core[busid].ep0_data_buf_len)) { + usbd_ep_set_stall(busid, USB_CONTROL_IN_EP0); + return; + } + + /*Send status to host*/ + usbd_ep_start_write(busid, USB_CONTROL_IN_EP0, NULL, 0); +#endif + } else { + /* Start reading the remain data */ + usbd_ep_start_read(busid, USB_CONTROL_OUT_EP0, g_usbd_core[busid].ep0_data_buf, g_usbd_core[busid].ep0_data_buf_residue); + } + } else { + /* Read out status completely, do nothing */ + USB_LOG_DBG("EP0 recv out status\r\n"); + } +} + +void usbd_event_ep_in_complete_handler(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + if (g_usbd_core[busid].tx_msg[ep & 0x7f].cb) { + g_usbd_core[busid].tx_msg[ep & 0x7f].cb(busid, ep, nbytes); + } +} + +void usbd_event_ep_out_complete_handler(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + if (g_usbd_core[busid].rx_msg[ep & 0x7f].cb) { + g_usbd_core[busid].rx_msg[ep & 0x7f].cb(busid, ep, nbytes); + } +} + +#ifdef CONFIG_USBDEV_ADVANCE_DESC +void usbd_desc_register(uint8_t busid, const struct usb_descriptor *desc) +{ + memset(&g_usbd_core[busid], 0, sizeof(struct usbd_core_priv)); + + g_usbd_core[busid].descriptors = desc; + g_usbd_core[busid].intf_offset = 0; + + g_usbd_core[busid].tx_msg[0].ep = 0x80; + g_usbd_core[busid].tx_msg[0].cb = usbd_event_ep0_in_complete_handler; + g_usbd_core[busid].rx_msg[0].ep = 0x00; + g_usbd_core[busid].rx_msg[0].cb = usbd_event_ep0_out_complete_handler; +} +#else +void usbd_desc_register(uint8_t busid, const uint8_t *desc) +{ + memset(&g_usbd_core[busid], 0, sizeof(struct usbd_core_priv)); + + g_usbd_core[busid].descriptors = desc; + g_usbd_core[busid].intf_offset = 0; + + g_usbd_core[busid].tx_msg[0].ep = 0x80; + g_usbd_core[busid].tx_msg[0].cb = usbd_event_ep0_in_complete_handler; + g_usbd_core[busid].rx_msg[0].ep = 0x00; + g_usbd_core[busid].rx_msg[0].cb = usbd_event_ep0_out_complete_handler; +} + +/* Register MS OS Descriptors version 1 */ +void usbd_msosv1_desc_register(uint8_t busid, struct usb_msosv1_descriptor *desc) +{ + g_usbd_core[busid].msosv1_desc = desc; +} + +/* Register MS OS Descriptors version 2 */ +void usbd_msosv2_desc_register(uint8_t busid, struct usb_msosv2_descriptor *desc) +{ + g_usbd_core[busid].msosv2_desc = desc; +} + +void usbd_bos_desc_register(uint8_t busid, struct usb_bos_descriptor *desc) +{ + g_usbd_core[busid].bos_desc = desc; +} + +void usbd_webusb_desc_register(uint8_t busid, struct usb_webusb_descriptor *desc) +{ + g_usbd_core[busid].webusb_url_desc = desc; +} +#endif + +void usbd_add_interface(uint8_t busid, struct usbd_interface *intf) +{ + intf->intf_num = g_usbd_core[busid].intf_offset; + g_usbd_core[busid].intf[g_usbd_core[busid].intf_offset] = intf; + g_usbd_core[busid].intf_offset++; +} + +void usbd_add_endpoint(uint8_t busid, struct usbd_endpoint *ep) +{ + if (ep->ep_addr & 0x80) { + g_usbd_core[busid].tx_msg[ep->ep_addr & 0x7f].ep = ep->ep_addr; + g_usbd_core[busid].tx_msg[ep->ep_addr & 0x7f].cb = ep->ep_cb; + } else { + g_usbd_core[busid].rx_msg[ep->ep_addr & 0x7f].ep = ep->ep_addr; + g_usbd_core[busid].rx_msg[ep->ep_addr & 0x7f].cb = ep->ep_cb; + } +} + +uint16_t usbd_get_ep_mps(uint8_t busid, uint8_t ep) +{ + if (ep & 0x80) { + return g_usbd_core[busid].tx_msg[ep & 0x7f].ep_mps; + } else { + return g_usbd_core[busid].rx_msg[ep & 0x7f].ep_mps; + } +} + +uint8_t usbd_get_ep_mult(uint8_t busid, uint8_t ep) +{ + if (ep & 0x80) { + return g_usbd_core[busid].tx_msg[ep & 0x7f].ep_mult; + } else { + return g_usbd_core[busid].rx_msg[ep & 0x7f].ep_mult; + } +} + +bool usb_device_is_configured(uint8_t busid) +{ + return g_usbd_core[busid].configuration; +} + +bool usb_device_is_suspend(uint8_t busid) +{ + return g_usbd_core[busid].is_suspend; +} + +int usbd_send_remote_wakeup(uint8_t busid) +{ + if (g_usbd_core[busid].remote_wakeup_support && g_usbd_core[busid].remote_wakeup_enabled && g_usbd_core[busid].is_suspend) { + return usbd_set_remote_wakeup(busid); + } else { + if (!g_usbd_core[busid].remote_wakeup_support) { + USB_LOG_ERR("device does not support remote wakeup\r\n"); + } + if (!g_usbd_core[busid].remote_wakeup_enabled) { + USB_LOG_ERR("device remote wakeup is not enabled\r\n"); + } + if (!g_usbd_core[busid].is_suspend) { + USB_LOG_ERR("device is not in suspend state\r\n"); + } + return -1; + } +} + +#ifdef CONFIG_USBDEV_EP0_THREAD +static void usbdev_ep0_thread(CONFIG_USB_OSAL_THREAD_SET_ARGV) +{ + uintptr_t event; + int ret; + uint8_t busid = (uint8_t)CONFIG_USB_OSAL_THREAD_GET_ARGV; + struct usb_setup_packet *setup = &g_usbd_core[busid].setup; + + while (1) { + ret = usb_osal_mq_recv(g_usbd_core[busid].usbd_ep0_mq, (uintptr_t *)&event, USB_OSAL_WAITING_FOREVER); + if (ret < 0) { + continue; + } + USB_LOG_DBG("event:%d\r\n", event); + + switch (event) { + case USB_EP0_STATE_SETUP: + __usbd_event_ep0_setup_complete_handler(busid, setup); + break; + case USB_EP0_STATE_IN: + // do nothing + break; + case USB_EP0_STATE_OUT: + /* Received all, send data to handler */ + g_usbd_core[busid].ep0_data_buf = g_usbd_core[busid].req_data; + if (!usbd_setup_request_handler(busid, setup, &g_usbd_core[busid].ep0_data_buf, &g_usbd_core[busid].ep0_data_buf_len)) { + usbd_ep_set_stall(busid, USB_CONTROL_IN_EP0); + continue; + } + + /*Send status to host*/ + usbd_ep_start_write(busid, USB_CONTROL_IN_EP0, NULL, 0); + break; + + default: + break; + } + } +} +#endif + +int usbd_initialize(uint8_t busid, uintptr_t reg_base, void (*event_handler)(uint8_t busid, uint8_t event)) +{ + int ret; + struct usbd_bus *bus; + + if (busid >= CONFIG_USBDEV_MAX_BUS) { + USB_LOG_ERR("bus overflow\r\n"); + while (1) { + } + } + + bus = &g_usbdev_bus[busid]; + bus->reg_base = reg_base; + +#ifdef CONFIG_USBDEV_EP0_THREAD + g_usbd_core[busid].usbd_ep0_mq = usb_osal_mq_create(1); + if (g_usbd_core[busid].usbd_ep0_mq == NULL) { + USB_LOG_ERR("No memory to alloc for g_usbd_core[busid].usbd_ep0_mq\r\n"); + while (1) { + } + } + g_usbd_core[busid].usbd_ep0_thread = usb_osal_thread_create("usbd_ep0", CONFIG_USBDEV_EP0_STACKSIZE, CONFIG_USBDEV_EP0_PRIO, usbdev_ep0_thread, (void *)(uint32_t)busid); + if (g_usbd_core[busid].usbd_ep0_thread == NULL) { + USB_LOG_ERR("No memory to alloc for g_usbd_core[busid].usbd_ep0_thread\r\n"); + while (1) { + } + } +#endif + + g_usbd_core[busid].event_handler = event_handler; + ret = usb_dc_init(busid); + usbd_class_event_notify_handler(busid, USBD_EVENT_INIT, NULL); + g_usbd_core[busid].event_handler(busid, USBD_EVENT_INIT); + return ret; +} + +int usbd_deinitialize(uint8_t busid) +{ + if (busid >= CONFIG_USBDEV_MAX_BUS) { + USB_LOG_ERR("bus overflow\r\n"); + while (1) { + } + } + + g_usbd_core[busid].event_handler(busid, USBD_EVENT_DEINIT); + usbd_class_event_notify_handler(busid, USBD_EVENT_DEINIT, NULL); + usb_dc_deinit(busid); + g_usbd_core[busid].intf_offset = 0; +#ifdef CONFIG_USBDEV_EP0_THREAD + if (g_usbd_core[busid].usbd_ep0_mq) { + usb_osal_mq_delete(g_usbd_core[busid].usbd_ep0_mq); + } + if (g_usbd_core[busid].usbd_ep0_thread) { + usb_osal_thread_delete(g_usbd_core[busid].usbd_ep0_thread); + } +#endif + + return 0; +} diff --git a/ch32v103_hallarray_controller/3rdparty/CherryUSB/core/usbd_core.h b/ch32v103_hallarray_controller/3rdparty/CherryUSB/core/usbd_core.h new file mode 100644 index 0000000..71bdb29 --- /dev/null +++ b/ch32v103_hallarray_controller/3rdparty/CherryUSB/core/usbd_core.h @@ -0,0 +1,116 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef USBD_CORE_H +#define USBD_CORE_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include +#include +#include +#include + +#include "usb_config.h" +#include "usb_util.h" +#include "usb_errno.h" +#include "usb_def.h" +#include "usb_list.h" +#include "usb_log.h" +#include "usb_dc.h" +#include "usb_memcpy.h" +#include "usb_version.h" + +enum usbd_event_type { + /* USB DCD IRQ */ + USBD_EVENT_ERROR, /** USB error reported by the controller */ + USBD_EVENT_RESET, /** USB reset */ + USBD_EVENT_SOF, /** Start of Frame received */ + USBD_EVENT_CONNECTED, /** USB connected*/ + USBD_EVENT_DISCONNECTED, /** USB disconnected */ + USBD_EVENT_SUSPEND, /** USB connection suspended by the HOST */ + USBD_EVENT_RESUME, /** USB connection resumed by the HOST */ + + /* USB DEVICE STATUS */ + USBD_EVENT_CONFIGURED, /** USB configuration done */ + USBD_EVENT_SET_INTERFACE, /** USB interface selected */ + USBD_EVENT_SET_REMOTE_WAKEUP, /** USB set remote wakeup */ + USBD_EVENT_CLR_REMOTE_WAKEUP, /** USB clear remote wakeup */ + USBD_EVENT_INIT, /** USB init done when call usbd_initialize */ + USBD_EVENT_DEINIT, /** USB deinit done when call usbd_deinitialize */ + USBD_EVENT_UNKNOWN +}; + +typedef int (*usbd_request_handler)(uint8_t busid, struct usb_setup_packet *setup, uint8_t **data, uint32_t *len); +typedef void (*usbd_endpoint_callback)(uint8_t busid, uint8_t ep, uint32_t nbytes); +typedef void (*usbd_notify_handler)(uint8_t busid, uint8_t event, void *arg); + +struct usbd_endpoint { + uint8_t ep_addr; + usbd_endpoint_callback ep_cb; +}; + +struct usbd_interface { + usbd_request_handler class_interface_handler; + usbd_request_handler class_endpoint_handler; + usbd_request_handler vendor_handler; + usbd_notify_handler notify_handler; + const uint8_t *hid_report_descriptor; + uint32_t hid_report_descriptor_len; + uint8_t intf_num; +}; + +struct usb_descriptor { + const uint8_t *(*device_descriptor_callback)(uint8_t speed); + const uint8_t *(*config_descriptor_callback)(uint8_t speed); + const uint8_t *(*device_quality_descriptor_callback)(uint8_t speed); + const uint8_t *(*other_speed_descriptor_callback)(uint8_t speed); + const char *(*string_descriptor_callback)(uint8_t speed, uint8_t index); + const struct usb_msosv1_descriptor *msosv1_descriptor; + const struct usb_msosv2_descriptor *msosv2_descriptor; + const struct usb_webusb_descriptor *webusb_url_descriptor; + const struct usb_bos_descriptor *bos_descriptor; +}; + +struct usbd_bus { + uint8_t busid; + uintptr_t reg_base; +}; + +extern struct usbd_bus g_usbdev_bus[]; + +#ifdef USBD_IRQHandler +#error USBD_IRQHandler is obsolete, please call USBD_IRQHandler(xxx) in your irq +#endif + +#ifdef CONFIG_USBDEV_ADVANCE_DESC +void usbd_desc_register(uint8_t busid, const struct usb_descriptor *desc); +#else +void usbd_desc_register(uint8_t busid, const uint8_t *desc); +void usbd_msosv1_desc_register(uint8_t busid, struct usb_msosv1_descriptor *desc); +void usbd_msosv2_desc_register(uint8_t busid, struct usb_msosv2_descriptor *desc); +void usbd_bos_desc_register(uint8_t busid, struct usb_bos_descriptor *desc); +void usbd_webusb_desc_register(uint8_t busid, struct usb_webusb_descriptor *desc); +#endif + +void usbd_add_interface(uint8_t busid, struct usbd_interface *intf); +void usbd_add_endpoint(uint8_t busid, struct usbd_endpoint *ep); + +uint16_t usbd_get_ep_mps(uint8_t busid, uint8_t ep); +uint8_t usbd_get_ep_mult(uint8_t busid, uint8_t ep); +bool usb_device_is_configured(uint8_t busid); +bool usb_device_is_suspend(uint8_t busid); +int usbd_send_remote_wakeup(uint8_t busid); + +int usbd_initialize(uint8_t busid, uintptr_t reg_base, void (*event_handler)(uint8_t busid, uint8_t event)); +int usbd_deinitialize(uint8_t busid); + +#ifdef __cplusplus +} +#endif + +#endif /* USBD_CORE_H */ diff --git a/ch32v103_hallarray_controller/3rdparty/CherryUSB/port/ch32v103/usb_ch32v1_usbfs_reg.h b/ch32v103_hallarray_controller/3rdparty/CherryUSB/port/ch32v103/usb_ch32v1_usbfs_reg.h new file mode 100644 index 0000000..0477c9e --- /dev/null +++ b/ch32v103_hallarray_controller/3rdparty/CherryUSB/port/ch32v103/usb_ch32v1_usbfs_reg.h @@ -0,0 +1,246 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#ifndef _USB_CH32_USBFS_REG_H +#define _USB_CH32_USBFS_REG_H + +#define __IO volatile /* defines 'read / write' permissions */ + +/* USBOTG_FS Registers */ +typedef struct +{ + __IO uint8_t BASE_CTRL; //0x40023400 + __IO uint8_t UDEV_CTRL; //0x40023401 + __IO uint8_t INT_EN; //0x40023402 + __IO uint8_t DEV_ADDR; //0x40023403 + __IO uint8_t __reserved0; //0x40023404 + __IO uint8_t MIS_ST; //0x40023405 + __IO uint8_t INT_FG; //0x40023406 + __IO uint8_t INT_ST; //0x40023407 + __IO uint16_t RX_LEN; //0x40023408 + __IO uint16_t __reserved1; //0x4002340A + __IO uint8_t UEP4_1_MOD; //0x4002340C + __IO uint8_t UEP2_3_MOD; //0x4002340D + __IO uint8_t UEP5_6_MOD; //0x4002340E + __IO uint8_t UEP7_MOD; //0x4002340F + __IO uint32_t UEP0_DMA; //0x40023410 + __IO uint32_t UEP1_DMA; //0x40023414 + __IO uint32_t UEP2_DMA; //0x40023418 + __IO uint32_t UEP3_DMA; //0x4002341C + __IO uint32_t UEP4_DMA; //0x40023420 + __IO uint32_t UEP5_DMA; //0x40023424 + __IO uint32_t UEP6_DMA; //0x40023428 + __IO uint32_t UEP7_DMA; //0x4002342C + __IO uint16_t UEP0_TX_LEN; //0x40023430 + __IO uint8_t UEP0_CTRL; //0x40023432 + __IO uint8_t __reserved2; + __IO uint16_t UEP1_TX_LEN; //0x40023434 + __IO uint8_t UEP1_CTRL; //0x40023436 + __IO uint8_t __reserved3; + __IO uint16_t UEP2_TX_LEN; //0x40023438 + __IO uint8_t UEP2_CTRL; //0x4002343A + __IO uint8_t __reserved4; + __IO uint16_t UEP3_TX_LEN; //0x4002343C + __IO uint8_t UEP3_CTRL; //0x4002343E + __IO uint8_t __reserved5; + __IO uint16_t UEP4_TX_LEN; //0x40023440 + __IO uint8_t UEP4_CTRL; //0x40023442 + __IO uint8_t __reserved6; + __IO uint16_t UEP5_TX_LEN; //0x40023444 + __IO uint8_t UEP5_CTRL; //0x40023446 + __IO uint8_t __reserved7; + __IO uint16_t UEP6_TX_LEN; //0x40023448 + __IO uint8_t UEP6_CTRL; //0x4002344a + __IO uint8_t __reserved8; + __IO uint16_t UEP7_TX_LEN; //0x4002344C + __IO uint8_t UEP7_CTRL; //0x4002344E + __IO uint8_t __reserved9; +} USB_FS_TypeDef; + +#define USBFS_DEVICE ((USB_FS_TypeDef *)(uint32_t)0x40023400) + +/******************* GLOBAL ******************/ + +/* BASE USB_CTRL */ +#define USBFS_BASE_CTRL_OFFSET 0x00 // USB base control +#define USBFS_UC_HOST_MODE 0x80 // enable USB host mode: 0=device mode, 1=host mode +#define USBFS_UC_LOW_SPEED 0x40 // enable USB low speed: 0=12Mbps, 1=1.5Mbps +#define USBFS_UC_DEV_PU_EN 0x20 // USB device enable and internal pullup resistance enable +#define USBFS_UC_SYS_CTRL1 0x20 // USB system control high bit +#define USBFS_UC_SYS_CTRL0 0x10 // USB system control low bit +#define USBFS_UC_SYS_CTRL_MASK 0x30 // bit mask of USB system control +// UC_HOST_MODE & UC_SYS_CTRL1 & UC_SYS_CTRL0: USB system control +// 0 00: disable USB device and disable internal pullup resistance +// 0 01: enable USB device and disable internal pullup resistance, need external pullup resistance +// 0 1x: enable USB device and enable internal pullup resistance +// 1 00: enable USB host and normal status +// 1 01: enable USB host and force UDP/UDM output SE0 state +// 1 10: enable USB host and force UDP/UDM output J state +// 1 11: enable USB host and force UDP/UDM output resume or K state +#define USBFS_UC_INT_BUSY 0x08 // enable automatic responding busy for device mode or automatic pause for host mode during interrupt flag UIF_TRANSFER valid +#define USBFS_UC_RESET_SIE 0x04 // force reset USB SIE, need software clear +#define USBFS_UC_CLR_ALL 0x02 // force clear FIFO and count of USB +#define USBFS_UC_DMA_EN 0x01 // DMA enable and DMA interrupt enable for USB + +/* USB INT EN */ +#define USBFS_INT_EN_OFFSET 0x02 +#define USBFS_UIE_DEV_SOF 0x80 // enable interrupt for SOF received for USB device mode +#define USBFS_UIE_DEV_NAK 0x40 // enable interrupt for NAK responded for USB device mode +#define USBFS_UIE_FIFO_OV 0x10 // enable interrupt for FIFO overflow +#define USBFS_UIE_HST_SOF 0x08 // enable interrupt for host SOF timer action for USB host mode +#define USBFS_UIE_SUSPEND 0x04 // enable interrupt for USB suspend or resume event +#define USBFS_UIE_TRANSFER 0x02 // enable interrupt for USB transfer completion +#define USBFS_UIE_DETECT 0x01 // enable interrupt for USB device detected event for USB host mode +#define USBFS_UIE_BUS_RST 0x01 // enable interrupt for USB bus reset event for USB device mode +/* USB_DEV_ADDR */ +#define USBFS_DEV_ADDR_OFFSET 0x03 +#define USBFS_UDA_GP_BIT 0x80 // general purpose bit +#define USBFS_USB_ADDR_MASK 0x7F // bit mask for USB device address + +/* USB_STATUS */ +#define USBFS_USB_STATUS_OFFSET 0x04 + +/* USB_MIS_ST */ +#define USBFS_MIS_ST_OFFSET 0x05 +#define USBFS_UMS_SOF_PRES 0x80 // RO, indicate host SOF timer presage status +#define USBFS_UMS_SOF_ACT 0x40 // RO, indicate host SOF timer action status for USB host +#define USBFS_UMS_SIE_FREE 0x20 // RO, indicate USB SIE free status +#define USBFS_UMS_R_FIFO_RDY 0x10 // RO, indicate USB receiving FIFO ready status (not empty) +#define USBFS_UMS_BUS_RESET 0x08 // RO, indicate USB bus reset status +#define USBFS_UMS_SUSPEND 0x04 // RO, indicate USB suspend status +#define USBFS_UMS_DM_LEVEL 0x02 // RO, indicate UDM level saved at device attached to USB host +#define USBFS_UMS_DEV_ATTACH 0x01 // RO, indicate device attached status on USB host + +/* USB_INT_FG */ +#define USBFS_INT_FG_OFFSET 0x06 +#define USBFS_U_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received +#define USBFS_U_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define USBFS_U_SIE_FREE 0x20 // RO, indicate USB SIE free status +#define USBFS_UIF_FIFO_OV 0x10 // FIFO overflow interrupt flag for USB, direct bit address clear or write 1 to clear +#define USBFS_UIF_HST_SOF 0x08 // host SOF timer interrupt flag for USB host, direct bit address clear or write 1 to clear +#define USBFS_UIF_SUSPEND 0x04 // USB suspend or resume event interrupt flag, direct bit address clear or write 1 to clear +#define USBFS_UIF_TRANSFER 0x02 // USB transfer completion interrupt flag, direct bit address clear or write 1 to clear +#define USBFS_UIF_DETECT 0x01 // device detected event interrupt flag for USB host mode, direct bit address clear or write 1 to clear +#define USBFS_UIF_BUS_RST 0x01 // bus reset event interrupt flag for USB device mode, direct bit address clear or write 1 to clear + +/* USB_INT_ST */ +#define USBFS_INT_ST_OFFSET 0x07 +#define USBFS_UIS_IS_SETUP 0x80 // RO, indicate current USB transfer is setup received for USB device mode +#define USBFS_UIS_IS_NAK 0x80 // RO, indicate current USB transfer is NAK received for USB device mode +#define USBFS_UIS_TOG_OK 0x40 // RO, indicate current USB transfer toggle is OK +#define USBFS_UIS_TOKEN1 0x20 // RO, current token PID code bit 1 received for USB device mode +#define USBFS_UIS_TOKEN0 0x10 // RO, current token PID code bit 0 received for USB device mode +#define USBFS_UIS_TOKEN_MASK 0x30 // RO, bit mask of current token PID code received for USB device mode +#define USBFS_UIS_TOKEN_OUT 0x00 +#define USBFS_UIS_TOKEN_SOF 0x10 +#define USBFS_UIS_TOKEN_IN 0x20 +#define USBFS_UIS_TOKEN_SETUP 0x30 +// UIS_TOKEN1 & UIS_TOKEN0: current token PID code received for USB device mode +// 00: OUT token PID received +// 01: SOF token PID received +// 10: IN token PID received +// 11: SETUP token PID received +#define USBFS_UIS_ENDP_MASK 0x0F // RO, bit mask of current transfer endpoint number for USB device mode +/* USB_RX_LEN */ +#define USBFS_RX_LEN_OFFSET 0x08 + +/******************* DEVICE ******************/ + +/* UDEV_CTRL */ +#define USBFS_UDEV_CTRL_OFFSET 0x01 +#define USBFS_UD_PD_DIS 0x80 // disable USB UDP/UDM pulldown resistance: 0=enable pulldown, 1=disable +#define USBFS_UD_DP_PIN 0x20 // ReadOnly: indicate current UDP pin level +#define USBFS_UD_DM_PIN 0x10 // ReadOnly: indicate current UDM pin level +#define USBFS_UD_LOW_SPEED 0x04 // enable USB physical port low speed: 0=full speed, 1=low speed +#define USBFS_UD_GP_BIT 0x02 // general purpose bit +#define USBFS_UD_PORT_EN 0x01 // enable USB physical port I/O: 0=disable, 1=enable + +/* UEP4_1_MOD */ +#define USBFS_UEP4_1_MOD_OFFSET 0x0C +#define USBFS_UEP1_RX_EN 0x80 // enable USB endpoint 1 receiving (OUT) +#define USBFS_UEP1_TX_EN 0x40 // enable USB endpoint 1 transmittal (IN) +#define USBFS_UEP1_BUF_MOD 0x10 // buffer mode of USB endpoint 1 +// UEPn_RX_EN & UEPn_TX_EN & UEPn_BUF_MOD: USB endpoint 1/2/3 buffer mode, buffer start address is UEPn_DMA +// 0 0 x: disable endpoint and disable buffer +// 1 0 0: 64 bytes buffer for receiving (OUT endpoint) +// 1 0 1: dual 64 bytes buffer by toggle bit bUEP_R_TOG selection for receiving (OUT endpoint), total=128bytes +// 0 1 0: 64 bytes buffer for transmittal (IN endpoint) +// 0 1 1: dual 64 bytes buffer by toggle bit bUEP_T_TOG selection for transmittal (IN endpoint), total=128bytes +// 1 1 0: 64 bytes buffer for receiving (OUT endpoint) + 64 bytes buffer for transmittal (IN endpoint), total=128bytes +// 1 1 1: dual 64 bytes buffer by bUEP_R_TOG selection for receiving (OUT endpoint) + dual 64 bytes buffer by bUEP_T_TOG selection for transmittal (IN endpoint), total=256bytes +#define USBFS_UEP4_RX_EN 0x08 // enable USB endpoint 4 receiving (OUT) +#define USBFS_UEP4_TX_EN 0x04 // enable USB endpoint 4 transmittal (IN) +// UEP4_RX_EN & UEP4_TX_EN: USB endpoint 4 buffer mode, buffer start address is UEP0_DMA +// 0 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) +// 1 0: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 receiving (OUT endpoint), total=128bytes +// 0 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=128bytes +// 1 1: single 64 bytes buffer for endpoint 0 receiving & transmittal (OUT & IN endpoint) +// + 64 bytes buffer for endpoint 4 receiving (OUT endpoint) + 64 bytes buffer for endpoint 4 transmittal (IN endpoint), total=192bytes + +/* UEP2_3_MOD */ +#define USBFS_UEP2_3_MOD_OFFSET 0x0D +#define USBFS_UEP3_RX_EN 0x80 // enable USB endpoint 3 receiving (OUT) +#define USBFS_UEP3_TX_EN 0x40 // enable USB endpoint 3 transmittal (IN) +#define USBFS_UEP3_BUF_MOD 0x10 // buffer mode of USB endpoint 3 +#define USBFS_UEP2_RX_EN 0x08 // enable USB endpoint 2 receiving (OUT) +#define USBFS_UEP2_TX_EN 0x04 // enable USB endpoint 2 transmittal (IN) +#define USBFS_UEP2_BUF_MOD 0x01 // buffer mode of USB endpoint 2 + +/* UEP5_6_MOD */ +#define USBFS_UEP5_6_MOD_OFFSET 0x0E +#define USBFS_UEP6_RX_EN 0x80 // enable USB endpoint 6 receiving (OUT) +#define USBFS_UEP6_TX_EN 0x40 // enable USB endpoint 6 transmittal (IN) +#define USBFS_UEP6_BUF_MOD 0x10 // buffer mode of USB endpoint 6 +#define USBFS_UEP5_RX_EN 0x08 // enable USB endpoint 5 receiving (OUT) +#define USBFS_UEP5_TX_EN 0x04 // enable USB endpoint 5 transmittal (IN) +#define USBFS_UEP5_BUF_MOD 0x01 // buffer mode of USB endpoint 5 + +/* UEP7_MOD */ +#define USBFS_UEP7_MOD_OFFSET 0x0F +#define USBFS_UEP7_RX_EN 0x08 // enable USB endpoint 7 receiving (OUT) +#define USBFS_UEP7_TX_EN 0x04 // enable USB endpoint 7 transmittal (IN) +#define USBFS_UEP7_BUF_MOD 0x01 // buffer mode of USB endpoint 7 + +/* USB_DMA */ +#define USBFS_UEPx_DMA_OFFSET(n) (0x10 + 4 * (n)) // endpoint x DMA buffer address +#define USBFS_UEP0_DMA_OFFSET 0x10 // endpoint 0 DMA buffer address +#define USBFS_UEP1_DMA_OFFSET 0x14 // endpoint 1 DMA buffer address +#define USBFS_UEP2_DMA_OFFSET 0x18 // endpoint 2 DMA buffer address +#define USBFS_UEP3_DMA_OFFSET 0x1c // endpoint 3 DMA buffer address +#define USBFS_UEP4_DMA_OFFSET 0x20 // endpoint 4 DMA buffer address +#define USBFS_UEP5_DMA_OFFSET 0x24 // endpoint 5 DMA buffer address +#define USBFS_UEP6_DMA_OFFSET 0x28 // endpoint 6 DMA buffer address +#define USBFS_UEP7_DMA_OFFSET 0x2c // endpoint 7 DMA buffer address +/* USB_EP_CTRL */ +#define USBFS_UEPx_T_LEN_OFFSET(n) (0x30 + 4 * (n)) // endpoint x DMA buffer address +#define USBFS_UEPx_TX_CTRL_OFFSET(n) (0x30 + 4 * (n) + 2) // endpoint x DMA buffer address +#define USBFS_UEPx_RX_CTRL_OFFSET(n) (0x30 + 4 * (n) + 3) // endpoint x DMA buffer address + +#define USBFS_UEP_AUTO_TOG 0x10 // enable automatic toggle after successful transfer completion on endpoint 1/2/3: 0=manual toggle, 1=automatic toggle +#define USBFS_UEP_R_TOG 0x80 // expected data toggle flag of USB endpoint X receiving (OUT): 0=DATA0, 1=DATA1 +#define USBFS_UEP_T_TOG 0x40 // prepared data toggle flag of USB endpoint X transmittal (IN): 0=DATA0, 1=DATA1 + +#define USBFS_UEP_R_RES_MASK 0x0C // bit mask of handshake response type for USB endpoint X receiving (OUT) +#define USBFS_UEP_R_RES_ACK 0x00 +#define USBFS_UEP_R_RES_TOUT 0x04 +#define USBFS_UEP_R_RES_NAK 0x08 +#define USBFS_UEP_R_RES_STALL 0x0C +// RB_UEP_R_RES1 & RB_UEP_R_RES0: handshake response type for USB endpoint X receiving (OUT) +// 00: ACK (ready) +// 01: no response, time out to host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: STALL (error) +#define USBFS_UEP_T_RES_MASK 0x03 // bit mask of handshake response type for USB endpoint X transmittal (IN) +#define USBFS_UEP_T_RES_ACK 0x00 +#define USBFS_UEP_T_RES_TOUT 0x01 +#define USBFS_UEP_T_RES_NAK 0x02 +#define USBFS_UEP_T_RES_STALL 0x03 +// bUEP_T_RES1 & bUEP_T_RES0: handshake response type for USB endpoint X transmittal (IN) +// 00: DATA0 or DATA1 then expecting ACK (ready) +// 01: DATA0 or DATA1 then expecting no response, time out from host, for non-zero endpoint isochronous transactions +// 10: NAK (busy) +// 11: TALL (error) + +#endif diff --git a/ch32v103_hallarray_controller/3rdparty/CherryUSB/port/ch32v103/usb_dc_ch32v1_usbfs.c b/ch32v103_hallarray_controller/3rdparty/CherryUSB/port/ch32v103/usb_dc_ch32v1_usbfs.c new file mode 100644 index 0000000..566e778 --- /dev/null +++ b/ch32v103_hallarray_controller/3rdparty/CherryUSB/port/ch32v103/usb_dc_ch32v1_usbfs.c @@ -0,0 +1,412 @@ +/* + * Copyright (c) 2022, sakumisu + * + * SPDX-License-Identifier: Apache-2.0 + */ +#include "usbd_core.h" +#include "usb_ch32v1_usbfs_reg.h" +#include "ch32v10x.h" + +#ifdef CONFIG_USB_HS +#error "usb fs do not support hs" +#endif + +void USBFS_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); + +#ifndef USB_NUM_BIDIR_ENDPOINTS +#define USB_NUM_BIDIR_ENDPOINTS 8 +#endif + +#define USB_SET_DMA(ep_idx, addr) (*(volatile uint32_t *)((uint32_t)(&USBFS_DEVICE->UEP0_DMA) + 4 * ep_idx) = addr) +#define USB_SET_TX_LEN(ep_idx, len) (*(volatile uint16_t *)((uint32_t)(&USBFS_DEVICE->UEP0_TX_LEN) + 4 * ep_idx) = len) +#define USB_GET_TX_LEN(ep_idx) (*(volatile uint16_t *)((uint32_t)(&USBFS_DEVICE->UEP0_TX_LEN) + 4 * ep_idx)) +#define USB_SET_TX_CTRL(ep_idx, val) (*(volatile uint8_t *)((uint32_t)(&USBFS_DEVICE->UEP0_CTRL) + 4 * ep_idx) = val) +#define USB_GET_TX_CTRL(ep_idx) (*(volatile uint8_t *)((uint32_t)(&USBFS_DEVICE->UEP0_CTRL) + 4 * ep_idx)) +#define USB_SET_RX_CTRL(ep_idx, val) (*(volatile uint8_t *)((uint32_t)(&USBFS_DEVICE->UEP0_CTRL) + 4 * ep_idx) = val) +#define USB_GET_RX_CTRL(ep_idx) (*(volatile uint8_t *)((uint32_t)(&USBFS_DEVICE->UEP0_CTRL) + 4 * ep_idx)) + +#define USB_EPn_SET_TX_NAK(ep_idx) USB_SET_TX_CTRL(ep_idx, (USB_GET_TX_CTRL(ep_idx) & ~USBFS_UEP_T_RES_MASK) | USBFS_UEP_T_RES_NAK); +#define USB_EPn_SET_TX_ACK(ep_idx) USB_SET_TX_CTRL(ep_idx, (USB_GET_TX_CTRL(ep_idx) & ~USBFS_UEP_T_RES_MASK) | USBFS_UEP_T_RES_ACK); + +#define USB_EPn_SET_RX_NAK(ep_idx) USB_SET_RX_CTRL(ep_idx, (USB_GET_RX_CTRL(ep_idx) & ~USBFS_UEP_R_RES_MASK) | USBFS_UEP_R_RES_NAK); +#define USB_EPn_SET_RX_ACK(ep_idx) USB_SET_RX_CTRL(ep_idx, (USB_GET_RX_CTRL(ep_idx) & ~USBFS_UEP_R_RES_MASK) | USBFS_UEP_R_RES_ACK); + +/* Endpoint state */ +struct ch32_usbfs_ep_state { + uint16_t ep_mps; /* Endpoint max packet size */ + uint8_t ep_type; /* Endpoint type */ + uint8_t ep_stalled; /* Endpoint stall flag */ + uint8_t ep_enable; /* Endpoint enable */ + uint8_t *xfer_buf; + uint32_t xfer_len; + uint32_t actual_xfer_len; +}; + +/* Driver state */ +struct ch32_usbfs_udc { + __attribute__((aligned(4))) struct usb_setup_packet setup; + volatile uint8_t dev_addr; + struct ch32_usbfs_ep_state in_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< IN endpoint parameters*/ + struct ch32_usbfs_ep_state out_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< OUT endpoint parameters */ + __attribute__((aligned(4))) uint8_t ep_databuf[USB_NUM_BIDIR_ENDPOINTS][64 + 64]; /*!< epx_out(64)+epx_in(64) */ +} g_ch32_usbfs_udc; + +volatile bool ep0_rx_data_toggle; +volatile bool ep0_tx_data_toggle; + +__WEAK void usb_dc_low_level_init(void) +{ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA, ENABLE); + + RCC_USBCLKConfig(RCC_USBCLKSource_PLLCLK_1Div5); //USBCLK=PLLCLK/1.5=48Mhz + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_USBHD, ENABLE); + + NVIC_InitTypeDef NVIC_InitStructure; + + NVIC_InitStructure.NVIC_IRQChannel = USBHD_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 1; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + EXTEN->EXTEN_CTR |= EXTEN_USBHD_IO_EN; + EXTEN->EXTEN_CTR |= EXTEN_USB_5V_SEL; +} + +__WEAK void usb_dc_low_level_deinit(void) +{ + +} + +int usb_dc_init(uint8_t busid) +{ + memset(&g_ch32_usbfs_udc, 0, sizeof(struct ch32_usbfs_udc)); + + usb_dc_low_level_init(); + + USBFS_DEVICE->BASE_CTRL = 0x00; + + USBFS_DEVICE->UEP4_1_MOD = USBFS_UEP4_RX_EN | USBFS_UEP4_TX_EN | USBFS_UEP1_RX_EN | USBFS_UEP1_TX_EN; + USBFS_DEVICE->UEP2_3_MOD = USBFS_UEP2_RX_EN | USBFS_UEP2_TX_EN | USBFS_UEP3_RX_EN | USBFS_UEP3_TX_EN; + USBFS_DEVICE->UEP5_6_MOD = USBFS_UEP5_RX_EN | USBFS_UEP5_TX_EN | USBFS_UEP6_RX_EN | USBFS_UEP6_TX_EN; + USBFS_DEVICE->UEP7_MOD = USBFS_UEP7_RX_EN | USBFS_UEP7_TX_EN; + + USBFS_DEVICE->UEP0_DMA = (uint16_t)(uint32_t)g_ch32_usbfs_udc.ep_databuf[0]; + USBFS_DEVICE->UEP1_DMA = (uint16_t)(uint32_t)g_ch32_usbfs_udc.ep_databuf[1]; + USBFS_DEVICE->UEP2_DMA = (uint16_t)(uint32_t)g_ch32_usbfs_udc.ep_databuf[2]; + USBFS_DEVICE->UEP3_DMA = (uint16_t)(uint32_t)g_ch32_usbfs_udc.ep_databuf[3]; + USBFS_DEVICE->UEP4_DMA = (uint16_t)(uint32_t)g_ch32_usbfs_udc.ep_databuf[4]; + USBFS_DEVICE->UEP5_DMA = (uint16_t)(uint32_t)g_ch32_usbfs_udc.ep_databuf[5]; + USBFS_DEVICE->UEP6_DMA = (uint16_t)(uint32_t)g_ch32_usbfs_udc.ep_databuf[6]; + USBFS_DEVICE->UEP7_DMA = (uint16_t)(uint32_t)g_ch32_usbfs_udc.ep_databuf[7]; + + USBFS_DEVICE->INT_FG = 0xFF; + USBFS_DEVICE->INT_EN = USBFS_UIE_SUSPEND | USBFS_UIE_BUS_RST | USBFS_UIE_TRANSFER; + USBFS_DEVICE->DEV_ADDR = 0x00; + + USBFS_DEVICE->BASE_CTRL = USBFS_UC_DEV_PU_EN | USBFS_UC_INT_BUSY | USBFS_UC_DMA_EN; + USBFS_DEVICE->UDEV_CTRL = USBFS_UD_PD_DIS | USBFS_UD_PORT_EN; + return 0; +} + +int usb_dc_deinit(uint8_t busid) +{ + return 0; +} + +int usbd_set_address(uint8_t busid, const uint8_t addr) +{ + if (addr == 0) { + USBFS_DEVICE->DEV_ADDR = (USBFS_DEVICE->DEV_ADDR & USBFS_UDA_GP_BIT) | 0; + } + g_ch32_usbfs_udc.dev_addr = addr; + return 0; +} + +uint8_t usbd_get_port_speed(uint8_t busid) +{ + return USB_SPEED_FULL; +} + +int usbd_ep_open(uint8_t busid, const struct usb_endpoint_descriptor *ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep->bEndpointAddress); + + if (USB_EP_DIR_IS_OUT(ep->bEndpointAddress)) { + g_ch32_usbfs_udc.out_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_ch32_usbfs_udc.out_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_ch32_usbfs_udc.out_ep[ep_idx].ep_enable = true; + + USB_EPn_SET_RX_NAK(ep_idx); + + if (ep_idx == 0 || ep_idx == 4) { + } else { + USB_SET_RX_CTRL(ep_idx, (USB_GET_RX_CTRL(ep_idx) | USBFS_UEP_AUTO_TOG)); + } + + } else { + g_ch32_usbfs_udc.in_ep[ep_idx].ep_mps = USB_GET_MAXPACKETSIZE(ep->wMaxPacketSize); + g_ch32_usbfs_udc.in_ep[ep_idx].ep_type = USB_GET_ENDPOINT_TYPE(ep->bmAttributes); + g_ch32_usbfs_udc.in_ep[ep_idx].ep_enable = true; + + USB_EPn_SET_TX_NAK(ep_idx); + + if (ep_idx == 0 || ep_idx == 4) { + } else { + USB_SET_TX_CTRL(ep_idx, (USB_GET_TX_CTRL(ep_idx) | USBFS_UEP_AUTO_TOG)); + } + } + return 0; +} + +int usbd_ep_close(uint8_t busid, const uint8_t ep) +{ + return 0; +} + +int usbd_ep_set_stall(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (USB_EP_DIR_IS_OUT(ep)) { + USB_SET_RX_CTRL(ep_idx, (USB_GET_RX_CTRL(ep_idx) & ~USBFS_UEP_R_RES_MASK) | USBFS_UEP_R_RES_STALL); + } else { + USB_SET_TX_CTRL(ep_idx, (USB_GET_TX_CTRL(ep_idx) & ~USBFS_UEP_T_RES_MASK) | USBFS_UEP_T_RES_STALL); + } + + return 0; +} + +int usbd_ep_clear_stall(uint8_t busid, const uint8_t ep) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (USB_EP_DIR_IS_OUT(ep)) { + USB_SET_RX_CTRL(ep_idx, (USB_GET_RX_CTRL(ep_idx) & ~(USBFS_UEP_R_TOG | USBFS_UEP_R_RES_MASK)) | USBFS_UEP_R_RES_ACK); + } else { + USB_SET_TX_CTRL(ep_idx, (USB_GET_TX_CTRL(ep_idx) & ~(USBFS_UEP_T_TOG | USBFS_UEP_T_RES_MASK)) | USBFS_UEP_T_RES_NAK); + } + return 0; +} + +int usbd_ep_is_stalled(uint8_t busid, const uint8_t ep, uint8_t *stalled) +{ + return 0; +} + +int usbd_ep_start_write(uint8_t busid, const uint8_t ep, const uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (!data && data_len) { + return -1; + } + if (!g_ch32_usbfs_udc.in_ep[ep_idx].ep_enable) { + return -2; + } + + if ((uint32_t)data & 0x03) { + printf("usbd_ep_start_write ep:%0x: data pointer@0x%08X is not 4-byte aligned\r\n", ep, data); + return -3; + } + + g_ch32_usbfs_udc.in_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_ch32_usbfs_udc.in_ep[ep_idx].xfer_len = data_len; + g_ch32_usbfs_udc.in_ep[ep_idx].actual_xfer_len = 0; + + if (data_len == 0) { + USB_SET_TX_LEN(ep_idx, 0); + } else { + data_len = MIN(data_len, g_ch32_usbfs_udc.in_ep[ep_idx].ep_mps); + USB_SET_TX_LEN(ep_idx, data_len); + if (ep_idx == 0) { + memcpy(&g_ch32_usbfs_udc.ep_databuf[0], data, data_len); + } else { + memcpy(&g_ch32_usbfs_udc.ep_databuf[ep_idx][64], data, data_len); + } + } + + USB_EPn_SET_TX_ACK(ep_idx); + return 0; +} + +int usbd_ep_start_read(uint8_t busid, const uint8_t ep, uint8_t *data, uint32_t data_len) +{ + uint8_t ep_idx = USB_EP_GET_IDX(ep); + + if (!data && data_len) { + return -1; + } + + if (!g_ch32_usbfs_udc.out_ep[ep_idx].ep_enable) { + return -2; + } + + if ((uint32_t)data & 0x03) { + printf("usbd_ep_start_read: data pointer@0x%08X is not 4-byte aligned\r\n", data); + return -3; + } + + g_ch32_usbfs_udc.out_ep[ep_idx].xfer_buf = (uint8_t *)data; + g_ch32_usbfs_udc.out_ep[ep_idx].xfer_len = data_len; + g_ch32_usbfs_udc.out_ep[ep_idx].actual_xfer_len = 0; + + if (ep_idx == 0) { + if (data_len == 0) { + + } else { + + } + } else { + + } + + USB_EPn_SET_RX_ACK(ep_idx); + + return 0; +} + +void USBFS_IRQHandler(void) +{ + volatile uint32_t ep_idx = 0, token, write_count, read_count; + volatile uint8_t intflag = 0; + + intflag = USBFS_DEVICE->INT_FG; + + if (intflag & USBFS_UIF_TRANSFER) { + token = USBFS_DEVICE->INT_ST & USBFS_UIS_TOKEN_MASK; + ep_idx = USBFS_DEVICE->INT_ST & USBFS_UIS_ENDP_MASK; + switch (token) { + case USBFS_UIS_TOKEN_SETUP: + USBFS_DEVICE->UEP0_CTRL = USBFS_UEP_R_TOG | USBFS_UEP_T_TOG | USBFS_UEP_T_RES_NAK; + memcpy((uint8_t *)&g_ch32_usbfs_udc.setup, (uint8_t *)&g_ch32_usbfs_udc.ep_databuf[0], 8); + + if (g_ch32_usbfs_udc.setup.bmRequestType >> USB_REQUEST_DIR_SHIFT == 0) { + USB_SET_TX_LEN(0, 0); + USB_EPn_SET_TX_ACK(0); + } + + USB_EPn_SET_RX_NAK(0); + usbd_event_ep0_setup_complete_handler(0, (uint8_t *)&g_ch32_usbfs_udc.setup); + break; + + case USBFS_UIS_TOKEN_IN: + if (ep_idx == 0x00) { + switch (g_ch32_usbfs_udc.setup.bmRequestType >> USB_REQUEST_DIR_SHIFT) { + case 1: + USBFS_DEVICE->UEP0_CTRL ^= USBFS_UEP_T_TOG; + USB_EPn_SET_TX_NAK(0); + + if (g_ch32_usbfs_udc.in_ep[ep_idx].xfer_len > g_ch32_usbfs_udc.in_ep[ep_idx].ep_mps) { + g_ch32_usbfs_udc.in_ep[ep_idx].xfer_len -= g_ch32_usbfs_udc.in_ep[ep_idx].ep_mps; + g_ch32_usbfs_udc.in_ep[ep_idx].actual_xfer_len += g_ch32_usbfs_udc.in_ep[ep_idx].ep_mps; + } else { + g_ch32_usbfs_udc.in_ep[ep_idx].actual_xfer_len += g_ch32_usbfs_udc.in_ep[ep_idx].xfer_len; + g_ch32_usbfs_udc.in_ep[ep_idx].xfer_len = 0; + } + + usbd_event_ep_in_complete_handler(0, ep_idx | 0x80, g_ch32_usbfs_udc.in_ep[ep_idx].actual_xfer_len); + break; + + case 0: + switch (g_ch32_usbfs_udc.setup.bRequest) { + case USB_REQUEST_SET_ADDRESS: + USBFS_DEVICE->DEV_ADDR = (USBFS_DEVICE->DEV_ADDR & USBFS_UDA_GP_BIT) | g_ch32_usbfs_udc.dev_addr; + USB_EPn_SET_TX_NAK(0); + USB_EPn_SET_RX_ACK(0); + break; + + default: + USB_EPn_SET_TX_NAK(0); + USB_EPn_SET_RX_ACK(0); + break; + } + break; + } + + } else { + if (ep_idx == 4) { + USBFS_DEVICE->UEP4_CTRL ^= USBFS_UEP_T_TOG; + } + USB_EPn_SET_TX_NAK(ep_idx); + + if (g_ch32_usbfs_udc.in_ep[ep_idx].xfer_len > g_ch32_usbfs_udc.in_ep[ep_idx].ep_mps) { + g_ch32_usbfs_udc.in_ep[ep_idx].xfer_buf += g_ch32_usbfs_udc.in_ep[ep_idx].ep_mps; + g_ch32_usbfs_udc.in_ep[ep_idx].xfer_len -= g_ch32_usbfs_udc.in_ep[ep_idx].ep_mps; + g_ch32_usbfs_udc.in_ep[ep_idx].actual_xfer_len += g_ch32_usbfs_udc.in_ep[ep_idx].ep_mps; + + write_count = MIN(g_ch32_usbfs_udc.in_ep[ep_idx].xfer_len, g_ch32_usbfs_udc.in_ep[ep_idx].ep_mps); + USB_SET_TX_LEN(ep_idx, write_count); + memcpy(&g_ch32_usbfs_udc.ep_databuf[ep_idx][64], g_ch32_usbfs_udc.in_ep[ep_idx].xfer_buf, write_count); + + USB_EPn_SET_TX_ACK(ep_idx); + } else { + g_ch32_usbfs_udc.in_ep[ep_idx].actual_xfer_len += g_ch32_usbfs_udc.in_ep[ep_idx].xfer_len; + g_ch32_usbfs_udc.in_ep[ep_idx].xfer_len = 0; + usbd_event_ep_in_complete_handler(0, ep_idx | 0x80, g_ch32_usbfs_udc.in_ep[ep_idx].actual_xfer_len); + } + } + break; + case USBFS_UIS_TOKEN_OUT: + if (ep_idx == 0x00) { + USBFS_DEVICE->UEP0_CTRL ^= USBFS_UEP_R_TOG; + read_count = USBFS_DEVICE->RX_LEN; + + memcpy(g_ch32_usbfs_udc.out_ep[ep_idx].xfer_buf, (uint8_t *)&g_ch32_usbfs_udc.ep_databuf[0], read_count); + + g_ch32_usbfs_udc.out_ep[ep_idx].actual_xfer_len += read_count; + g_ch32_usbfs_udc.out_ep[ep_idx].xfer_len -= read_count; + + usbd_event_ep_out_complete_handler(0, 0x00, g_ch32_usbfs_udc.out_ep[ep_idx].actual_xfer_len); + + if (read_count == 0) { + /* Out status, start reading setup */ + USB_EPn_SET_RX_ACK(ep_idx) + } + } else { + if (USBFS_DEVICE->INT_ST & USBFS_UIS_TOG_OK) { + if (ep_idx == 4) { + USBFS_DEVICE->UEP4_CTRL ^= USBFS_UEP_R_TOG; + } + + read_count = USBFS_DEVICE->RX_LEN; + + memcpy(g_ch32_usbfs_udc.out_ep[ep_idx].xfer_buf, &g_ch32_usbfs_udc.ep_databuf[ep_idx][0], read_count); + + g_ch32_usbfs_udc.out_ep[ep_idx].xfer_buf += read_count; + g_ch32_usbfs_udc.out_ep[ep_idx].actual_xfer_len += read_count; + g_ch32_usbfs_udc.out_ep[ep_idx].xfer_len -= read_count; + + if ((read_count < g_ch32_usbfs_udc.out_ep[ep_idx].ep_mps) || (g_ch32_usbfs_udc.out_ep[ep_idx].xfer_len == 0)) { + usbd_event_ep_out_complete_handler(0, ep_idx, g_ch32_usbfs_udc.out_ep[ep_idx].actual_xfer_len); + } else { + USB_EPn_SET_RX_ACK(ep_idx); + } + } + } + break; + + case USBFS_UIS_TOKEN_SOF: + break; + + default: + break; + } + + USBFS_DEVICE->INT_FG = USBFS_UIF_TRANSFER; + } else if (intflag & USBFS_UIF_BUS_RST) { + USBFS_DEVICE-> DEV_ADDR = 0; + usbd_event_reset_handler(0); + USB_EPn_SET_RX_ACK(0); + USBFS_DEVICE->INT_FG = USBFS_UIF_BUS_RST; + } else if (intflag & USBFS_UIF_SUSPEND) { + if (USBFS_DEVICE->MIS_ST & USBFS_UMS_SUSPEND) { + + } else { + + } + USBFS_DEVICE->INT_FG = USBFS_UIF_SUSPEND; + } else { + USBFS_DEVICE->INT_FG = intflag; + } +} diff --git a/ch32v103_hallarray_controller/ch32v103_hallarray_controller.wvproj b/ch32v103_hallarray_controller/ch32v103_hallarray_controller.wvproj new file mode 100644 index 0000000000000000000000000000000000000000..bba9fc56081371be8eddf1a88d88770a407ded40 GIT binary patch literal 202 zcmV;*05$)DGAO`;2*!#FZV_9e8dJ5jB$!Mm7f>4!o>otYCtadwf4e3dN=?IpRKaIr z!4qMswl{*YT2;YJl!L;hniL8*JFZzpYI&R!uRJzQgmF@nQ2_`J9KwOT0CbsWxswq* zGJmaZgFh$>x_pv<1af>7sHqrhsj|NWwsbIhU@uZCUmy=bQ39oHF+KqtUuha?kt{DI zUO^|hGf^BebV9ndP&PS&p$AkpR}PM-X+l{|Z + +/* define compiler specific symbols */ +#if defined(__CC_ARM) + #define __ASM __asm /* asm keyword for ARM Compiler */ + #define __INLINE __inline /* inline keyword for ARM Compiler */ + +#elif defined(__ICCARM__) + #define __ASM __asm /* asm keyword for IAR Compiler */ + #define __INLINE inline /* inline keyword for IAR Compiler. Only avaiable in High optimization mode! */ + +#elif defined(__GNUC__) + #define __ASM __asm /* asm keyword for GNU Compiler */ + #define __INLINE inline /* inline keyword for GNU Compiler */ + +#elif defined(__TASKING__) + #define __ASM __asm /* asm keyword for TASKING Compiler */ + #define __INLINE inline /* inline keyword for TASKING Compiler */ + +#endif + +/********************************************************************* + * @fn __get_MSTATUS + * + * @brief Return the Machine Status Register + * + * @return mstatus value + */ +uint32_t __get_MSTATUS(void) +{ + uint32_t result; + + __ASM volatile("csrr %0," "mstatus": "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MSTATUS + * + * @brief Set the Machine Status Register + * + * @param value - set mstatus value + * + * @return none + */ +void __set_MSTATUS(uint32_t value) +{ + __ASM volatile("csrw mstatus, %0" : : "r"(value)); +} + +/********************************************************************* + * @fn __get_MISA + * + * @brief Return the Machine ISA Register + * + * @return misa value + */ +uint32_t __get_MISA(void) +{ + uint32_t result; + + __ASM volatile("csrr %0,""misa" : "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MISA + * + * @brief Set the Machine ISA Register + * + * @param value - set misa value + * + * @return none + */ +void __set_MISA(uint32_t value) +{ + __ASM volatile("csrw misa, %0" : : "r"(value)); +} + +/********************************************************************* + * @fn __get_MTVEC + * + * @brief Return the Machine Trap-Vector Base-Address Register + * + * @return mtvec value + */ +uint32_t __get_MTVEC(void) +{ + uint32_t result; + + __ASM volatile("csrr %0," "mtvec": "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MTVEC + * + * @brief Set the Machine Trap-Vector Base-Address Register + * + * @param value - set mtvec value + * + * @return none + */ +void __set_MTVEC(uint32_t value) +{ + __ASM volatile("csrw mtvec, %0":: "r"(value)); +} + +/********************************************************************* + * @fn __get_MSCRATCH + * + * @brief Return the Machine Seratch Register + * + * @return mscratch value + */ +uint32_t __get_MSCRATCH(void) +{ + uint32_t result; + + __ASM volatile("csrr %0," "mscratch" : "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MSCRATCH + * + * @brief Set the Machine Seratch Register + * + * @param value - set mscratch value + * + * @return none + */ +void __set_MSCRATCH(uint32_t value) +{ + __ASM volatile("csrw mscratch, %0" : : "r"(value)); +} + +/********************************************************************* + * @fn __get_MEPC + * + * @brief Return the Machine Exception Program Register + * + * @return mepc value + */ +uint32_t __get_MEPC(void) +{ + uint32_t result; + + __ASM volatile("csrr %0," "mepc" : "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MEPC + * + * @brief Set the Machine Exception Program Register + * + * @return mepc value + */ +void __set_MEPC(uint32_t value) +{ + __ASM volatile("csrw mepc, %0" : : "r"(value)); +} + +/********************************************************************* + * @fn __get_MCAUSE + * + * @brief Return the Machine Cause Register + * + * @return mcause value + */ +uint32_t __get_MCAUSE(void) +{ + uint32_t result; + + __ASM volatile("csrr %0," "mcause": "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MEPC + * + * @brief Set the Machine Cause Register + * + * @return mcause value + */ +void __set_MCAUSE(uint32_t value) +{ + __ASM volatile("csrw mcause, %0":: "r"(value)); +} + +/********************************************************************* + * @fn __get_MTVAL + * + * @brief Return the Machine Trap Value Register + * + * @return mtval value + */ +uint32_t __get_MTVAL(void) +{ + uint32_t result; + + __ASM volatile("csrr %0," "mtval" : "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __set_MTVAL + * + * @brief Set the Machine Trap Value Register + * + * @return mtval value + */ +void __set_MTVAL(uint32_t value) +{ + __ASM volatile("csrw mtval, %0":: "r"(value)); +} + +/********************************************************************* + * @fn __get_MVENDORID + * + * @brief Return Vendor ID Register + * + * @return mvendorid value + */ +uint32_t __get_MVENDORID(void) +{ + uint32_t result; + + __ASM volatile("csrr %0,""mvendorid": "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __get_MARCHID + * + * @brief Return Machine Architecture ID Register + * + * @return marchid value + */ +uint32_t __get_MARCHID(void) +{ + uint32_t result; + + __ASM volatile("csrr %0,""marchid": "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __get_MIMPID + * + * @brief Return Machine Implementation ID Register + * + * @return mimpid value + */ +uint32_t __get_MIMPID(void) +{ + uint32_t result; + + __ASM volatile("csrr %0,""mimpid": "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __get_MHARTID + * + * @brief Return Hart ID Register + * + * @return mhartid value + */ +uint32_t __get_MHARTID(void) +{ + uint32_t result; + + __ASM volatile("csrr %0,""mhartid": "=r"(result)); + return (result); +} + +/********************************************************************* + * @fn __get_SP + * + * @brief Return SP Register + * + * @return SP value + */ +uint32_t __get_SP(void) +{ + uint32_t result; + + __ASM volatile("mv %0,""sp": "=r"(result):); + return (result); +} diff --git a/ch32v103_hallarray_controller/src/core/core_riscv.h b/ch32v103_hallarray_controller/src/core/core_riscv.h new file mode 100644 index 0000000..a9fdae4 --- /dev/null +++ b/ch32v103_hallarray_controller/src/core/core_riscv.h @@ -0,0 +1,629 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : core_riscv.h + * Author : WCH + * Version : V1.0.1 + * Date : 2023/11/11 + * Description : RISC-V V3 Core Peripheral Access Layer Header File for CH32V10x +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CORE_RISCV_H__ +#define __CORE_RISCV_H__ + +#ifdef __cplusplus +extern "C" { +#endif + + +/* IO definitions */ +#ifdef __cplusplus + #define __I volatile /* defines 'read only' permissions */ +#else + #define __I volatile const /* defines 'read only' permissions */ +#endif +#define __O volatile /* defines 'write only' permissions */ +#define __IO volatile /* defines 'read / write' permissions */ + +/* Standard Peripheral Library old types (maintained for legacy purpose) */ +typedef __I uint32_t vuc32; /* Read Only */ +typedef __I uint16_t vuc16; /* Read Only */ +typedef __I uint8_t vuc8; /* Read Only */ + +typedef const uint32_t uc32; /* Read Only */ +typedef const uint16_t uc16; /* Read Only */ +typedef const uint8_t uc8; /* Read Only */ + +typedef __I int32_t vsc32; /* Read Only */ +typedef __I int16_t vsc16; /* Read Only */ +typedef __I int8_t vsc8; /* Read Only */ + +typedef const int32_t sc32; /* Read Only */ +typedef const int16_t sc16; /* Read Only */ +typedef const int8_t sc8; /* Read Only */ + +typedef __IO uint32_t vu32; +typedef __IO uint16_t vu16; +typedef __IO uint8_t vu8; + +typedef uint32_t u32; +typedef uint16_t u16; +typedef uint8_t u8; + +typedef __IO int32_t vs32; +typedef __IO int16_t vs16; +typedef __IO int8_t vs8; + +typedef int32_t s32; +typedef int16_t s16; +typedef int8_t s8; + +typedef enum {NoREADY = 0, READY = !NoREADY} ErrorStatus; + +typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState; + +typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus; + +#define RV_STATIC_INLINE static inline + +/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */ +typedef struct{ + __I uint32_t ISR[8]; + __I uint32_t IPR[8]; + __IO uint32_t ITHRESDR; + __IO uint32_t VTFBADDRR; + __IO uint32_t CFGR; + __I uint32_t GISR; + uint8_t RESERVED0[0x10]; + __IO uint32_t VTFADDRR[4]; + uint8_t RESERVED1[0x90]; + __O uint32_t IENR[8]; + uint8_t RESERVED2[0x60]; + __O uint32_t IRER[8]; + uint8_t RESERVED3[0x60]; + __O uint32_t IPSR[8]; + uint8_t RESERVED4[0x60]; + __O uint32_t IPRR[8]; + uint8_t RESERVED5[0x60]; + __IO uint32_t IACTR[8]; + uint8_t RESERVED6[0xE0]; + __IO uint8_t IPRIOR[256]; + uint8_t RESERVED7[0x810]; + __IO uint32_t SCTLR; +}PFIC_Type; + +#define FIBADDRR VTFBADDRR +#define FIOFADDRR VTFADDRR + + +/* memory mapped structure for SysTick */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint8_t CNTL0; + __IO uint8_t CNTL1; + __IO uint8_t CNTL2; + __IO uint8_t CNTL3; + __IO uint8_t CNTH0; + __IO uint8_t CNTH1; + __IO uint8_t CNTH2; + __IO uint8_t CNTH3; + __IO uint8_t CMPLR0; + __IO uint8_t CMPLR1; + __IO uint8_t CMPLR2; + __IO uint8_t CMPLR3; + __IO uint8_t CMPHR0; + __IO uint8_t CMPHR1; + __IO uint8_t CMPHR2; + __IO uint8_t CMPHR3; +}SysTick_Type; + + +#define PFIC ((PFIC_Type *) 0xE000E000 ) +#define NVIC PFIC +#define NVIC_KEY1 ((uint32_t)0xFA050000) +#define NVIC_KEY2 ((uint32_t)0xBCAF0000) +#define NVIC_KEY3 ((uint32_t)0xBEEF0000) + +#define SysTick ((SysTick_Type *) 0xE000F000) + +/********************************************************************* + * @fn __enable_irq + * This function is only used for Machine mode. + * + * @brief Enable Global Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __enable_irq() +{ + __asm volatile ("csrs mstatus, %0" : : "r" (0x88) ); +} + +/********************************************************************* + * @fn __disable_irq + * This function is only used for Machine mode. + * + * @brief Disable Global Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __disable_irq() +{ + __asm volatile ("csrc mstatus, %0" : : "r" (0x88) ); +} + +/********************************************************************* + * @fn __NOP + * + * @brief nop + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __NOP() +{ + __asm volatile ("nop"); +} + +/********************************************************************* + * @fn NVIC_EnableIRQ + * + * @brief Enable Interrupt + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) +{ + NVIC->IENR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_DisableIRQ + * + * @brief Disable Interrupt + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) +{ + uint32_t t; + + t = NVIC->ITHRESDR; + NVIC->ITHRESDR = 0x10; + NVIC->IRER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); + NVIC->ITHRESDR = t; +} + +/********************************************************************* + * @fn NVIC_GetStatusIRQ + * + * @brief Get Interrupt Enable State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Enable + * 0 - Interrupt Disable + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetStatusIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->ISR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_GetPendingIRQ + * + * @brief Get Interrupt Pending State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Pending Enable + * 0 - Interrupt Pending Disable + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + return((uint32_t) ((NVIC->IPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_SetPendingIRQ + * + * @brief Set Interrupt Pending + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + NVIC->IPSR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_ClearPendingIRQ + * + * @brief Clear Interrupt Pending + * + * @param IRQn - Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + NVIC->IPRR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); +} + +/********************************************************************* + * @fn NVIC_GetActive + * + * @brief Get Interrupt Active State + * + * @param IRQn - Interrupt Numbers + * + * @return 1 - Interrupt Active + * 0 - Interrupt No Active + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn) +{ + return((uint32_t)((NVIC->IACTR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); +} + +/********************************************************************* + * @fn NVIC_SetPriority + * + * @brief Set Interrupt Priority + * + * @param IRQn - Interrupt Numbers + * interrupt nesting enable(PFIC->CFGR bit1 = 0) + * priority - bit[7] - Preemption Priority + * bit[6:4] - Sub priority + * bit[3:0] - Reserve + * interrupt nesting disable(PFIC->CFGR bit1 = 1) + * priority - bit[7:4] - Sub priority + * bit[3:0] - Reserve + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint8_t priority) +{ + NVIC->IPRIOR[(uint32_t)(IRQn)] = priority; +} + +/********************************************************************* + * @fn __WFI + * + * @brief Wait for Interrupt + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFI(void) +{ + NVIC->SCTLR &= ~(1<<3); // wfi + asm volatile ("wfi"); +} + +/********************************************************************* + * @fn _SEV + * + * @brief Set Event + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _SEV(void) +{ + NVIC->SCTLR |= (1<<3)|(1<<5); +} + +/********************************************************************* + * @fn _WFE + * + * @brief Wait for Events + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void _WFE(void) +{ + NVIC->SCTLR |= (1<<3); + asm volatile ("wfi"); +} + +/********************************************************************* + * @fn __WFE + * + * @brief Wait for Events + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void __WFE(void) +{ + _SEV(); + _WFE(); + _WFE(); +} + +/********************************************************************* + * @fn NVIC_SetFastIRQ + * + * @brief Set VTF Interrupt + * + * @param add - VTF interrupt service function base address. + * IRQn - Interrupt Numbers + * num - VTF Interrupt Numbers + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SetFastIRQ(uint32_t addr, IRQn_Type IRQn, uint8_t num) +{ + if(num > 3) return ; + NVIC->VTFBADDRR = addr; + NVIC->VTFADDRR[num] = ((uint32_t)IRQn<<24)|(addr&0xfffff); +} + +/********************************************************************* + * @fn NVIC_SystemReset + * + * @brief Initiate a system reset request + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_SystemReset(void) +{ + NVIC->CFGR = NVIC_KEY3|(1<<7); +} + +/********************************************************************* + * @fn NVIC_HaltPushCfg + * + * @brief Enable Hardware Stack + * + * @param NewState - DISABLE or ENABLE + + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_HaltPushCfg(FunctionalState NewState) +{ + if (NewState != DISABLE) + { + NVIC->CFGR = NVIC_KEY1; + } + else + { + NVIC->CFGR = NVIC_KEY1|(1<<0); + } +} + +/********************************************************************* + * @fn NVIC_INTNestCfg + * + * @brief Enable Interrupt Nesting + * + * @param NewState - DISABLE or ENABLE + * + * @return none + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE void NVIC_INTNestCfg(FunctionalState NewState) +{ + if (NewState != DISABLE) + { + NVIC->CFGR = NVIC_KEY1; + } + else + { + NVIC->CFGR = NVIC_KEY1|(1<<1); + } +} + +/********************************************************************* + * @fn __AMOADD_W + * + * @brief Atomic Add with 32bit value + * Atomically ADD 32bit value with value in memory using amoadd.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be ADDed + * + * @return return memory value + add value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOADD_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoadd.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOAND_W + * + * @brief Atomic And with 32bit value + * Atomically AND 32bit value with value in memory using amoand.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be ANDed + * + * @return return memory value & and value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOAND_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoand.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMAX_W + * + * @brief Atomic signed MAX with 32bit value + * Atomically signed max compare 32bit value with value in memory using amomax.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return return the bigger value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMAX_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amomax.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMAXU_W + * + * @brief Atomic unsigned MAX with 32bit value + * Atomically unsigned max compare 32bit value with value in memory using amomaxu.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return return the bigger value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMAXU_W(volatile uint32_t *addr, uint32_t value) +{ + uint32_t result; + + __asm volatile ("amomaxu.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMIN_W + * + * @brief Atomic signed MIN with 32bit value + * Atomically signed min compare 32bit value with value in memory using amomin.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return return the smaller value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOMIN_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amomin.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOMINU_W + * + * @brief Atomic unsigned MIN with 32bit value + * Atomically unsigned min compare 32bit value with value in memory using amominu.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be compared + * + * @return return the smaller value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOMINU_W(volatile uint32_t *addr, uint32_t value) +{ + uint32_t result; + + __asm volatile ("amominu.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOOR_W + * + * @brief Atomic OR with 32bit value + * Atomically OR 32bit value with value in memory using amoor.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be ORed + * + * @return return memory value | and value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOOR_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoor.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/********************************************************************* + * @fn __AMOSWAP_W + * + * @brief Atomically swap new 32bit value into memory using amoswap.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * newval - New value to be stored into the address + * + * @return return the original value in memory + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE uint32_t __AMOSWAP_W(volatile uint32_t *addr, uint32_t newval) +{ + uint32_t result; + + __asm volatile ("amoswap.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(newval) : "memory"); + return result; +} + +/********************************************************************* + * @fn __AMOXOR_W + * + * @brief Atomic XOR with 32bit value + * Atomically XOR 32bit value with value in memory using amoxor.d. + * + * @param addr - Address pointer to data, address need to be 4byte aligned + * value - value to be XORed + * + * @return return memory value ^ and value + */ +__attribute__( ( always_inline ) ) RV_STATIC_INLINE int32_t __AMOXOR_W(volatile int32_t *addr, int32_t value) +{ + int32_t result; + + __asm volatile ("amoxor.w %0, %2, %1" : \ + "=r"(result), "+A"(*addr) : "r"(value) : "memory"); + return *addr; +} + +/* Core_Exported_Functions */ +extern uint32_t __get_MSTATUS(void); +extern void __set_MSTATUS(uint32_t value); +extern uint32_t __get_MISA(void); +extern void __set_MISA(uint32_t value); +extern uint32_t __get_MTVEC(void); +extern void __set_MTVEC(uint32_t value); +extern uint32_t __get_MSCRATCH(void); +extern void __set_MSCRATCH(uint32_t value); +extern uint32_t __get_MEPC(void); +extern void __set_MEPC(uint32_t value); +extern uint32_t __get_MCAUSE(void); +extern void __set_MCAUSE(uint32_t value); +extern uint32_t __get_MTVAL(void); +extern void __set_MTVAL(uint32_t value); +extern uint32_t __get_MVENDORID(void); +extern uint32_t __get_MARCHID(void); +extern uint32_t __get_MIMPID(void); +extern uint32_t __get_MHARTID(void); +extern uint32_t __get_SP(void); + + +#ifdef __cplusplus +} +#endif + +#endif/* __CORE_RISCV_H__ */ + + + + + diff --git a/ch32v103_hallarray_controller/src/core/ld_ch32v10x.ld b/ch32v103_hallarray_controller/src/core/ld_ch32v10x.ld new file mode 100644 index 0000000..2cf2a5f --- /dev/null +++ b/ch32v103_hallarray_controller/src/core/ld_ch32v10x.ld @@ -0,0 +1 @@ +ENTRY( _start ) __stack_size = 2048; PROVIDE( _stack_size = __stack_size ); MEMORY { FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 64K RAM (xrw) : ORIGIN = 0x20000000, LENGTH = 20K } SECTIONS { .init : { _sinit = .; . = ALIGN(4); KEEP(*(SORT_NONE(.init))) . = ALIGN(4); _einit = .; } >FLASH AT>FLASH .vector : { *(.vector); . = ALIGN(64); } >FLASH AT>FLASH .text : { . = ALIGN(4); *(.text) *(.text.*) *(.rodata) *(.rodata*) *(.gnu.linkonce.t.*) . = ALIGN(4); } >FLASH AT>FLASH .fini : { KEEP(*(SORT_NONE(.fini))) . = ALIGN(4); } >FLASH AT>FLASH PROVIDE( _etext = . ); PROVIDE( _eitcm = . ); .preinit_array : { PROVIDE_HIDDEN (__preinit_array_start = .); KEEP (*(.preinit_array)) PROVIDE_HIDDEN (__preinit_array_end = .); } >FLASH AT>FLASH .init_array : { PROVIDE_HIDDEN (__init_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) PROVIDE_HIDDEN (__init_array_end = .); } >FLASH AT>FLASH .fini_array : { PROVIDE_HIDDEN (__fini_array_start = .); KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) PROVIDE_HIDDEN (__fini_array_end = .); } >FLASH AT>FLASH .ctors : { /* gcc uses crtbegin.o to find the start of the constructors, so we make sure it is first. Because this is a wildcard, it doesn't matter if the user does not actually link against crtbegin.o; the linker won't look for a file to match a wildcard. The wildcard also means that it doesn't matter which directory crtbegin.o is in. */ KEEP (*crtbegin.o(.ctors)) KEEP (*crtbegin?.o(.ctors)) /* We don't want to include the .ctor section from the crtend.o file until after the sorted ctors. The .ctor section from the crtend file contains the end of ctors marker and it must be last */ KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) KEEP (*(SORT(.ctors.*))) KEEP (*(.ctors)) } >FLASH AT>FLASH .dtors : { KEEP (*crtbegin.o(.dtors)) KEEP (*crtbegin?.o(.dtors)) KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) KEEP (*(SORT(.dtors.*))) KEEP (*(.dtors)) } >FLASH AT>FLASH .dalign : { . = ALIGN(4); PROVIDE(_data_vma = .); } >RAM AT>FLASH .dlalign : { . = ALIGN(4); PROVIDE(_data_lma = .); } >FLASH AT>FLASH .data : { *(.gnu.linkonce.r.*) *(.data .data.*) *(.gnu.linkonce.d.*) . = ALIGN(8); PROVIDE( __global_pointer$ = . + 0x800 ); *(.sdata .sdata.*) *(.sdata2.*) *(.gnu.linkonce.s.*) . = ALIGN(8); *(.srodata.cst16) *(.srodata.cst8) *(.srodata.cst4) *(.srodata.cst2) *(.srodata .srodata.*) . = ALIGN(4); PROVIDE( _edata = .); } >RAM AT>FLASH .bss : { . = ALIGN(4); PROVIDE( _sbss = .); *(.sbss*) *(.gnu.linkonce.sb.*) *(.bss*) *(.gnu.linkonce.b.*) *(COMMON*) . = ALIGN(4); PROVIDE( _ebss = .); } >RAM AT>FLASH PROVIDE( _end = _ebss); PROVIDE( end = . ); .stack ORIGIN(RAM) + LENGTH(RAM) - __stack_size : { PROVIDE( _heap_end = . ); . = ALIGN(4); PROVIDE(_susrstack = . ); . = . + __stack_size; PROVIDE( _eusrstack = .); } >RAM } \ No newline at end of file diff --git a/ch32v103_hallarray_controller/src/core/startup_ch32v10x.S b/ch32v103_hallarray_controller/src/core/startup_ch32v10x.S new file mode 100644 index 0000000..b8ed2a0 --- /dev/null +++ b/ch32v103_hallarray_controller/src/core/startup_ch32v10x.S @@ -0,0 +1,237 @@ +;/********************************** (C) COPYRIGHT ******************************* +;* File Name : startup_ch32v10x.s +;* Author : WCH +;* Version : V1.0.1 +;* Date : 2024/01/11 +;* Description : CH32V10x vector table for eclipse toolchain. +;********************************************************************************* +;* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +;* Attention: This software (modified or not) and binary are used for +;* microcontroller manufactured by Nanjing Qinheng Microelectronics. +;*******************************************************************************/ + + .section .init,"ax",@progbits + .global _start + .align 1 +_start: + j handle_reset + .word 0x00000013 + .word 0x00000013 + .word 0x00000013 + .word 0x00000013 + .word 0x00000013 + .word 0x00000013 + .word 0x00000013 + .word 0x00000013 + .word 0x00000013 + .word 0x00000013 + .word 0x00000013 + .word 0x00000013 + .word 0x00100073 + + .section .vector,"ax",@progbits + .align 1 +_vector_base: + .option norvc; + j _start + .word 0 + j NMI_Handler /* NMI Handler */ + j HardFault_Handler /* Hard Fault Handler */ + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + j SysTick_Handler /* SysTick Handler */ + .word 0 + j SW_Handler /* SW Handler */ + .word 0 + /* External Interrupts */ + j WWDG_IRQHandler /* Window Watchdog */ + j PVD_IRQHandler /* PVD through EXTI Line detect */ + j TAMPER_IRQHandler /* TAMPER */ + j RTC_IRQHandler /* RTC */ + j FLASH_IRQHandler /* Flash */ + j RCC_IRQHandler /* RCC */ + j EXTI0_IRQHandler /* EXTI Line 0 */ + j EXTI1_IRQHandler /* EXTI Line 1 */ + j EXTI2_IRQHandler /* EXTI Line 2 */ + j EXTI3_IRQHandler /* EXTI Line 3 */ + j EXTI4_IRQHandler /* EXTI Line 4 */ + j DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + j DMA1_Channel2_IRQHandler /* DMA1 Channel 2 */ + j DMA1_Channel3_IRQHandler /* DMA1 Channel 3 */ + j DMA1_Channel4_IRQHandler /* DMA1 Channel 4 */ + j DMA1_Channel5_IRQHandler /* DMA1 Channel 5 */ + j DMA1_Channel6_IRQHandler /* DMA1 Channel 6 */ + j DMA1_Channel7_IRQHandler /* DMA1 Channel 7 */ + j ADC1_2_IRQHandler /* ADC1_2 */ + .word 0 + .word 0 + .word 0 + .word 0 + j EXTI9_5_IRQHandler /* EXTI Line 9..5 */ + j TIM1_BRK_IRQHandler /* TIM1 Break */ + j TIM1_UP_IRQHandler /* TIM1 Update */ + j TIM1_TRG_COM_IRQHandler /* TIM1 Trigger and Commutation */ + j TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + j TIM2_IRQHandler /* TIM2 */ + j TIM3_IRQHandler /* TIM3 */ + j TIM4_IRQHandler /* TIM4 */ + j I2C1_EV_IRQHandler /* I2C1 Event */ + j I2C1_ER_IRQHandler /* I2C1 Error */ + j I2C2_EV_IRQHandler /* I2C2 Event */ + j I2C2_ER_IRQHandler /* I2C2 Error */ + j SPI1_IRQHandler /* SPI1 */ + j SPI2_IRQHandler /* SPI2 */ + j USART1_IRQHandler /* USART1 */ + j USART2_IRQHandler /* USART2 */ + j USART3_IRQHandler /* USART3 */ + j EXTI15_10_IRQHandler /* EXTI Line 15..10 */ + j RTCAlarm_IRQHandler /* RTC Alarm through EXTI Line */ + j USBWakeUp_IRQHandler /* USB Wakeup from suspend */ + j USBFS_IRQHandler /* USBFS */ + + .option rvc; + .section .text.vector_handler, "ax", @progbits + .weak NMI_Handler + .weak HardFault_Handler + .weak SysTick_Handler + .weak SW_Handler + .weak WWDG_IRQHandler + .weak PVD_IRQHandler + .weak TAMPER_IRQHandler + .weak RTC_IRQHandler + .weak FLASH_IRQHandler + .weak RCC_IRQHandler + .weak EXTI0_IRQHandler + .weak EXTI1_IRQHandler + .weak EXTI2_IRQHandler + .weak EXTI3_IRQHandler + .weak EXTI4_IRQHandler + .weak DMA1_Channel1_IRQHandler + .weak DMA1_Channel2_IRQHandler + .weak DMA1_Channel3_IRQHandler + .weak DMA1_Channel4_IRQHandler + .weak DMA1_Channel5_IRQHandler + .weak DMA1_Channel6_IRQHandler + .weak DMA1_Channel7_IRQHandler + .weak ADC1_2_IRQHandler + .weak EXTI9_5_IRQHandler + .weak TIM1_BRK_IRQHandler + .weak TIM1_UP_IRQHandler + .weak TIM1_TRG_COM_IRQHandler + .weak TIM1_CC_IRQHandler + .weak TIM2_IRQHandler + .weak TIM3_IRQHandler + .weak TIM4_IRQHandler + .weak I2C1_EV_IRQHandler + .weak I2C1_ER_IRQHandler + .weak I2C2_EV_IRQHandler + .weak I2C2_ER_IRQHandler + .weak SPI1_IRQHandler + .weak SPI2_IRQHandler + .weak USART1_IRQHandler + .weak USART2_IRQHandler + .weak USART3_IRQHandler + .weak EXTI15_10_IRQHandler + .weak RTCAlarm_IRQHandler + .weak USBWakeUp_IRQHandler + .weak USBFS_IRQHandler + +NMI_Handler: +HardFault_Handler: +SysTick_Handler: +SW_Handler: +WWDG_IRQHandler: +PVD_IRQHandler: +TAMPER_IRQHandler: +RTC_IRQHandler: +FLASH_IRQHandler: +RCC_IRQHandler: +EXTI0_IRQHandler: +EXTI1_IRQHandler: +EXTI2_IRQHandler: +EXTI3_IRQHandler: +EXTI4_IRQHandler: +DMA1_Channel1_IRQHandler: +DMA1_Channel2_IRQHandler: +DMA1_Channel3_IRQHandler: +DMA1_Channel4_IRQHandler: +DMA1_Channel5_IRQHandler: +DMA1_Channel6_IRQHandler: +DMA1_Channel7_IRQHandler: +ADC1_2_IRQHandler: +EXTI9_5_IRQHandler: +TIM1_BRK_IRQHandler: +TIM1_UP_IRQHandler: +TIM1_TRG_COM_IRQHandler: +TIM1_CC_IRQHandler: +TIM2_IRQHandler: +TIM3_IRQHandler: +TIM4_IRQHandler: +I2C1_EV_IRQHandler: +I2C1_ER_IRQHandler: +I2C2_EV_IRQHandler: +I2C2_ER_IRQHandler: +SPI1_IRQHandler: +SPI2_IRQHandler: +USART1_IRQHandler: +USART2_IRQHandler: +USART3_IRQHandler: +EXTI15_10_IRQHandler: +RTCAlarm_IRQHandler: +USBWakeUp_IRQHandler: +USBFS_IRQHandler: +1: + j 1b + + .section .text.handle_reset,"ax",@progbits + .weak handle_reset + .align 1 +handle_reset: +.option push +.option norelax + la gp, __global_pointer$ +.option pop +1: + la sp, _eusrstack +2: +/* Load data section from flash to RAM */ + la a0, _data_lma + la a1, _data_vma + la a2, _edata + bgeu a1, a2, 2f +1: + lw t0, (a0) + sw t0, (a1) + addi a0, a0, 4 + addi a1, a1, 4 + bltu a1, a2, 1b +2: +/* Clear bss section */ + la a0, _sbss + la a1, _ebss + bgeu a0, a1, 2f +1: + sw zero, (a0) + addi a0, a0, 4 + bltu a0, a1, 1b +2: +/* Enable global interrupt and configure privileged mode */ + li t0, 0x88 + csrw mstatus, t0 +/* Configure entry address mode */ + la t0, _vector_base + ori t0, t0, 1 + csrw mtvec, t0 + + jal SystemInit + la t0, main + csrw mepc, t0 + mret + + diff --git a/ch32v103_hallarray_controller/src/periph/ch32v10x.h b/ch32v103_hallarray_controller/src/periph/ch32v10x.h new file mode 100644 index 0000000..db8565f --- /dev/null +++ b/ch32v103_hallarray_controller/src/periph/ch32v10x.h @@ -0,0 +1,3209 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x.h + * Author : WCH + * Version : V1.0.1 + * Date : 2025/01/02 + * Description : CH32V10x Device Peripheral Access Layer Header File. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V10x_H +#define __CH32V10x_H + +#ifdef __cplusplus +extern "C" { +#endif + +#define __MPU_PRESENT 0 /* Other CH32 devices does not provide an MPU */ +#define __Vendor_SysTickConfig 0 /* Set to 1 if different SysTick Config is used */ + +#ifndef HSE_VALUE +#define HSE_VALUE ((uint32_t)8000000) /* Value of the External oscillator in Hz */ +#endif + +/* In the following line adjust the External High Speed oscillator (HSE) Startup Timeout value */ +#define HSE_STARTUP_TIMEOUT ((uint16_t)0x500) /* Time out for HSE start up */ + +#define HSI_VALUE ((uint32_t)8000000) /* Value of the Internal oscillator in Hz */ + +/* CH32V10x Standard Peripheral Library version number */ +#define __CH32V10x_STDPERIPH_VERSION_MAIN (0x02) /* [15:8] main version */ +#define __CH32V10x_STDPERIPH_VERSION_SUB (0x07) /* [7:0] sub version */ +#define __CH32V10x_STDPERIPH_VERSION ( (__CH32V10x_STDPERIPH_VERSION_MAIN << 8)\ + |(__CH32V10x_STDPERIPH_VERSION_SUB << 0)) + +/* Interrupt Number Definition, according to the selected device */ +typedef enum IRQn +{ + /****** RISC-V Processor Exceptions Numbers *******************************************************/ + NonMaskableInt_IRQn = 2, /* 2 Non Maskable Interrupt */ + EXC_IRQn = 3, /* 4 Exception Interrupt */ + SysTick_IRQn = 12, /* 12 System timer Interrupt */ + Software_IRQn = 14, /* 14 software Interrupt */ + + /****** RISC-V specific Interrupt Numbers *********************************************************/ + WWDG_IRQn = 16, /* Window WatchDog Interrupt */ + PVD_IRQn = 17, /* PVD through EXTI Line detection Interrupt */ + TAMPER_IRQn = 18, /* Tamper Interrupt */ + RTC_IRQn = 19, /* RTC global Interrupt */ + FLASH_IRQn = 20, /* FLASH global Interrupt */ + RCC_IRQn = 21, /* RCC global Interrupt */ + EXTI0_IRQn = 22, /* EXTI Line0 Interrupt */ + EXTI1_IRQn = 23, /* EXTI Line1 Interrupt */ + EXTI2_IRQn = 24, /* EXTI Line2 Interrupt */ + EXTI3_IRQn = 25, /* EXTI Line3 Interrupt */ + EXTI4_IRQn = 26, /* EXTI Line4 Interrupt */ + DMA1_Channel1_IRQn = 27, /* DMA1 Channel 1 global Interrupt */ + DMA1_Channel2_IRQn = 28, /* DMA1 Channel 2 global Interrupt */ + DMA1_Channel3_IRQn = 29, /* DMA1 Channel 3 global Interrupt */ + DMA1_Channel4_IRQn = 30, /* DMA1 Channel 4 global Interrupt */ + DMA1_Channel5_IRQn = 31, /* DMA1 Channel 5 global Interrupt */ + DMA1_Channel6_IRQn = 32, /* DMA1 Channel 6 global Interrupt */ + DMA1_Channel7_IRQn = 33, /* DMA1 Channel 7 global Interrupt */ + ADC_IRQn = 34, /* ADC1 global Interrupt */ + EXTI9_5_IRQn = 39, /* External Line[9:5] Interrupts */ + TIM1_BRK_IRQn = 40, /* TIM1 Break Interrupt */ + TIM1_UP_IRQn = 41, /* TIM1 Update Interrupt */ + TIM1_TRG_COM_IRQn = 42, /* TIM1 Trigger and Commutation Interrupt */ + TIM1_CC_IRQn = 43, /* TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 44, /* TIM2 global Interrupt */ + TIM3_IRQn = 45, /* TIM3 global Interrupt */ + TIM4_IRQn = 46, /* TIM4 global Interrupt */ + I2C1_EV_IRQn = 47, /* I2C1 Event Interrupt */ + I2C1_ER_IRQn = 48, /* I2C1 Error Interrupt */ + I2C2_EV_IRQn = 49, /* I2C2 Event Interrupt */ + I2C2_ER_IRQn = 50, /* I2C2 Error Interrupt */ + SPI1_IRQn = 51, /* SPI1 global Interrupt */ + SPI2_IRQn = 52, /* SPI2 global Interrupt */ + USART1_IRQn = 53, /* USART1 global Interrupt */ + USART2_IRQn = 54, /* USART2 global Interrupt */ + USART3_IRQn = 55, /* USART3 global Interrupt */ + EXTI15_10_IRQn = 56, /* External Line[15:10] Interrupts */ + RTCAlarm_IRQn = 57, /* RTC Alarm through EXTI Line Interrupt */ + USBWakeUp_IRQn = 58, /* USB WakeUp from suspend through EXTI Line Interrupt */ + USBFS_IRQn = 59, /* USBFS Interrupt */ + +} IRQn_Type; + +#define USBHD_IRQn USBFS_IRQn +#define USBHD_IRQHandler USBFS_IRQHandler +#define SysTicK_IRQn SysTick_IRQn + +#define HardFault_IRQn EXC_IRQn +#define ADC1_2_IRQn ADC_IRQn + +#include +#include "core_riscv.h" +#include "system_ch32v10x.h" + +/* Standard Peripheral Library old definitions (maintained for legacy purpose) */ +#define HSI_Value HSI_VALUE +#define HSE_Value HSE_VALUE +#define HSEStartUp_TimeOut HSE_STARTUP_TIMEOUT + +/* Analog to Digital Converter */ +typedef struct +{ + __IO uint32_t STATR; + __IO uint32_t CTLR1; + __IO uint32_t CTLR2; + __IO uint32_t SAMPTR1; + __IO uint32_t SAMPTR2; + __IO uint32_t IOFR1; + __IO uint32_t IOFR2; + __IO uint32_t IOFR3; + __IO uint32_t IOFR4; + __IO uint32_t WDHTR; + __IO uint32_t WDLTR; + __IO uint32_t RSQR1; + __IO uint32_t RSQR2; + __IO uint32_t RSQR3; + __IO uint32_t ISQR; + __IO uint32_t IDATAR1; + __IO uint32_t IDATAR2; + __IO uint32_t IDATAR3; + __IO uint32_t IDATAR4; + __IO uint32_t RDATAR; +} ADC_TypeDef; + +/* Backup Registers */ +typedef struct +{ + uint32_t RESERVED0; + __IO uint16_t DATAR1; + uint16_t RESERVED1; + __IO uint16_t DATAR2; + uint16_t RESERVED2; + __IO uint16_t DATAR3; + uint16_t RESERVED3; + __IO uint16_t DATAR4; + uint16_t RESERVED4; + __IO uint16_t DATAR5; + uint16_t RESERVED5; + __IO uint16_t DATAR6; + uint16_t RESERVED6; + __IO uint16_t DATAR7; + uint16_t RESERVED7; + __IO uint16_t DATAR8; + uint16_t RESERVED8; + __IO uint16_t DATAR9; + uint16_t RESERVED9; + __IO uint16_t DATAR10; + uint16_t RESERVED10; + __IO uint16_t OCTLR; + uint16_t RESERVED11; + __IO uint16_t TPCTLR; + uint16_t RESERVED12; + __IO uint16_t TPCSR; + uint16_t RESERVED13[5]; + __IO uint16_t DATAR11; + uint16_t RESERVED14; + __IO uint16_t DATAR12; + uint16_t RESERVED15; + __IO uint16_t DATAR13; + uint16_t RESERVED16; + __IO uint16_t DATAR14; + uint16_t RESERVED17; + __IO uint16_t DATAR15; + uint16_t RESERVED18; + __IO uint16_t DATAR16; + uint16_t RESERVED19; + __IO uint16_t DATAR17; + uint16_t RESERVED20; + __IO uint16_t DATAR18; + uint16_t RESERVED21; + __IO uint16_t DATAR19; + uint16_t RESERVED22; + __IO uint16_t DATAR20; + uint16_t RESERVED23; + __IO uint16_t DATAR21; + uint16_t RESERVED24; + __IO uint16_t DATAR22; + uint16_t RESERVED25; + __IO uint16_t DATAR23; + uint16_t RESERVED26; + __IO uint16_t DATAR24; + uint16_t RESERVED27; + __IO uint16_t DATAR25; + uint16_t RESERVED28; + __IO uint16_t DATAR26; + uint16_t RESERVED29; + __IO uint16_t DATAR27; + uint16_t RESERVED30; + __IO uint16_t DATAR28; + uint16_t RESERVED31; + __IO uint16_t DATAR29; + uint16_t RESERVED32; + __IO uint16_t DATAR30; + uint16_t RESERVED33; + __IO uint16_t DATAR31; + uint16_t RESERVED34; + __IO uint16_t DATAR32; + uint16_t RESERVED35; + __IO uint16_t DATAR33; + uint16_t RESERVED36; + __IO uint16_t DATAR34; + uint16_t RESERVED37; + __IO uint16_t DATAR35; + uint16_t RESERVED38; + __IO uint16_t DATAR36; + uint16_t RESERVED39; + __IO uint16_t DATAR37; + uint16_t RESERVED40; + __IO uint16_t DATAR38; + uint16_t RESERVED41; + __IO uint16_t DATAR39; + uint16_t RESERVED42; + __IO uint16_t DATAR40; + uint16_t RESERVED43; + __IO uint16_t DATAR41; + uint16_t RESERVED44; + __IO uint16_t DATAR42; + uint16_t RESERVED45; +} BKP_TypeDef; + +/* CRC Calculation Unit */ +typedef struct +{ + __IO uint32_t DATAR; + __IO uint8_t IDATAR; + uint8_t RESERVED0; + uint16_t RESERVED1; + __IO uint32_t CTLR; +} CRC_TypeDef; + +/* Digital to Analog Converter */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t SWTR; + __IO uint32_t R12BDHR1; + __IO uint32_t L12BDHR1; + __IO uint32_t R8BDHR1; + __IO uint32_t R12BDHR2; + __IO uint32_t L12BDHR2; + __IO uint32_t R8BDHR2; + __IO uint32_t RD12BDHR; + __IO uint32_t LD12BDHR; + __IO uint32_t RD8BDHR; + __IO uint32_t DOR1; + __IO uint32_t DOR2; +} DAC_TypeDef; + +/* Debug MCU */ +typedef struct +{ + __IO uint32_t CFGR0; + __IO uint32_t CFGR1; +} DBGMCU_TypeDef; + +/* DMA Controller */ +typedef struct +{ + __IO uint32_t CFGR; + __IO uint32_t CNTR; + __IO uint32_t PADDR; + __IO uint32_t MADDR; +} DMA_Channel_TypeDef; + +typedef struct +{ + __IO uint32_t INTFR; + __IO uint32_t INTFCR; +} DMA_TypeDef; + +/* External Interrupt/Event Controller */ +typedef struct +{ + __IO uint32_t INTENR; + __IO uint32_t EVENR; + __IO uint32_t RTENR; + __IO uint32_t FTENR; + __IO uint32_t SWIEVR; + __IO uint32_t INTFR; +} EXTI_TypeDef; + +/* FLASH Registers */ +typedef struct +{ + __IO uint32_t ACTLR; + __IO uint32_t KEYR; + __IO uint32_t OBKEYR; + __IO uint32_t STATR; + __IO uint32_t CTLR; + __IO uint32_t ADDR; + __IO uint32_t RESERVED; + __IO uint32_t OBR; + __IO uint32_t WPR; + __IO uint32_t MODEKEYR; +} FLASH_TypeDef; + +/* Option Bytes Registers */ +typedef struct +{ + __IO uint16_t RDPR; + __IO uint16_t USER; + __IO uint16_t Data0; + __IO uint16_t Data1; + __IO uint16_t WRPR0; + __IO uint16_t WRPR1; + __IO uint16_t WRPR2; + __IO uint16_t WRPR3; +} OB_TypeDef; + +/* General Purpose I/O */ +typedef struct +{ + __IO uint32_t CFGLR; + __IO uint32_t CFGHR; + __IO uint32_t INDR; + __IO uint32_t OUTDR; + __IO uint32_t BSHR; + __IO uint32_t BCR; + __IO uint32_t LCKR; +} GPIO_TypeDef; + +/* Alternate Function I/O */ +typedef struct +{ + __IO uint32_t ECR; + __IO uint32_t PCFR1; + __IO uint32_t EXTICR[4]; + uint32_t RESERVED0; + __IO uint32_t PCFR2; +} AFIO_TypeDef; + +/* Inter Integrated Circuit Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t OADDR1; + uint16_t RESERVED2; + __IO uint16_t OADDR2; + uint16_t RESERVED3; + __IO uint16_t DATAR; + uint16_t RESERVED4; + __IO uint16_t STAR1; + uint16_t RESERVED5; + __IO uint16_t STAR2; + uint16_t RESERVED6; + __IO uint16_t CKCFGR; + uint16_t RESERVED7; + __IO uint16_t RTR; + uint16_t RESERVED8; +} I2C_TypeDef; + +/* Independent WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t PSCR; + __IO uint32_t RLDR; + __IO uint32_t STATR; +} IWDG_TypeDef; + +/* Power Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CSR; +} PWR_TypeDef; + +/* Reset and Clock Control */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR0; + __IO uint32_t INTR; + __IO uint32_t APB2PRSTR; + __IO uint32_t APB1PRSTR; + __IO uint32_t AHBPCENR; + __IO uint32_t APB2PCENR; + __IO uint32_t APB1PCENR; + __IO uint32_t BDCTLR; + __IO uint32_t RSTSCKR; +} RCC_TypeDef; + +/* Real-Time Clock */ +typedef struct +{ + __IO uint16_t CTLRH; + uint16_t RESERVED0; + __IO uint16_t CTLRL; + uint16_t RESERVED1; + __IO uint16_t PSCRH; + uint16_t RESERVED2; + __IO uint16_t PSCRL; + uint16_t RESERVED3; + __IO uint16_t DIVH; + uint16_t RESERVED4; + __IO uint16_t DIVL; + uint16_t RESERVED5; + __IO uint16_t CNTH; + uint16_t RESERVED6; + __IO uint16_t CNTL; + uint16_t RESERVED7; + __IO uint16_t ALRMH; + uint16_t RESERVED8; + __IO uint16_t ALRML; + uint16_t RESERVED9; +} RTC_TypeDef; + +/* Serial Peripheral Interface */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t STATR; + uint16_t RESERVED2; + __IO uint16_t DATAR; + uint16_t RESERVED3; + __IO uint16_t CRCR; + uint16_t RESERVED4; + __IO uint16_t RCRCR; + uint16_t RESERVED5; + __IO uint16_t TCRCR; + uint16_t RESERVED6; + uint32_t RESERVED7; + uint32_t RESERVED8; + __IO uint16_t HSCR; + uint16_t RESERVED9; +} SPI_TypeDef; + +/* TIM */ +typedef struct +{ + __IO uint16_t CTLR1; + uint16_t RESERVED0; + __IO uint16_t CTLR2; + uint16_t RESERVED1; + __IO uint16_t SMCFGR; + uint16_t RESERVED2; + __IO uint16_t DMAINTENR; + uint16_t RESERVED3; + __IO uint16_t INTFR; + uint16_t RESERVED4; + __IO uint16_t SWEVGR; + uint16_t RESERVED5; + __IO uint16_t CHCTLR1; + uint16_t RESERVED6; + __IO uint16_t CHCTLR2; + uint16_t RESERVED7; + __IO uint16_t CCER; + uint16_t RESERVED8; + __IO uint16_t CNT; + uint16_t RESERVED9; + __IO uint16_t PSC; + uint16_t RESERVED10; + __IO uint16_t ATRLR; + uint16_t RESERVED11; + __IO uint16_t RPTCR; + uint16_t RESERVED12; + __IO uint16_t CH1CVR; + uint16_t RESERVED13; + __IO uint16_t CH2CVR; + uint16_t RESERVED14; + __IO uint16_t CH3CVR; + uint16_t RESERVED15; + __IO uint16_t CH4CVR; + uint16_t RESERVED16; + __IO uint16_t BDTR; + uint16_t RESERVED17; + __IO uint16_t DMACFGR; + uint16_t RESERVED18; + __IO uint16_t DMAADR; + uint16_t RESERVED19; +} TIM_TypeDef; + +/* Universal Synchronous Asynchronous Receiver Transmitter */ +typedef struct +{ + __IO uint16_t STATR; + uint16_t RESERVED0; + __IO uint16_t DATAR; + uint16_t RESERVED1; + __IO uint16_t BRR; + uint16_t RESERVED2; + __IO uint16_t CTLR1; + uint16_t RESERVED3; + __IO uint16_t CTLR2; + uint16_t RESERVED4; + __IO uint16_t CTLR3; + uint16_t RESERVED5; + __IO uint16_t GPR; + uint16_t RESERVED6; +} USART_TypeDef; + +/* Window WatchDog */ +typedef struct +{ + __IO uint32_t CTLR; + __IO uint32_t CFGR; + __IO uint32_t STATR; +} WWDG_TypeDef; + +/* Enhanced Registers */ +typedef struct +{ + __IO uint32_t EXTEN_CTR; +} EXTEN_TypeDef; + +/* Peripheral memory map */ +#define FLASH_BASE ((uint32_t)0x08000000) /* FLASH base address in the alias region */ +#define SRAM_BASE ((uint32_t)0x20000000) /* SRAM base address in the alias region */ +#define PERIPH_BASE ((uint32_t)0x40000000) /* Peripheral base address in the alias region */ + +#define APB1PERIPH_BASE (PERIPH_BASE) +#define APB2PERIPH_BASE (PERIPH_BASE + 0x10000) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x20000) + +#define TIM2_BASE (APB1PERIPH_BASE + 0x0000) +#define TIM3_BASE (APB1PERIPH_BASE + 0x0400) +#define TIM4_BASE (APB1PERIPH_BASE + 0x0800) +#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00) +#define TIM6_BASE (APB1PERIPH_BASE + 0x1000) +#define TIM7_BASE (APB1PERIPH_BASE + 0x1400) +#define TIM12_BASE (APB1PERIPH_BASE + 0x1800) +#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00) +#define TIM14_BASE (APB1PERIPH_BASE + 0x2000) +#define RTC_BASE (APB1PERIPH_BASE + 0x2800) +#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) +#define IWDG_BASE (APB1PERIPH_BASE + 0x3000) +#define SPI2_BASE (APB1PERIPH_BASE + 0x3800) +#define USART2_BASE (APB1PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1PERIPH_BASE + 0x4800) +#define UART4_BASE (APB1PERIPH_BASE + 0x4C00) +#define UART5_BASE (APB1PERIPH_BASE + 0x5000) +#define I2C1_BASE (APB1PERIPH_BASE + 0x5400) +#define I2C2_BASE (APB1PERIPH_BASE + 0x5800) +#define BKP_BASE (APB1PERIPH_BASE + 0x6C00) +#define PWR_BASE (APB1PERIPH_BASE + 0x7000) +#define DAC_BASE (APB1PERIPH_BASE + 0x7400) + +#define AFIO_BASE (APB2PERIPH_BASE + 0x0000) +#define EXTI_BASE (APB2PERIPH_BASE + 0x0400) +#define GPIOA_BASE (APB2PERIPH_BASE + 0x0800) +#define GPIOB_BASE (APB2PERIPH_BASE + 0x0C00) +#define GPIOC_BASE (APB2PERIPH_BASE + 0x1000) +#define GPIOD_BASE (APB2PERIPH_BASE + 0x1400) +#define GPIOE_BASE (APB2PERIPH_BASE + 0x1800) +#define GPIOF_BASE (APB2PERIPH_BASE + 0x1C00) +#define GPIOG_BASE (APB2PERIPH_BASE + 0x2000) +#define ADC1_BASE (APB2PERIPH_BASE + 0x2400) +#define ADC2_BASE (APB2PERIPH_BASE + 0x2800) +#define TIM1_BASE (APB2PERIPH_BASE + 0x2C00) +#define SPI1_BASE (APB2PERIPH_BASE + 0x3000) +#define TIM8_BASE (APB2PERIPH_BASE + 0x3400) +#define USART1_BASE (APB2PERIPH_BASE + 0x3800) +#define ADC3_BASE (APB2PERIPH_BASE + 0x3C00) +#define TIM15_BASE (APB2PERIPH_BASE + 0x4000) +#define TIM16_BASE (APB2PERIPH_BASE + 0x4400) +#define TIM17_BASE (APB2PERIPH_BASE + 0x4800) +#define TIM9_BASE (APB2PERIPH_BASE + 0x4C00) +#define TIM10_BASE (APB2PERIPH_BASE + 0x5000) +#define TIM11_BASE (APB2PERIPH_BASE + 0x5400) + +#define DMA1_BASE (AHBPERIPH_BASE + 0x0000) +#define DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x0008) +#define DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x001C) +#define DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x0030) +#define DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x0044) +#define DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x0058) +#define DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x006C) +#define DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x0080) +#define DMA2_BASE (AHBPERIPH_BASE + 0x0400) +#define DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x0408) +#define DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x041C) +#define DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x0430) +#define DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x0444) +#define DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x0458) +#define RCC_BASE (AHBPERIPH_BASE + 0x1000) +#define CRC_BASE (AHBPERIPH_BASE + 0x3000) + +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x2000) /* Flash registers base address */ +#define OB_BASE ((uint32_t)0x1FFFF800) /* Flash Option Bytes base address */ +#define DBGMCU_BASE ((uint32_t)0xE000D000) +#define EXTEN_BASE ((uint32_t)0x40023800) + +/* Peripheral declaration */ +#define TIM2 ((TIM_TypeDef *)TIM2_BASE) +#define TIM3 ((TIM_TypeDef *)TIM3_BASE) +#define TIM4 ((TIM_TypeDef *)TIM4_BASE) +#define TIM5 ((TIM_TypeDef *)TIM5_BASE) +#define TIM6 ((TIM_TypeDef *)TIM6_BASE) +#define TIM7 ((TIM_TypeDef *)TIM7_BASE) +#define TIM12 ((TIM_TypeDef *)TIM12_BASE) +#define TIM13 ((TIM_TypeDef *)TIM13_BASE) +#define TIM14 ((TIM_TypeDef *)TIM14_BASE) +#define RTC ((RTC_TypeDef *)RTC_BASE) +#define WWDG ((WWDG_TypeDef *)WWDG_BASE) +#define IWDG ((IWDG_TypeDef *)IWDG_BASE) +#define SPI2 ((SPI_TypeDef *)SPI2_BASE) +#define USART2 ((USART_TypeDef *)USART2_BASE) +#define USART3 ((USART_TypeDef *)USART3_BASE) +#define UART4 ((USART_TypeDef *)UART4_BASE) +#define UART5 ((USART_TypeDef *)UART5_BASE) +#define I2C1 ((I2C_TypeDef *)I2C1_BASE) +#define I2C2 ((I2C_TypeDef *)I2C2_BASE) +#define BKP ((BKP_TypeDef *)BKP_BASE) +#define PWR ((PWR_TypeDef *)PWR_BASE) +#define DAC ((DAC_TypeDef *)DAC_BASE) +#define AFIO ((AFIO_TypeDef *)AFIO_BASE) +#define EXTI ((EXTI_TypeDef *)EXTI_BASE) +#define GPIOA ((GPIO_TypeDef *)GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *)GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *)GPIOC_BASE) +#define GPIOD ((GPIO_TypeDef *)GPIOD_BASE) +#define GPIOE ((GPIO_TypeDef *)GPIOE_BASE) +#define GPIOF ((GPIO_TypeDef *)GPIOF_BASE) +#define GPIOG ((GPIO_TypeDef *)GPIOG_BASE) +#define ADC1 ((ADC_TypeDef *)ADC1_BASE) +#define ADC2 ((ADC_TypeDef *)ADC2_BASE) +#define TIM1 ((TIM_TypeDef *)TIM1_BASE) +#define SPI1 ((SPI_TypeDef *)SPI1_BASE) +#define TIM8 ((TIM_TypeDef *)TIM8_BASE) +#define USART1 ((USART_TypeDef *)USART1_BASE) +#define ADC3 ((ADC_TypeDef *)ADC3_BASE) +#define TIM15 ((TIM_TypeDef *)TIM15_BASE) +#define TIM16 ((TIM_TypeDef *)TIM16_BASE) +#define TIM17 ((TIM_TypeDef *)TIM17_BASE) +#define TIM9 ((TIM_TypeDef *)TIM9_BASE) +#define TIM10 ((TIM_TypeDef *)TIM10_BASE) +#define TIM11 ((TIM_TypeDef *)TIM11_BASE) +#define DMA1 ((DMA_TypeDef *)DMA1_BASE) +#define DMA2 ((DMA_TypeDef *)DMA2_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE) +#define DMA2_Channel1 ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE) +#define DMA2_Channel2 ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE) +#define DMA2_Channel3 ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE) +#define DMA2_Channel4 ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE) +#define DMA2_Channel5 ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE) +#define RCC ((RCC_TypeDef *)RCC_BASE) +#define CRC ((CRC_TypeDef *)CRC_BASE) +#define FLASH ((FLASH_TypeDef *)FLASH_R_BASE) +#define OB ((OB_TypeDef *)OB_BASE) +#define DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE) +#define EXTEN ((EXTEN_TypeDef *)EXTEN_BASE) + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* Analog to Digital Converter */ +/******************************************************************************/ + +/******************** Bit definition for ADC_STATR register ********************/ +#define ADC_AWD ((uint8_t)0x01) /* Analog watchdog flag */ +#define ADC_EOC ((uint8_t)0x02) /* End of conversion */ +#define ADC_JEOC ((uint8_t)0x04) /* Injected channel end of conversion */ +#define ADC_JSTRT ((uint8_t)0x08) /* Injected channel Start flag */ +#define ADC_STRT ((uint8_t)0x10) /* Regular channel Start flag */ + +/******************* Bit definition for ADC_CTLR1 register ********************/ +#define ADC_AWDCH ((uint32_t)0x0000001F) /* AWDCH[4:0] bits (Analog watchdog channel select bits) */ +#define ADC_AWDCH_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_AWDCH_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_AWDCH_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_AWDCH_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_AWDCH_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_EOCIE ((uint32_t)0x00000020) /* Interrupt enable for EOC */ +#define ADC_AWDIE ((uint32_t)0x00000040) /* Analog Watchdog interrupt enable */ +#define ADC_JEOCIE ((uint32_t)0x00000080) /* Interrupt enable for injected channels */ +#define ADC_SCAN ((uint32_t)0x00000100) /* Scan mode */ +#define ADC_AWDSGL ((uint32_t)0x00000200) /* Enable the watchdog on a single channel in scan mode */ +#define ADC_JAUTO ((uint32_t)0x00000400) /* Automatic injected group conversion */ +#define ADC_DISCEN ((uint32_t)0x00000800) /* Discontinuous mode on regular channels */ +#define ADC_JDISCEN ((uint32_t)0x00001000) /* Discontinuous mode on injected channels */ + +#define ADC_DISCNUM ((uint32_t)0x0000E000) /* DISCNUM[2:0] bits (Discontinuous mode channel count) */ +#define ADC_DISCNUM_0 ((uint32_t)0x00002000) /* Bit 0 */ +#define ADC_DISCNUM_1 ((uint32_t)0x00004000) /* Bit 1 */ +#define ADC_DISCNUM_2 ((uint32_t)0x00008000) /* Bit 2 */ + +#define ADC_DUALMOD ((uint32_t)0x000F0000) /* DUALMOD[3:0] bits (Dual mode selection) */ +#define ADC_DUALMOD_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define ADC_DUALMOD_1 ((uint32_t)0x00020000) /* Bit 1 */ +#define ADC_DUALMOD_2 ((uint32_t)0x00040000) /* Bit 2 */ +#define ADC_DUALMOD_3 ((uint32_t)0x00080000) /* Bit 3 */ + +#define ADC_JAWDEN ((uint32_t)0x00400000) /* Analog watchdog enable on injected channels */ +#define ADC_AWDEN ((uint32_t)0x00800000) /* Analog watchdog enable on regular channels */ + +/******************* Bit definition for ADC_CTLR2 register ********************/ +#define ADC_ADON ((uint32_t)0x00000001) /* A/D Converter ON / OFF */ +#define ADC_CONT ((uint32_t)0x00000002) /* Continuous Conversion */ +#define ADC_CAL ((uint32_t)0x00000004) /* A/D Calibration */ +#define ADC_RSTCAL ((uint32_t)0x00000008) /* Reset Calibration */ +#define ADC_DMA ((uint32_t)0x00000100) /* Direct Memory access mode */ +#define ADC_ALIGN ((uint32_t)0x00000800) /* Data Alignment */ + +#define ADC_JEXTSEL ((uint32_t)0x00007000) /* JEXTSEL[2:0] bits (External event select for injected group) */ +#define ADC_JEXTSEL_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_JEXTSEL_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_JEXTSEL_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_JEXTTRIG ((uint32_t)0x00008000) /* External Trigger Conversion mode for injected channels */ + +#define ADC_EXTSEL ((uint32_t)0x000E0000) /* EXTSEL[2:0] bits (External Event Select for regular group) */ +#define ADC_EXTSEL_0 ((uint32_t)0x00020000) /* Bit 0 */ +#define ADC_EXTSEL_1 ((uint32_t)0x00040000) /* Bit 1 */ +#define ADC_EXTSEL_2 ((uint32_t)0x00080000) /* Bit 2 */ + +#define ADC_EXTTRIG ((uint32_t)0x00100000) /* External Trigger Conversion mode for regular channels */ +#define ADC_JSWSTART ((uint32_t)0x00200000) /* Start Conversion of injected channels */ +#define ADC_SWSTART ((uint32_t)0x00400000) /* Start Conversion of regular channels */ +#define ADC_TSVREFE ((uint32_t)0x00800000) /* Temperature Sensor and VREFINT Enable */ + +/****************** Bit definition for ADC_SAMPTR1 register *******************/ +#define ADC_SMP10 ((uint32_t)0x00000007) /* SMP10[2:0] bits (Channel 10 Sample time selection) */ +#define ADC_SMP10_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP10_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP10_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP11 ((uint32_t)0x00000038) /* SMP11[2:0] bits (Channel 11 Sample time selection) */ +#define ADC_SMP11_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP11_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP11_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP12 ((uint32_t)0x000001C0) /* SMP12[2:0] bits (Channel 12 Sample time selection) */ +#define ADC_SMP12_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP12_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP12_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP13 ((uint32_t)0x00000E00) /* SMP13[2:0] bits (Channel 13 Sample time selection) */ +#define ADC_SMP13_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP13_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP13_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP14 ((uint32_t)0x00007000) /* SMP14[2:0] bits (Channel 14 Sample time selection) */ +#define ADC_SMP14_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP14_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP14_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP15 ((uint32_t)0x00038000) /* SMP15[2:0] bits (Channel 15 Sample time selection) */ +#define ADC_SMP15_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP15_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP15_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define ADC_SMP16 ((uint32_t)0x001C0000) /* SMP16[2:0] bits (Channel 16 Sample time selection) */ +#define ADC_SMP16_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP16_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP16_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP17 ((uint32_t)0x00E00000) /* SMP17[2:0] bits (Channel 17 Sample time selection) */ +#define ADC_SMP17_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP17_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP17_2 ((uint32_t)0x00800000) /* Bit 2 */ + +/****************** Bit definition for ADC_SAMPTR2 register *******************/ +#define ADC_SMP0 ((uint32_t)0x00000007) /* SMP0[2:0] bits (Channel 0 Sample time selection) */ +#define ADC_SMP0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SMP0_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SMP0_2 ((uint32_t)0x00000004) /* Bit 2 */ + +#define ADC_SMP1 ((uint32_t)0x00000038) /* SMP1[2:0] bits (Channel 1 Sample time selection) */ +#define ADC_SMP1_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define ADC_SMP1_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define ADC_SMP1_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define ADC_SMP2 ((uint32_t)0x000001C0) /* SMP2[2:0] bits (Channel 2 Sample time selection) */ +#define ADC_SMP2_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define ADC_SMP2_1 ((uint32_t)0x00000080) /* Bit 1 */ +#define ADC_SMP2_2 ((uint32_t)0x00000100) /* Bit 2 */ + +#define ADC_SMP3 ((uint32_t)0x00000E00) /* SMP3[2:0] bits (Channel 3 Sample time selection) */ +#define ADC_SMP3_0 ((uint32_t)0x00000200) /* Bit 0 */ +#define ADC_SMP3_1 ((uint32_t)0x00000400) /* Bit 1 */ +#define ADC_SMP3_2 ((uint32_t)0x00000800) /* Bit 2 */ + +#define ADC_SMP4 ((uint32_t)0x00007000) /* SMP4[2:0] bits (Channel 4 Sample time selection) */ +#define ADC_SMP4_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define ADC_SMP4_1 ((uint32_t)0x00002000) /* Bit 1 */ +#define ADC_SMP4_2 ((uint32_t)0x00004000) /* Bit 2 */ + +#define ADC_SMP5 ((uint32_t)0x00038000) /* SMP5[2:0] bits (Channel 5 Sample time selection) */ +#define ADC_SMP5_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SMP5_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SMP5_2 ((uint32_t)0x00020000) /* Bit 2 */ + +#define ADC_SMP6 ((uint32_t)0x001C0000) /* SMP6[2:0] bits (Channel 6 Sample time selection) */ +#define ADC_SMP6_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define ADC_SMP6_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define ADC_SMP6_2 ((uint32_t)0x00100000) /* Bit 2 */ + +#define ADC_SMP7 ((uint32_t)0x00E00000) /* SMP7[2:0] bits (Channel 7 Sample time selection) */ +#define ADC_SMP7_0 ((uint32_t)0x00200000) /* Bit 0 */ +#define ADC_SMP7_1 ((uint32_t)0x00400000) /* Bit 1 */ +#define ADC_SMP7_2 ((uint32_t)0x00800000) /* Bit 2 */ + +#define ADC_SMP8 ((uint32_t)0x07000000) /* SMP8[2:0] bits (Channel 8 Sample time selection) */ +#define ADC_SMP8_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define ADC_SMP8_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define ADC_SMP8_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define ADC_SMP9 ((uint32_t)0x38000000) /* SMP9[2:0] bits (Channel 9 Sample time selection) */ +#define ADC_SMP9_0 ((uint32_t)0x08000000) /* Bit 0 */ +#define ADC_SMP9_1 ((uint32_t)0x10000000) /* Bit 1 */ +#define ADC_SMP9_2 ((uint32_t)0x20000000) /* Bit 2 */ + +/****************** Bit definition for ADC_IOFR1 register *******************/ +#define ADC_JOFFSET1 ((uint16_t)0x0FFF) /* Data offset for injected channel 1 */ + +/****************** Bit definition for ADC_IOFR2 register *******************/ +#define ADC_JOFFSET2 ((uint16_t)0x0FFF) /* Data offset for injected channel 2 */ + +/****************** Bit definition for ADC_IOFR3 register *******************/ +#define ADC_JOFFSET3 ((uint16_t)0x0FFF) /* Data offset for injected channel 3 */ + +/****************** Bit definition for ADC_IOFR4 register *******************/ +#define ADC_JOFFSET4 ((uint16_t)0x0FFF) /* Data offset for injected channel 4 */ + +/******************* Bit definition for ADC_WDHTR register ********************/ +#define ADC_HT ((uint16_t)0x0FFF) /* Analog watchdog high threshold */ + +/******************* Bit definition for ADC_WDLTR register ********************/ +#define ADC_LT ((uint16_t)0x0FFF) /* Analog watchdog low threshold */ + +/******************* Bit definition for ADC_RSQR1 register *******************/ +#define ADC_SQ13 ((uint32_t)0x0000001F) /* SQ13[4:0] bits (13th conversion in regular sequence) */ +#define ADC_SQ13_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ13_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ13_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ13_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ13_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ14 ((uint32_t)0x000003E0) /* SQ14[4:0] bits (14th conversion in regular sequence) */ +#define ADC_SQ14_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ14_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ14_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ14_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ14_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ15 ((uint32_t)0x00007C00) /* SQ15[4:0] bits (15th conversion in regular sequence) */ +#define ADC_SQ15_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ15_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ15_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ15_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ15_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ16 ((uint32_t)0x000F8000) /* SQ16[4:0] bits (16th conversion in regular sequence) */ +#define ADC_SQ16_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ16_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ16_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ16_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ16_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_L ((uint32_t)0x00F00000) /* L[3:0] bits (Regular channel sequence length) */ +#define ADC_L_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_L_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_L_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_L_3 ((uint32_t)0x00800000) /* Bit 3 */ + +/******************* Bit definition for ADC_RSQR2 register *******************/ +#define ADC_SQ7 ((uint32_t)0x0000001F) /* SQ7[4:0] bits (7th conversion in regular sequence) */ +#define ADC_SQ7_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ7_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ7_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ7_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ7_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ8 ((uint32_t)0x000003E0) /* SQ8[4:0] bits (8th conversion in regular sequence) */ +#define ADC_SQ8_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ8_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ8_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ8_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ8_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ9 ((uint32_t)0x00007C00) /* SQ9[4:0] bits (9th conversion in regular sequence) */ +#define ADC_SQ9_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ9_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ9_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ9_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ9_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ10 ((uint32_t)0x000F8000) /* SQ10[4:0] bits (10th conversion in regular sequence) */ +#define ADC_SQ10_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ10_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ10_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ10_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ10_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ11 ((uint32_t)0x01F00000) /* SQ11[4:0] bits (11th conversion in regular sequence) */ +#define ADC_SQ11_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ11_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ11_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ11_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ11_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ12 ((uint32_t)0x3E000000) /* SQ12[4:0] bits (12th conversion in regular sequence) */ +#define ADC_SQ12_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ12_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ12_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ12_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ12_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_RSQR3 register *******************/ +#define ADC_SQ1 ((uint32_t)0x0000001F) /* SQ1[4:0] bits (1st conversion in regular sequence) */ +#define ADC_SQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_SQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_SQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_SQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_SQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_SQ2 ((uint32_t)0x000003E0) /* SQ2[4:0] bits (2nd conversion in regular sequence) */ +#define ADC_SQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_SQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_SQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_SQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_SQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_SQ3 ((uint32_t)0x00007C00) /* SQ3[4:0] bits (3rd conversion in regular sequence) */ +#define ADC_SQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_SQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_SQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_SQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_SQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_SQ4 ((uint32_t)0x000F8000) /* SQ4[4:0] bits (4th conversion in regular sequence) */ +#define ADC_SQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_SQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_SQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_SQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_SQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_SQ5 ((uint32_t)0x01F00000) /* SQ5[4:0] bits (5th conversion in regular sequence) */ +#define ADC_SQ5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_SQ5_1 ((uint32_t)0x00200000) /* Bit 1 */ +#define ADC_SQ5_2 ((uint32_t)0x00400000) /* Bit 2 */ +#define ADC_SQ5_3 ((uint32_t)0x00800000) /* Bit 3 */ +#define ADC_SQ5_4 ((uint32_t)0x01000000) /* Bit 4 */ + +#define ADC_SQ6 ((uint32_t)0x3E000000) /* SQ6[4:0] bits (6th conversion in regular sequence) */ +#define ADC_SQ6_0 ((uint32_t)0x02000000) /* Bit 0 */ +#define ADC_SQ6_1 ((uint32_t)0x04000000) /* Bit 1 */ +#define ADC_SQ6_2 ((uint32_t)0x08000000) /* Bit 2 */ +#define ADC_SQ6_3 ((uint32_t)0x10000000) /* Bit 3 */ +#define ADC_SQ6_4 ((uint32_t)0x20000000) /* Bit 4 */ + +/******************* Bit definition for ADC_ISQR register *******************/ +#define ADC_JSQ1 ((uint32_t)0x0000001F) /* JSQ1[4:0] bits (1st conversion in injected sequence) */ +#define ADC_JSQ1_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define ADC_JSQ1_1 ((uint32_t)0x00000002) /* Bit 1 */ +#define ADC_JSQ1_2 ((uint32_t)0x00000004) /* Bit 2 */ +#define ADC_JSQ1_3 ((uint32_t)0x00000008) /* Bit 3 */ +#define ADC_JSQ1_4 ((uint32_t)0x00000010) /* Bit 4 */ + +#define ADC_JSQ2 ((uint32_t)0x000003E0) /* JSQ2[4:0] bits (2nd conversion in injected sequence) */ +#define ADC_JSQ2_0 ((uint32_t)0x00000020) /* Bit 0 */ +#define ADC_JSQ2_1 ((uint32_t)0x00000040) /* Bit 1 */ +#define ADC_JSQ2_2 ((uint32_t)0x00000080) /* Bit 2 */ +#define ADC_JSQ2_3 ((uint32_t)0x00000100) /* Bit 3 */ +#define ADC_JSQ2_4 ((uint32_t)0x00000200) /* Bit 4 */ + +#define ADC_JSQ3 ((uint32_t)0x00007C00) /* JSQ3[4:0] bits (3rd conversion in injected sequence) */ +#define ADC_JSQ3_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define ADC_JSQ3_1 ((uint32_t)0x00000800) /* Bit 1 */ +#define ADC_JSQ3_2 ((uint32_t)0x00001000) /* Bit 2 */ +#define ADC_JSQ3_3 ((uint32_t)0x00002000) /* Bit 3 */ +#define ADC_JSQ3_4 ((uint32_t)0x00004000) /* Bit 4 */ + +#define ADC_JSQ4 ((uint32_t)0x000F8000) /* JSQ4[4:0] bits (4th conversion in injected sequence) */ +#define ADC_JSQ4_0 ((uint32_t)0x00008000) /* Bit 0 */ +#define ADC_JSQ4_1 ((uint32_t)0x00010000) /* Bit 1 */ +#define ADC_JSQ4_2 ((uint32_t)0x00020000) /* Bit 2 */ +#define ADC_JSQ4_3 ((uint32_t)0x00040000) /* Bit 3 */ +#define ADC_JSQ4_4 ((uint32_t)0x00080000) /* Bit 4 */ + +#define ADC_JL ((uint32_t)0x00300000) /* JL[1:0] bits (Injected Sequence length) */ +#define ADC_JL_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define ADC_JL_1 ((uint32_t)0x00200000) /* Bit 1 */ + +/******************* Bit definition for ADC_IDATAR1 register *******************/ +#define ADC_IDATAR1_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR2 register *******************/ +#define ADC_IDATAR2_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR3 register *******************/ +#define ADC_IDATAR3_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************* Bit definition for ADC_IDATAR4 register *******************/ +#define ADC_IDATAR4_JDATA ((uint16_t)0xFFFF) /* Injected data */ + +/******************** Bit definition for ADC_RDATAR register ********************/ +#define ADC_RDATAR_DATA ((uint32_t)0x0000FFFF) /* Regular data */ +#define ADC_RDATAR_ADC2DATA ((uint32_t)0xFFFF0000) /* ADC2 data */ + +/******************************************************************************/ +/* Backup registers */ +/******************************************************************************/ + +/******************* Bit definition for BKP_DATAR1 register ********************/ +#define BKP_DATAR1_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR2 register ********************/ +#define BKP_DATAR2_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR3 register ********************/ +#define BKP_DATAR3_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR4 register ********************/ +#define BKP_DATAR4_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR5 register ********************/ +#define BKP_DATAR5_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR6 register ********************/ +#define BKP_DATAR6_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR7 register ********************/ +#define BKP_DATAR7_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR8 register ********************/ +#define BKP_DATAR8_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR9 register ********************/ +#define BKP_DATAR9_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR10 register *******************/ +#define BKP_DATAR10_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR11 register *******************/ +#define BKP_DATAR11_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR12 register *******************/ +#define BKP_DATAR12_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR13 register *******************/ +#define BKP_DATAR13_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR14 register *******************/ +#define BKP_DATAR14_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR15 register *******************/ +#define BKP_DATAR15_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR16 register *******************/ +#define BKP_DATAR16_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR17 register *******************/ +#define BKP_DATAR17_D ((uint16_t)0xFFFF) /* Backup data */ + +/****************** Bit definition for BKP_DATAR18 register ********************/ +#define BKP_DATAR18_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR19 register *******************/ +#define BKP_DATAR19_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR20 register *******************/ +#define BKP_DATAR20_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR21 register *******************/ +#define BKP_DATAR21_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR22 register *******************/ +#define BKP_DATAR22_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR23 register *******************/ +#define BKP_DATAR23_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR24 register *******************/ +#define BKP_DATAR24_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR25 register *******************/ +#define BKP_DATAR25_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR26 register *******************/ +#define BKP_DATAR26_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR27 register *******************/ +#define BKP_DATAR27_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR28 register *******************/ +#define BKP_DATAR28_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR29 register *******************/ +#define BKP_DATAR29_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR30 register *******************/ +#define BKP_DATAR30_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR31 register *******************/ +#define BKP_DATAR31_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR32 register *******************/ +#define BKP_DATAR32_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR33 register *******************/ +#define BKP_DATAR33_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR34 register *******************/ +#define BKP_DATAR34_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR35 register *******************/ +#define BKP_DATAR35_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR36 register *******************/ +#define BKP_DATAR36_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR37 register *******************/ +#define BKP_DATAR37_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR38 register *******************/ +#define BKP_DATAR38_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR39 register *******************/ +#define BKP_DATAR39_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR40 register *******************/ +#define BKP_DATAR40_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR41 register *******************/ +#define BKP_DATAR41_D ((uint16_t)0xFFFF) /* Backup data */ + +/******************* Bit definition for BKP_DATAR42 register *******************/ +#define BKP_DATAR42_D ((uint16_t)0xFFFF) /* Backup data */ + +/****************** Bit definition for BKP_OCTLR register *******************/ +#define BKP_CAL ((uint16_t)0x007F) /* Calibration value */ +#define BKP_CCO ((uint16_t)0x0080) /* Calibration Clock Output */ +#define BKP_ASOE ((uint16_t)0x0100) /* Alarm or Second Output Enable */ +#define BKP_ASOS ((uint16_t)0x0200) /* Alarm or Second Output Selection */ + +/******************** Bit definition for BKP_TPCTLR register ********************/ +#define BKP_TPE ((uint8_t)0x01) /* TAMPER pin enable */ +#define BKP_TPAL ((uint8_t)0x02) /* TAMPER pin active level */ + +/******************* Bit definition for BKP_TPCSR register ********************/ +#define BKP_CTE ((uint16_t)0x0001) /* Clear Tamper event */ +#define BKP_CTI ((uint16_t)0x0002) /* Clear Tamper Interrupt */ +#define BKP_TPIE ((uint16_t)0x0004) /* TAMPER Pin interrupt enable */ +#define BKP_TEF ((uint16_t)0x0100) /* Tamper Event Flag */ +#define BKP_TIF ((uint16_t)0x0200) /* Tamper Interrupt Flag */ + +/******************************************************************************/ +/* CRC Calculation Unit */ +/******************************************************************************/ + +/******************* Bit definition for CRC_DATAR register *********************/ +#define CRC_DATAR_DR ((uint32_t)0xFFFFFFFF) /* Data register bits */ + +/******************* Bit definition for CRC_IDATAR register ********************/ +#define CRC_IDR_IDATAR ((uint8_t)0xFF) /* General-purpose 8-bit data register bits */ + +/******************** Bit definition for CRC_CTLR register ********************/ +#define CRC_CTLR_RESET ((uint8_t)0x01) /* RESET bit */ + +/******************************************************************************/ +/* Digital to Analog Converter */ +/******************************************************************************/ + +/******************** Bit definition for DAC_CTLR register ********************/ +#define DAC_EN1 ((uint32_t)0x00000001) /* DAC channel1 enable */ +#define DAC_BOFF1 ((uint32_t)0x00000002) /* DAC channel1 output buffer disable */ +#define DAC_TEN1 ((uint32_t)0x00000004) /* DAC channel1 Trigger enable */ + +#define DAC_TSEL1 ((uint32_t)0x00000038) /* TSEL1[2:0] (DAC channel1 Trigger selection) */ +#define DAC_TSEL1_0 ((uint32_t)0x00000008) /* Bit 0 */ +#define DAC_TSEL1_1 ((uint32_t)0x00000010) /* Bit 1 */ +#define DAC_TSEL1_2 ((uint32_t)0x00000020) /* Bit 2 */ + +#define DAC_WAVE1 ((uint32_t)0x000000C0) /* WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */ +#define DAC_WAVE1_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define DAC_WAVE1_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define DAC_MAMP1 ((uint32_t)0x00000F00) /* MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */ +#define DAC_MAMP1_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define DAC_MAMP1_1 ((uint32_t)0x00000200) /* Bit 1 */ +#define DAC_MAMP1_2 ((uint32_t)0x00000400) /* Bit 2 */ +#define DAC_MAMP1_3 ((uint32_t)0x00000800) /* Bit 3 */ + +#define DAC_DMAEN1 ((uint32_t)0x00001000) /* DAC channel1 DMA enable */ +#define DAC_EN2 ((uint32_t)0x00010000) /* DAC channel2 enable */ +#define DAC_BOFF2 ((uint32_t)0x00020000) /* DAC channel2 output buffer disable */ +#define DAC_TEN2 ((uint32_t)0x00040000) /* DAC channel2 Trigger enable */ + +#define DAC_TSEL2 ((uint32_t)0x00380000) /* TSEL2[2:0] (DAC channel2 Trigger selection) */ +#define DAC_TSEL2_0 ((uint32_t)0x00080000) /* Bit 0 */ +#define DAC_TSEL2_1 ((uint32_t)0x00100000) /* Bit 1 */ +#define DAC_TSEL2_2 ((uint32_t)0x00200000) /* Bit 2 */ + +#define DAC_WAVE2 ((uint32_t)0x00C00000) /* WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */ +#define DAC_WAVE2_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define DAC_WAVE2_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define DAC_MAMP2 ((uint32_t)0x0F000000) /* MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */ +#define DAC_MAMP2_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define DAC_MAMP2_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define DAC_MAMP2_2 ((uint32_t)0x04000000) /* Bit 2 */ +#define DAC_MAMP2_3 ((uint32_t)0x08000000) /* Bit 3 */ + +#define DAC_DMAEN2 ((uint32_t)0x10000000) /* DAC channel2 DMA enabled */ + +/***************** Bit definition for DAC_SWTR register ******************/ +#define DAC_SWTRIG1 ((uint8_t)0x01) /* DAC channel1 software trigger */ +#define DAC_SWTRIG2 ((uint8_t)0x02) /* DAC channel2 software trigger */ + +/***************** Bit definition for DAC_R12BDHR1 register ******************/ +#define DAC_DHR12R1 ((uint16_t)0x0FFF) /* DAC channel1 12-bit Right aligned data */ + +/***************** Bit definition for DAC_L12BDHR1 register ******************/ +#define DAC_DHR12L1 ((uint16_t)0xFFF0) /* DAC channel1 12-bit Left aligned data */ + +/****************** Bit definition for DAC_R8BDHR1 register ******************/ +#define DAC_DHR8R1 ((uint8_t)0xFF) /* DAC channel1 8-bit Right aligned data */ + +/***************** Bit definition for DAC_R12BDHR2 register ******************/ +#define DAC_DHR12R2 ((uint16_t)0x0FFF) /* DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_L12BDHR2 register ******************/ +#define DAC_DHR12L2 ((uint16_t)0xFFF0) /* DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_R8BDHR2 register ******************/ +#define DAC_DHR8R2 ((uint8_t)0xFF) /* DAC channel2 8-bit Right aligned data */ + +/***************** Bit definition for DAC_RD12BDHR register ******************/ +#define DAC_RD12BDHR_DACC1DHR ((uint32_t)0x00000FFF) /* DAC channel1 12-bit Right aligned data */ +#define DAC_RD12BDHR_DACC2DHR ((uint32_t)0x0FFF0000) /* DAC channel2 12-bit Right aligned data */ + +/***************** Bit definition for DAC_LD12BDHR register ******************/ +#define DAC_LD12BDHR_DACC1DHR ((uint32_t)0x0000FFF0) /* DAC channel1 12-bit Left aligned data */ +#define DAC_LD12BDHR_DACC2DHR ((uint32_t)0xFFF00000) /* DAC channel2 12-bit Left aligned data */ + +/****************** Bit definition for DAC_RD8BDHR register ******************/ +#define DAC_RD8BDHR_DACC1DHR ((uint16_t)0x00FF) /* DAC channel1 8-bit Right aligned data */ +#define DAC_RD8BDHR_DACC2DHR ((uint16_t)0xFF00) /* DAC channel2 8-bit Right aligned data */ + +/******************* Bit definition for DAC_DOR1 register *******************/ +#define DAC_DACC1DOR ((uint16_t)0x0FFF) /* DAC channel1 data output */ + +/******************* Bit definition for DAC_DOR2 register *******************/ +#define DAC_DACC2DOR ((uint16_t)0x0FFF) /* DAC channel2 data output */ + +/******************************************************************************/ +/* DMA Controller */ +/******************************************************************************/ + +/******************* Bit definition for DMA_INTFR register ********************/ +#define DMA_GIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt flag */ +#define DMA_TCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete flag */ +#define DMA_HTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer flag */ +#define DMA_TEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error flag */ +#define DMA_GIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt flag */ +#define DMA_TCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete flag */ +#define DMA_HTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer flag */ +#define DMA_TEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error flag */ +#define DMA_GIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt flag */ +#define DMA_TCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete flag */ +#define DMA_HTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer flag */ +#define DMA_TEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error flag */ +#define DMA_GIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt flag */ +#define DMA_TCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete flag */ +#define DMA_HTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer flag */ +#define DMA_TEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error flag */ +#define DMA_GIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt flag */ +#define DMA_TCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete flag */ +#define DMA_HTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer flag */ +#define DMA_TEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error flag */ +#define DMA_GIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt flag */ +#define DMA_TCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete flag */ +#define DMA_HTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer flag */ +#define DMA_TEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error flag */ +#define DMA_GIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt flag */ +#define DMA_TCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete flag */ +#define DMA_HTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer flag */ +#define DMA_TEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_INTFCR register *******************/ +#define DMA_CGIF1 ((uint32_t)0x00000001) /* Channel 1 Global interrupt clear */ +#define DMA_CTCIF1 ((uint32_t)0x00000002) /* Channel 1 Transfer Complete clear */ +#define DMA_CHTIF1 ((uint32_t)0x00000004) /* Channel 1 Half Transfer clear */ +#define DMA_CTEIF1 ((uint32_t)0x00000008) /* Channel 1 Transfer Error clear */ +#define DMA_CGIF2 ((uint32_t)0x00000010) /* Channel 2 Global interrupt clear */ +#define DMA_CTCIF2 ((uint32_t)0x00000020) /* Channel 2 Transfer Complete clear */ +#define DMA_CHTIF2 ((uint32_t)0x00000040) /* Channel 2 Half Transfer clear */ +#define DMA_CTEIF2 ((uint32_t)0x00000080) /* Channel 2 Transfer Error clear */ +#define DMA_CGIF3 ((uint32_t)0x00000100) /* Channel 3 Global interrupt clear */ +#define DMA_CTCIF3 ((uint32_t)0x00000200) /* Channel 3 Transfer Complete clear */ +#define DMA_CHTIF3 ((uint32_t)0x00000400) /* Channel 3 Half Transfer clear */ +#define DMA_CTEIF3 ((uint32_t)0x00000800) /* Channel 3 Transfer Error clear */ +#define DMA_CGIF4 ((uint32_t)0x00001000) /* Channel 4 Global interrupt clear */ +#define DMA_CTCIF4 ((uint32_t)0x00002000) /* Channel 4 Transfer Complete clear */ +#define DMA_CHTIF4 ((uint32_t)0x00004000) /* Channel 4 Half Transfer clear */ +#define DMA_CTEIF4 ((uint32_t)0x00008000) /* Channel 4 Transfer Error clear */ +#define DMA_CGIF5 ((uint32_t)0x00010000) /* Channel 5 Global interrupt clear */ +#define DMA_CTCIF5 ((uint32_t)0x00020000) /* Channel 5 Transfer Complete clear */ +#define DMA_CHTIF5 ((uint32_t)0x00040000) /* Channel 5 Half Transfer clear */ +#define DMA_CTEIF5 ((uint32_t)0x00080000) /* Channel 5 Transfer Error clear */ +#define DMA_CGIF6 ((uint32_t)0x00100000) /* Channel 6 Global interrupt clear */ +#define DMA_CTCIF6 ((uint32_t)0x00200000) /* Channel 6 Transfer Complete clear */ +#define DMA_CHTIF6 ((uint32_t)0x00400000) /* Channel 6 Half Transfer clear */ +#define DMA_CTEIF6 ((uint32_t)0x00800000) /* Channel 6 Transfer Error clear */ +#define DMA_CGIF7 ((uint32_t)0x01000000) /* Channel 7 Global interrupt clear */ +#define DMA_CTCIF7 ((uint32_t)0x02000000) /* Channel 7 Transfer Complete clear */ +#define DMA_CHTIF7 ((uint32_t)0x04000000) /* Channel 7 Half Transfer clear */ +#define DMA_CTEIF7 ((uint32_t)0x08000000) /* Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CFGR1 register *******************/ +#define DMA_CFGR1_EN ((uint16_t)0x0001) /* Channel enable*/ +#define DMA_CFGR1_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR1_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR1_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR1_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR1_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR1_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR1_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR1_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR1_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR1_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR1_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR1_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR1_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR1_PL ((uint16_t)0x3000) /* PL[1:0] bits(Channel Priority level) */ +#define DMA_CFGR1_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR1_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR1_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR2 register *******************/ +#define DMA_CFGR2_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR2_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR2_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR2_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR2_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR2_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR2_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR2_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR2_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR2_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR2_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR2_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR2_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR2_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR2_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR2_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR2_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR2_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFGR3 register *******************/ +#define DMA_CFGR3_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFGR3_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFGR3_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFGR3_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFGR3_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFGR3_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFGR3_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFGR3_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFGR3_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFGR3_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFGR3_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFGR3_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFGR3_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFGR3_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFGR3_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFGR3_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFGR3_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFGR3_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFG4 register *******************/ +#define DMA_CFG4_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG4_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG4_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG4_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG4_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG4_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG4_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG4_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG4_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG4_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG4_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG4_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG4_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG4_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG4_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG4_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG4_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG4_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/****************** Bit definition for DMA_CFG5 register *******************/ +#define DMA_CFG5_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG5_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG5_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG5_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG5_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG5_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG5_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG5_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG5_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG5_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG5_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG5_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG5_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG5_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG5_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG5_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG5_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG5_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/******************* Bit definition for DMA_CFG6 register *******************/ +#define DMA_CFG6_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG6_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG6_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG6_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG6_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG6_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG6_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG6_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG6_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG6_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG6_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG6_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG6_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG6_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG6_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG6_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG6_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG6_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode */ + +/******************* Bit definition for DMA_CFG7 register *******************/ +#define DMA_CFG7_EN ((uint16_t)0x0001) /* Channel enable */ +#define DMA_CFG7_TCIE ((uint16_t)0x0002) /* Transfer complete interrupt enable */ +#define DMA_CFG7_HTIE ((uint16_t)0x0004) /* Half Transfer interrupt enable */ +#define DMA_CFG7_TEIE ((uint16_t)0x0008) /* Transfer error interrupt enable */ +#define DMA_CFG7_DIR ((uint16_t)0x0010) /* Data transfer direction */ +#define DMA_CFG7_CIRC ((uint16_t)0x0020) /* Circular mode */ +#define DMA_CFG7_PINC ((uint16_t)0x0040) /* Peripheral increment mode */ +#define DMA_CFG7_MINC ((uint16_t)0x0080) /* Memory increment mode */ + +#define DMA_CFG7_PSIZE ((uint16_t)0x0300) /* PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CFG7_PSIZE_0 ((uint16_t)0x0100) /* Bit 0 */ +#define DMA_CFG7_PSIZE_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define DMA_CFG7_MSIZE ((uint16_t)0x0C00) /* MSIZE[1:0] bits (Memory size) */ +#define DMA_CFG7_MSIZE_0 ((uint16_t)0x0400) /* Bit 0 */ +#define DMA_CFG7_MSIZE_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define DMA_CFG7_PL ((uint16_t)0x3000) /* PL[1:0] bits (Channel Priority level) */ +#define DMA_CFG7_PL_0 ((uint16_t)0x1000) /* Bit 0 */ +#define DMA_CFG7_PL_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define DMA_CFG7_MEM2MEM ((uint16_t)0x4000) /* Memory to memory mode enable */ + +/****************** Bit definition for DMA_CNTR1 register ******************/ +#define DMA_CNTR1_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR2 register ******************/ +#define DMA_CNTR2_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR3 register ******************/ +#define DMA_CNTR3_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR4 register ******************/ +#define DMA_CNTR4_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR5 register ******************/ +#define DMA_CNTR5_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR6 register ******************/ +#define DMA_CNTR6_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_CNTR7 register ******************/ +#define DMA_CNTR7_NDT ((uint16_t)0xFFFF) /* Number of data to Transfer */ + +/****************** Bit definition for DMA_PADDR1 register *******************/ +#define DMA_PADDR1_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR2 register *******************/ +#define DMA_PADDR2_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR3 register *******************/ +#define DMA_PADDR3_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR4 register *******************/ +#define DMA_PADDR4_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR5 register *******************/ +#define DMA_PADDR5_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR6 register *******************/ +#define DMA_PADDR6_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_PADDR7 register *******************/ +#define DMA_PADDR7_PA ((uint32_t)0xFFFFFFFF) /* Peripheral Address */ + +/****************** Bit definition for DMA_MADDR1 register *******************/ +#define DMA_MADDR1_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR2 register *******************/ +#define DMA_MADDR2_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR3 register *******************/ +#define DMA_MADDR3_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR4 register *******************/ +#define DMA_MADDR4_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR5 register *******************/ +#define DMA_MADDR5_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR6 register *******************/ +#define DMA_MADDR6_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/****************** Bit definition for DMA_MADDR7 register *******************/ +#define DMA_MADDR7_MA ((uint32_t)0xFFFFFFFF) /* Memory Address */ + +/******************************************************************************/ +/* External Interrupt/Event Controller */ +/******************************************************************************/ + +/******************* Bit definition for EXTI_INTENR register *******************/ +#define EXTI_INTENR_MR0 ((uint32_t)0x00000001) /* Interrupt Mask on line 0 */ +#define EXTI_INTENR_MR1 ((uint32_t)0x00000002) /* Interrupt Mask on line 1 */ +#define EXTI_INTENR_MR2 ((uint32_t)0x00000004) /* Interrupt Mask on line 2 */ +#define EXTI_INTENR_MR3 ((uint32_t)0x00000008) /* Interrupt Mask on line 3 */ +#define EXTI_INTENR_MR4 ((uint32_t)0x00000010) /* Interrupt Mask on line 4 */ +#define EXTI_INTENR_MR5 ((uint32_t)0x00000020) /* Interrupt Mask on line 5 */ +#define EXTI_INTENR_MR6 ((uint32_t)0x00000040) /* Interrupt Mask on line 6 */ +#define EXTI_INTENR_MR7 ((uint32_t)0x00000080) /* Interrupt Mask on line 7 */ +#define EXTI_INTENR_MR8 ((uint32_t)0x00000100) /* Interrupt Mask on line 8 */ +#define EXTI_INTENR_MR9 ((uint32_t)0x00000200) /* Interrupt Mask on line 9 */ +#define EXTI_INTENR_MR10 ((uint32_t)0x00000400) /* Interrupt Mask on line 10 */ +#define EXTI_INTENR_MR11 ((uint32_t)0x00000800) /* Interrupt Mask on line 11 */ +#define EXTI_INTENR_MR12 ((uint32_t)0x00001000) /* Interrupt Mask on line 12 */ +#define EXTI_INTENR_MR13 ((uint32_t)0x00002000) /* Interrupt Mask on line 13 */ +#define EXTI_INTENR_MR14 ((uint32_t)0x00004000) /* Interrupt Mask on line 14 */ +#define EXTI_INTENR_MR15 ((uint32_t)0x00008000) /* Interrupt Mask on line 15 */ +#define EXTI_INTENR_MR16 ((uint32_t)0x00010000) /* Interrupt Mask on line 16 */ +#define EXTI_INTENR_MR17 ((uint32_t)0x00020000) /* Interrupt Mask on line 17 */ +#define EXTI_INTENR_MR18 ((uint32_t)0x00040000) /* Interrupt Mask on line 18 */ +#define EXTI_INTENR_MR19 ((uint32_t)0x00080000) /* Interrupt Mask on line 19 */ + +/******************* Bit definition for EXTI_EVENR register *******************/ +#define EXTI_EVENR_MR0 ((uint32_t)0x00000001) /* Event Mask on line 0 */ +#define EXTI_EVENR_MR1 ((uint32_t)0x00000002) /* Event Mask on line 1 */ +#define EXTI_EVENR_MR2 ((uint32_t)0x00000004) /* Event Mask on line 2 */ +#define EXTI_EVENR_MR3 ((uint32_t)0x00000008) /* Event Mask on line 3 */ +#define EXTI_EVENR_MR4 ((uint32_t)0x00000010) /* Event Mask on line 4 */ +#define EXTI_EVENR_MR5 ((uint32_t)0x00000020) /* Event Mask on line 5 */ +#define EXTI_EVENR_MR6 ((uint32_t)0x00000040) /* Event Mask on line 6 */ +#define EXTI_EVENR_MR7 ((uint32_t)0x00000080) /* Event Mask on line 7 */ +#define EXTI_EVENR_MR8 ((uint32_t)0x00000100) /* Event Mask on line 8 */ +#define EXTI_EVENR_MR9 ((uint32_t)0x00000200) /* Event Mask on line 9 */ +#define EXTI_EVENR_MR10 ((uint32_t)0x00000400) /* Event Mask on line 10 */ +#define EXTI_EVENR_MR11 ((uint32_t)0x00000800) /* Event Mask on line 11 */ +#define EXTI_EVENR_MR12 ((uint32_t)0x00001000) /* Event Mask on line 12 */ +#define EXTI_EVENR_MR13 ((uint32_t)0x00002000) /* Event Mask on line 13 */ +#define EXTI_EVENR_MR14 ((uint32_t)0x00004000) /* Event Mask on line 14 */ +#define EXTI_EVENR_MR15 ((uint32_t)0x00008000) /* Event Mask on line 15 */ +#define EXTI_EVENR_MR16 ((uint32_t)0x00010000) /* Event Mask on line 16 */ +#define EXTI_EVENR_MR17 ((uint32_t)0x00020000) /* Event Mask on line 17 */ +#define EXTI_EVENR_MR18 ((uint32_t)0x00040000) /* Event Mask on line 18 */ +#define EXTI_EVENR_MR19 ((uint32_t)0x00080000) /* Event Mask on line 19 */ + +/****************** Bit definition for EXTI_RTENR register *******************/ +#define EXTI_RTENR_TR0 ((uint32_t)0x00000001) /* Rising trigger event configuration bit of line 0 */ +#define EXTI_RTENR_TR1 ((uint32_t)0x00000002) /* Rising trigger event configuration bit of line 1 */ +#define EXTI_RTENR_TR2 ((uint32_t)0x00000004) /* Rising trigger event configuration bit of line 2 */ +#define EXTI_RTENR_TR3 ((uint32_t)0x00000008) /* Rising trigger event configuration bit of line 3 */ +#define EXTI_RTENR_TR4 ((uint32_t)0x00000010) /* Rising trigger event configuration bit of line 4 */ +#define EXTI_RTENR_TR5 ((uint32_t)0x00000020) /* Rising trigger event configuration bit of line 5 */ +#define EXTI_RTENR_TR6 ((uint32_t)0x00000040) /* Rising trigger event configuration bit of line 6 */ +#define EXTI_RTENR_TR7 ((uint32_t)0x00000080) /* Rising trigger event configuration bit of line 7 */ +#define EXTI_RTENR_TR8 ((uint32_t)0x00000100) /* Rising trigger event configuration bit of line 8 */ +#define EXTI_RTENR_TR9 ((uint32_t)0x00000200) /* Rising trigger event configuration bit of line 9 */ +#define EXTI_RTENR_TR10 ((uint32_t)0x00000400) /* Rising trigger event configuration bit of line 10 */ +#define EXTI_RTENR_TR11 ((uint32_t)0x00000800) /* Rising trigger event configuration bit of line 11 */ +#define EXTI_RTENR_TR12 ((uint32_t)0x00001000) /* Rising trigger event configuration bit of line 12 */ +#define EXTI_RTENR_TR13 ((uint32_t)0x00002000) /* Rising trigger event configuration bit of line 13 */ +#define EXTI_RTENR_TR14 ((uint32_t)0x00004000) /* Rising trigger event configuration bit of line 14 */ +#define EXTI_RTENR_TR15 ((uint32_t)0x00008000) /* Rising trigger event configuration bit of line 15 */ +#define EXTI_RTENR_TR16 ((uint32_t)0x00010000) /* Rising trigger event configuration bit of line 16 */ +#define EXTI_RTENR_TR17 ((uint32_t)0x00020000) /* Rising trigger event configuration bit of line 17 */ +#define EXTI_RTENR_TR18 ((uint32_t)0x00040000) /* Rising trigger event configuration bit of line 18 */ +#define EXTI_RTENR_TR19 ((uint32_t)0x00080000) /* Rising trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_FTENR register *******************/ +#define EXTI_FTENR_TR0 ((uint32_t)0x00000001) /* Falling trigger event configuration bit of line 0 */ +#define EXTI_FTENR_TR1 ((uint32_t)0x00000002) /* Falling trigger event configuration bit of line 1 */ +#define EXTI_FTENR_TR2 ((uint32_t)0x00000004) /* Falling trigger event configuration bit of line 2 */ +#define EXTI_FTENR_TR3 ((uint32_t)0x00000008) /* Falling trigger event configuration bit of line 3 */ +#define EXTI_FTENR_TR4 ((uint32_t)0x00000010) /* Falling trigger event configuration bit of line 4 */ +#define EXTI_FTENR_TR5 ((uint32_t)0x00000020) /* Falling trigger event configuration bit of line 5 */ +#define EXTI_FTENR_TR6 ((uint32_t)0x00000040) /* Falling trigger event configuration bit of line 6 */ +#define EXTI_FTENR_TR7 ((uint32_t)0x00000080) /* Falling trigger event configuration bit of line 7 */ +#define EXTI_FTENR_TR8 ((uint32_t)0x00000100) /* Falling trigger event configuration bit of line 8 */ +#define EXTI_FTENR_TR9 ((uint32_t)0x00000200) /* Falling trigger event configuration bit of line 9 */ +#define EXTI_FTENR_TR10 ((uint32_t)0x00000400) /* Falling trigger event configuration bit of line 10 */ +#define EXTI_FTENR_TR11 ((uint32_t)0x00000800) /* Falling trigger event configuration bit of line 11 */ +#define EXTI_FTENR_TR12 ((uint32_t)0x00001000) /* Falling trigger event configuration bit of line 12 */ +#define EXTI_FTENR_TR13 ((uint32_t)0x00002000) /* Falling trigger event configuration bit of line 13 */ +#define EXTI_FTENR_TR14 ((uint32_t)0x00004000) /* Falling trigger event configuration bit of line 14 */ +#define EXTI_FTENR_TR15 ((uint32_t)0x00008000) /* Falling trigger event configuration bit of line 15 */ +#define EXTI_FTENR_TR16 ((uint32_t)0x00010000) /* Falling trigger event configuration bit of line 16 */ +#define EXTI_FTENR_TR17 ((uint32_t)0x00020000) /* Falling trigger event configuration bit of line 17 */ +#define EXTI_FTENR_TR18 ((uint32_t)0x00040000) /* Falling trigger event configuration bit of line 18 */ +#define EXTI_FTENR_TR19 ((uint32_t)0x00080000) /* Falling trigger event configuration bit of line 19 */ + +/****************** Bit definition for EXTI_SWIEVR register ******************/ +#define EXTI_SWIEVR_SWIEVR0 ((uint32_t)0x00000001) /* Software Interrupt on line 0 */ +#define EXTI_SWIEVR_SWIEVR1 ((uint32_t)0x00000002) /* Software Interrupt on line 1 */ +#define EXTI_SWIEVR_SWIEVR2 ((uint32_t)0x00000004) /* Software Interrupt on line 2 */ +#define EXTI_SWIEVR_SWIEVR3 ((uint32_t)0x00000008) /* Software Interrupt on line 3 */ +#define EXTI_SWIEVR_SWIEVR4 ((uint32_t)0x00000010) /* Software Interrupt on line 4 */ +#define EXTI_SWIEVR_SWIEVR5 ((uint32_t)0x00000020) /* Software Interrupt on line 5 */ +#define EXTI_SWIEVR_SWIEVR6 ((uint32_t)0x00000040) /* Software Interrupt on line 6 */ +#define EXTI_SWIEVR_SWIEVR7 ((uint32_t)0x00000080) /* Software Interrupt on line 7 */ +#define EXTI_SWIEVR_SWIEVR8 ((uint32_t)0x00000100) /* Software Interrupt on line 8 */ +#define EXTI_SWIEVR_SWIEVR9 ((uint32_t)0x00000200) /* Software Interrupt on line 9 */ +#define EXTI_SWIEVR_SWIEVR10 ((uint32_t)0x00000400) /* Software Interrupt on line 10 */ +#define EXTI_SWIEVR_SWIEVR11 ((uint32_t)0x00000800) /* Software Interrupt on line 11 */ +#define EXTI_SWIEVR_SWIEVR12 ((uint32_t)0x00001000) /* Software Interrupt on line 12 */ +#define EXTI_SWIEVR_SWIEVR13 ((uint32_t)0x00002000) /* Software Interrupt on line 13 */ +#define EXTI_SWIEVR_SWIEVR14 ((uint32_t)0x00004000) /* Software Interrupt on line 14 */ +#define EXTI_SWIEVR_SWIEVR15 ((uint32_t)0x00008000) /* Software Interrupt on line 15 */ +#define EXTI_SWIEVR_SWIEVR16 ((uint32_t)0x00010000) /* Software Interrupt on line 16 */ +#define EXTI_SWIEVR_SWIEVR17 ((uint32_t)0x00020000) /* Software Interrupt on line 17 */ +#define EXTI_SWIEVR_SWIEVR18 ((uint32_t)0x00040000) /* Software Interrupt on line 18 */ +#define EXTI_SWIEVR_SWIEVR19 ((uint32_t)0x00080000) /* Software Interrupt on line 19 */ + +/******************* Bit definition for EXTI_INTFR register ********************/ +#define EXTI_INTF_INTF0 ((uint32_t)0x00000001) /* Pending bit for line 0 */ +#define EXTI_INTF_INTF1 ((uint32_t)0x00000002) /* Pending bit for line 1 */ +#define EXTI_INTF_INTF2 ((uint32_t)0x00000004) /* Pending bit for line 2 */ +#define EXTI_INTF_INTF3 ((uint32_t)0x00000008) /* Pending bit for line 3 */ +#define EXTI_INTF_INTF4 ((uint32_t)0x00000010) /* Pending bit for line 4 */ +#define EXTI_INTF_INTF5 ((uint32_t)0x00000020) /* Pending bit for line 5 */ +#define EXTI_INTF_INTF6 ((uint32_t)0x00000040) /* Pending bit for line 6 */ +#define EXTI_INTF_INTF7 ((uint32_t)0x00000080) /* Pending bit for line 7 */ +#define EXTI_INTF_INTF8 ((uint32_t)0x00000100) /* Pending bit for line 8 */ +#define EXTI_INTF_INTF9 ((uint32_t)0x00000200) /* Pending bit for line 9 */ +#define EXTI_INTF_INTF10 ((uint32_t)0x00000400) /* Pending bit for line 10 */ +#define EXTI_INTF_INTF11 ((uint32_t)0x00000800) /* Pending bit for line 11 */ +#define EXTI_INTF_INTF12 ((uint32_t)0x00001000) /* Pending bit for line 12 */ +#define EXTI_INTF_INTF13 ((uint32_t)0x00002000) /* Pending bit for line 13 */ +#define EXTI_INTF_INTF14 ((uint32_t)0x00004000) /* Pending bit for line 14 */ +#define EXTI_INTF_INTF15 ((uint32_t)0x00008000) /* Pending bit for line 15 */ +#define EXTI_INTF_INTF16 ((uint32_t)0x00010000) /* Pending bit for line 16 */ +#define EXTI_INTF_INTF17 ((uint32_t)0x00020000) /* Pending bit for line 17 */ +#define EXTI_INTF_INTF18 ((uint32_t)0x00040000) /* Pending bit for line 18 */ +#define EXTI_INTF_INTF19 ((uint32_t)0x00080000) /* Pending bit for line 19 */ + +/******************************************************************************/ +/* FLASH and Option Bytes Registers */ +/******************************************************************************/ + +/******************* Bit definition for FLASH_ACTLR register ******************/ +#define FLASH_ACTLR_LATENCY ((uint8_t)0x03) /* LATENCY[2:0] bits (Latency) */ +#define FLASH_ACTLR_LATENCY_0 ((uint8_t)0x00) /* Bit 0 */ +#define FLASH_ACTLR_LATENCY_1 ((uint8_t)0x01) /* Bit 0 */ +#define FLASH_ACTLR_LATENCY_2 ((uint8_t)0x02) /* Bit 1 */ + +#define FLASH_ACTLR_HLFCYA ((uint8_t)0x08) /* Flash Half Cycle Access Enable */ +#define FLASH_ACTLR_PRFTBE ((uint8_t)0x10) /* Prefetch Buffer Enable */ +#define FLASH_ACTLR_PRFTBS ((uint8_t)0x20) /* Prefetch Buffer Status */ + +/****************** Bit definition for FLASH_KEYR register ******************/ +#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /* FPEC Key */ + +/***************** Bit definition for FLASH_OBKEYR register ****************/ +#define FLASH_OBKEYR_OBKEYR ((uint32_t)0xFFFFFFFF) /* Option Byte Key */ + +/****************** Bit definition for FLASH_STATR register *******************/ +#define FLASH_STATR_BSY ((uint8_t)0x01) /* Busy */ +#define FLASH_STATR_PGERR ((uint8_t)0x04) /* Programming Error */ +#define FLASH_STATR_WRPRTERR ((uint8_t)0x10) /* Write Protection Error */ +#define FLASH_STATR_EOP ((uint8_t)0x20) /* End of operation */ + +/******************* Bit definition for FLASH_CTLR register *******************/ +#define FLASH_CTLR_PG ((uint16_t)0x0001) /* Programming */ +#define FLASH_CTLR_PER ((uint16_t)0x0002) /* Page Erase */ +#define FLASH_CTLR_MER ((uint16_t)0x0004) /* Mass Erase */ +#define FLASH_CTLR_OPTPG ((uint16_t)0x0010) /* Option Byte Programming */ +#define FLASH_CTLR_OPTER ((uint16_t)0x0020) /* Option Byte Erase */ +#define FLASH_CTLR_STRT ((uint16_t)0x0040) /* Start */ +#define FLASH_CTLR_LOCK ((uint16_t)0x0080) /* Lock */ +#define FLASH_CTLR_OPTWRE ((uint16_t)0x0200) /* Option Bytes Write Enable */ +#define FLASH_CTLR_ERRIE ((uint16_t)0x0400) /* Error Interrupt Enable */ +#define FLASH_CTLR_EOPIE ((uint16_t)0x1000) /* End of operation interrupt enable */ +#define FLASH_CTLR_PAGE_PG ((uint16_t)0x00010000) /* Page Programming 128Byte */ +#define FLASH_CTLR_PAGE_ER ((uint16_t)0x00020000) /* Page Erase 128Byte */ +#define FLASH_CTLR_BUF_LOAD ((uint16_t)0x00040000) /* Buffer Load */ +#define FLASH_CTLR_BUF_RST ((uint16_t)0x00080000) /* Buffer Reset */ + +/******************* Bit definition for FLASH_ADDR register *******************/ +#define FLASH_ADDR_FAR ((uint32_t)0xFFFFFFFF) /* Flash Address */ + +/****************** Bit definition for FLASH_OBR register *******************/ +#define FLASH_OBR_OPTERR ((uint16_t)0x0001) /* Option Byte Error */ +#define FLASH_OBR_RDPRT ((uint16_t)0x0002) /* Read protection */ + +#define FLASH_OBR_USER ((uint16_t)0x03FC) /* User Option Bytes */ +#define FLASH_OBR_WDG_SW ((uint16_t)0x0004) /* WDG_SW */ +#define FLASH_OBR_nRST_STOP ((uint16_t)0x0008) /* nRST_STOP */ +#define FLASH_OBR_nRST_STDBY ((uint16_t)0x0010) /* nRST_STDBY */ +#define FLASH_OBR_BFB2 ((uint16_t)0x0020) /* BFB2 */ + +/****************** Bit definition for FLASH_WPR register ******************/ +#define FLASH_WPR_WRP ((uint32_t)0xFFFFFFFF) /* Write Protect */ + +/****************** Bit definition for FLASH_RDPR register *******************/ +#define FLASH_RDPR_RDPR ((uint32_t)0x000000FF) /* Read protection option byte */ +#define FLASH_RDPR_nRDPR ((uint32_t)0x0000FF00) /* Read protection complemented option byte */ + +/****************** Bit definition for FLASH_USER register ******************/ +#define FLASH_USER_USER ((uint32_t)0x00FF0000) /* User option byte */ +#define FLASH_USER_nUSER ((uint32_t)0xFF000000) /* User complemented option byte */ + +/****************** Bit definition for FLASH_Data0 register *****************/ +#define FLASH_Data0_Data0 ((uint32_t)0x000000FF) /* User data storage option byte */ +#define FLASH_Data0_nData0 ((uint32_t)0x0000FF00) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_Data1 register *****************/ +#define FLASH_Data1_Data1 ((uint32_t)0x00FF0000) /* User data storage option byte */ +#define FLASH_Data1_nData1 ((uint32_t)0xFF000000) /* User data storage complemented option byte */ + +/****************** Bit definition for FLASH_WRPR0 register ******************/ +#define FLASH_WRPR0_WRPR0 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR0_nWRPR0 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR1 register ******************/ +#define FLASH_WRPR1_WRPR1 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR1_nWRPR1 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR2 register ******************/ +#define FLASH_WRPR2_WRPR2 ((uint32_t)0x000000FF) /* Flash memory write protection option bytes */ +#define FLASH_WRPR2_nWRPR2 ((uint32_t)0x0000FF00) /* Flash memory write protection complemented option bytes */ + +/****************** Bit definition for FLASH_WRPR3 register ******************/ +#define FLASH_WRPR3_WRPR3 ((uint32_t)0x00FF0000) /* Flash memory write protection option bytes */ +#define FLASH_WRPR3_nWRPR3 ((uint32_t)0xFF000000) /* Flash memory write protection complemented option bytes */ + +/******************************************************************************/ +/* General Purpose and Alternate Function I/O */ +/******************************************************************************/ + +/******************* Bit definition for GPIO_CFGLR register *******************/ +#define GPIO_CFGLR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGLR_MODE0 ((uint32_t)0x00000003) /* MODE0[1:0] bits (Port x mode bits, pin 0) */ +#define GPIO_CFGLR_MODE0_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGLR_MODE0_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGLR_MODE1 ((uint32_t)0x00000030) /* MODE1[1:0] bits (Port x mode bits, pin 1) */ +#define GPIO_CFGLR_MODE1_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGLR_MODE1_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGLR_MODE2 ((uint32_t)0x00000300) /* MODE2[1:0] bits (Port x mode bits, pin 2) */ +#define GPIO_CFGLR_MODE2_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGLR_MODE2_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGLR_MODE3 ((uint32_t)0x00003000) /* MODE3[1:0] bits (Port x mode bits, pin 3) */ +#define GPIO_CFGLR_MODE3_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGLR_MODE3_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE4 ((uint32_t)0x00030000) /* MODE4[1:0] bits (Port x mode bits, pin 4) */ +#define GPIO_CFGLR_MODE4_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGLR_MODE4_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE5 ((uint32_t)0x00300000) /* MODE5[1:0] bits (Port x mode bits, pin 5) */ +#define GPIO_CFGLR_MODE5_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGLR_MODE5_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE6 ((uint32_t)0x03000000) /* MODE6[1:0] bits (Port x mode bits, pin 6) */ +#define GPIO_CFGLR_MODE6_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE6_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGLR_MODE7 ((uint32_t)0x30000000) /* MODE7[1:0] bits (Port x mode bits, pin 7) */ +#define GPIO_CFGLR_MODE7_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGLR_MODE7_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGLR_CNF0 ((uint32_t)0x0000000C) /* CNF0[1:0] bits (Port x configuration bits, pin 0) */ +#define GPIO_CFGLR_CNF0_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGLR_CNF0_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGLR_CNF1 ((uint32_t)0x000000C0) /* CNF1[1:0] bits (Port x configuration bits, pin 1) */ +#define GPIO_CFGLR_CNF1_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGLR_CNF1_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGLR_CNF2 ((uint32_t)0x00000C00) /* CNF2[1:0] bits (Port x configuration bits, pin 2) */ +#define GPIO_CFGLR_CNF2_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGLR_CNF2_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGLR_CNF3 ((uint32_t)0x0000C000) /* CNF3[1:0] bits (Port x configuration bits, pin 3) */ +#define GPIO_CFGLR_CNF3_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGLR_CNF3_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF4 ((uint32_t)0x000C0000) /* CNF4[1:0] bits (Port x configuration bits, pin 4) */ +#define GPIO_CFGLR_CNF4_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGLR_CNF4_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF5 ((uint32_t)0x00C00000) /* CNF5[1:0] bits (Port x configuration bits, pin 5) */ +#define GPIO_CFGLR_CNF5_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGLR_CNF5_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF6 ((uint32_t)0x0C000000) /* CNF6[1:0] bits (Port x configuration bits, pin 6) */ +#define GPIO_CFGLR_CNF6_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF6_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGLR_CNF7 ((uint32_t)0xC0000000) /* CNF7[1:0] bits (Port x configuration bits, pin 7) */ +#define GPIO_CFGLR_CNF7_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGLR_CNF7_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_CFGHR register *******************/ +#define GPIO_CFGHR_MODE ((uint32_t)0x33333333) /* Port x mode bits */ + +#define GPIO_CFGHR_MODE8 ((uint32_t)0x00000003) /* MODE8[1:0] bits (Port x mode bits, pin 8) */ +#define GPIO_CFGHR_MODE8_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define GPIO_CFGHR_MODE8_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define GPIO_CFGHR_MODE9 ((uint32_t)0x00000030) /* MODE9[1:0] bits (Port x mode bits, pin 9) */ +#define GPIO_CFGHR_MODE9_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define GPIO_CFGHR_MODE9_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define GPIO_CFGHR_MODE10 ((uint32_t)0x00000300) /* MODE10[1:0] bits (Port x mode bits, pin 10) */ +#define GPIO_CFGHR_MODE10_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define GPIO_CFGHR_MODE10_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define GPIO_CFGHR_MODE11 ((uint32_t)0x00003000) /* MODE11[1:0] bits (Port x mode bits, pin 11) */ +#define GPIO_CFGHR_MODE11_0 ((uint32_t)0x00001000) /* Bit 0 */ +#define GPIO_CFGHR_MODE11_1 ((uint32_t)0x00002000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE12 ((uint32_t)0x00030000) /* MODE12[1:0] bits (Port x mode bits, pin 12) */ +#define GPIO_CFGHR_MODE12_0 ((uint32_t)0x00010000) /* Bit 0 */ +#define GPIO_CFGHR_MODE12_1 ((uint32_t)0x00020000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE13 ((uint32_t)0x00300000) /* MODE13[1:0] bits (Port x mode bits, pin 13) */ +#define GPIO_CFGHR_MODE13_0 ((uint32_t)0x00100000) /* Bit 0 */ +#define GPIO_CFGHR_MODE13_1 ((uint32_t)0x00200000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE14 ((uint32_t)0x03000000) /* MODE14[1:0] bits (Port x mode bits, pin 14) */ +#define GPIO_CFGHR_MODE14_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define GPIO_CFGHR_MODE14_1 ((uint32_t)0x02000000) /* Bit 1 */ + +#define GPIO_CFGHR_MODE15 ((uint32_t)0x30000000) /* MODE15[1:0] bits (Port x mode bits, pin 15) */ +#define GPIO_CFGHR_MODE15_0 ((uint32_t)0x10000000) /* Bit 0 */ +#define GPIO_CFGHR_MODE15_1 ((uint32_t)0x20000000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF ((uint32_t)0xCCCCCCCC) /* Port x configuration bits */ + +#define GPIO_CFGHR_CNF8 ((uint32_t)0x0000000C) /* CNF8[1:0] bits (Port x configuration bits, pin 8) */ +#define GPIO_CFGHR_CNF8_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define GPIO_CFGHR_CNF8_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define GPIO_CFGHR_CNF9 ((uint32_t)0x000000C0) /* CNF9[1:0] bits (Port x configuration bits, pin 9) */ +#define GPIO_CFGHR_CNF9_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define GPIO_CFGHR_CNF9_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define GPIO_CFGHR_CNF10 ((uint32_t)0x00000C00) /* CNF10[1:0] bits (Port x configuration bits, pin 10) */ +#define GPIO_CFGHR_CNF10_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define GPIO_CFGHR_CNF10_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define GPIO_CFGHR_CNF11 ((uint32_t)0x0000C000) /* CNF11[1:0] bits (Port x configuration bits, pin 11) */ +#define GPIO_CFGHR_CNF11_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define GPIO_CFGHR_CNF11_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF12 ((uint32_t)0x000C0000) /* CNF12[1:0] bits (Port x configuration bits, pin 12) */ +#define GPIO_CFGHR_CNF12_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define GPIO_CFGHR_CNF12_1 ((uint32_t)0x00080000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF13 ((uint32_t)0x00C00000) /* CNF13[1:0] bits (Port x configuration bits, pin 13) */ +#define GPIO_CFGHR_CNF13_0 ((uint32_t)0x00400000) /* Bit 0 */ +#define GPIO_CFGHR_CNF13_1 ((uint32_t)0x00800000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF14 ((uint32_t)0x0C000000) /* CNF14[1:0] bits (Port x configuration bits, pin 14) */ +#define GPIO_CFGHR_CNF14_0 ((uint32_t)0x04000000) /* Bit 0 */ +#define GPIO_CFGHR_CNF14_1 ((uint32_t)0x08000000) /* Bit 1 */ + +#define GPIO_CFGHR_CNF15 ((uint32_t)0xC0000000) /* CNF15[1:0] bits (Port x configuration bits, pin 15) */ +#define GPIO_CFGHR_CNF15_0 ((uint32_t)0x40000000) /* Bit 0 */ +#define GPIO_CFGHR_CNF15_1 ((uint32_t)0x80000000) /* Bit 1 */ + +/******************* Bit definition for GPIO_INDR register *******************/ +#define GPIO_INDR_IDR0 ((uint16_t)0x0001) /* Port input data, bit 0 */ +#define GPIO_INDR_IDR1 ((uint16_t)0x0002) /* Port input data, bit 1 */ +#define GPIO_INDR_IDR2 ((uint16_t)0x0004) /* Port input data, bit 2 */ +#define GPIO_INDR_IDR3 ((uint16_t)0x0008) /* Port input data, bit 3 */ +#define GPIO_INDR_IDR4 ((uint16_t)0x0010) /* Port input data, bit 4 */ +#define GPIO_INDR_IDR5 ((uint16_t)0x0020) /* Port input data, bit 5 */ +#define GPIO_INDR_IDR6 ((uint16_t)0x0040) /* Port input data, bit 6 */ +#define GPIO_INDR_IDR7 ((uint16_t)0x0080) /* Port input data, bit 7 */ +#define GPIO_INDR_IDR8 ((uint16_t)0x0100) /* Port input data, bit 8 */ +#define GPIO_INDR_IDR9 ((uint16_t)0x0200) /* Port input data, bit 9 */ +#define GPIO_INDR_IDR10 ((uint16_t)0x0400) /* Port input data, bit 10 */ +#define GPIO_INDR_IDR11 ((uint16_t)0x0800) /* Port input data, bit 11 */ +#define GPIO_INDR_IDR12 ((uint16_t)0x1000) /* Port input data, bit 12 */ +#define GPIO_INDR_IDR13 ((uint16_t)0x2000) /* Port input data, bit 13 */ +#define GPIO_INDR_IDR14 ((uint16_t)0x4000) /* Port input data, bit 14 */ +#define GPIO_INDR_IDR15 ((uint16_t)0x8000) /* Port input data, bit 15 */ + +/******************* Bit definition for GPIO_OUTDR register *******************/ +#define GPIO_OUTDR_ODR0 ((uint16_t)0x0001) /* Port output data, bit 0 */ +#define GPIO_OUTDR_ODR1 ((uint16_t)0x0002) /* Port output data, bit 1 */ +#define GPIO_OUTDR_ODR2 ((uint16_t)0x0004) /* Port output data, bit 2 */ +#define GPIO_OUTDR_ODR3 ((uint16_t)0x0008) /* Port output data, bit 3 */ +#define GPIO_OUTDR_ODR4 ((uint16_t)0x0010) /* Port output data, bit 4 */ +#define GPIO_OUTDR_ODR5 ((uint16_t)0x0020) /* Port output data, bit 5 */ +#define GPIO_OUTDR_ODR6 ((uint16_t)0x0040) /* Port output data, bit 6 */ +#define GPIO_OUTDR_ODR7 ((uint16_t)0x0080) /* Port output data, bit 7 */ +#define GPIO_OUTDR_ODR8 ((uint16_t)0x0100) /* Port output data, bit 8 */ +#define GPIO_OUTDR_ODR9 ((uint16_t)0x0200) /* Port output data, bit 9 */ +#define GPIO_OUTDR_ODR10 ((uint16_t)0x0400) /* Port output data, bit 10 */ +#define GPIO_OUTDR_ODR11 ((uint16_t)0x0800) /* Port output data, bit 11 */ +#define GPIO_OUTDR_ODR12 ((uint16_t)0x1000) /* Port output data, bit 12 */ +#define GPIO_OUTDR_ODR13 ((uint16_t)0x2000) /* Port output data, bit 13 */ +#define GPIO_OUTDR_ODR14 ((uint16_t)0x4000) /* Port output data, bit 14 */ +#define GPIO_OUTDR_ODR15 ((uint16_t)0x8000) /* Port output data, bit 15 */ + +/****************** Bit definition for GPIO_BSHR register *******************/ +#define GPIO_BSHR_BS0 ((uint32_t)0x00000001) /* Port x Set bit 0 */ +#define GPIO_BSHR_BS1 ((uint32_t)0x00000002) /* Port x Set bit 1 */ +#define GPIO_BSHR_BS2 ((uint32_t)0x00000004) /* Port x Set bit 2 */ +#define GPIO_BSHR_BS3 ((uint32_t)0x00000008) /* Port x Set bit 3 */ +#define GPIO_BSHR_BS4 ((uint32_t)0x00000010) /* Port x Set bit 4 */ +#define GPIO_BSHR_BS5 ((uint32_t)0x00000020) /* Port x Set bit 5 */ +#define GPIO_BSHR_BS6 ((uint32_t)0x00000040) /* Port x Set bit 6 */ +#define GPIO_BSHR_BS7 ((uint32_t)0x00000080) /* Port x Set bit 7 */ +#define GPIO_BSHR_BS8 ((uint32_t)0x00000100) /* Port x Set bit 8 */ +#define GPIO_BSHR_BS9 ((uint32_t)0x00000200) /* Port x Set bit 9 */ +#define GPIO_BSHR_BS10 ((uint32_t)0x00000400) /* Port x Set bit 10 */ +#define GPIO_BSHR_BS11 ((uint32_t)0x00000800) /* Port x Set bit 11 */ +#define GPIO_BSHR_BS12 ((uint32_t)0x00001000) /* Port x Set bit 12 */ +#define GPIO_BSHR_BS13 ((uint32_t)0x00002000) /* Port x Set bit 13 */ +#define GPIO_BSHR_BS14 ((uint32_t)0x00004000) /* Port x Set bit 14 */ +#define GPIO_BSHR_BS15 ((uint32_t)0x00008000) /* Port x Set bit 15 */ + +#define GPIO_BSHR_BR0 ((uint32_t)0x00010000) /* Port x Reset bit 0 */ +#define GPIO_BSHR_BR1 ((uint32_t)0x00020000) /* Port x Reset bit 1 */ +#define GPIO_BSHR_BR2 ((uint32_t)0x00040000) /* Port x Reset bit 2 */ +#define GPIO_BSHR_BR3 ((uint32_t)0x00080000) /* Port x Reset bit 3 */ +#define GPIO_BSHR_BR4 ((uint32_t)0x00100000) /* Port x Reset bit 4 */ +#define GPIO_BSHR_BR5 ((uint32_t)0x00200000) /* Port x Reset bit 5 */ +#define GPIO_BSHR_BR6 ((uint32_t)0x00400000) /* Port x Reset bit 6 */ +#define GPIO_BSHR_BR7 ((uint32_t)0x00800000) /* Port x Reset bit 7 */ +#define GPIO_BSHR_BR8 ((uint32_t)0x01000000) /* Port x Reset bit 8 */ +#define GPIO_BSHR_BR9 ((uint32_t)0x02000000) /* Port x Reset bit 9 */ +#define GPIO_BSHR_BR10 ((uint32_t)0x04000000) /* Port x Reset bit 10 */ +#define GPIO_BSHR_BR11 ((uint32_t)0x08000000) /* Port x Reset bit 11 */ +#define GPIO_BSHR_BR12 ((uint32_t)0x10000000) /* Port x Reset bit 12 */ +#define GPIO_BSHR_BR13 ((uint32_t)0x20000000) /* Port x Reset bit 13 */ +#define GPIO_BSHR_BR14 ((uint32_t)0x40000000) /* Port x Reset bit 14 */ +#define GPIO_BSHR_BR15 ((uint32_t)0x80000000) /* Port x Reset bit 15 */ + +/******************* Bit definition for GPIO_BCR register *******************/ +#define GPIO_BCR_BR0 ((uint16_t)0x0001) /* Port x Reset bit 0 */ +#define GPIO_BCR_BR1 ((uint16_t)0x0002) /* Port x Reset bit 1 */ +#define GPIO_BCR_BR2 ((uint16_t)0x0004) /* Port x Reset bit 2 */ +#define GPIO_BCR_BR3 ((uint16_t)0x0008) /* Port x Reset bit 3 */ +#define GPIO_BCR_BR4 ((uint16_t)0x0010) /* Port x Reset bit 4 */ +#define GPIO_BCR_BR5 ((uint16_t)0x0020) /* Port x Reset bit 5 */ +#define GPIO_BCR_BR6 ((uint16_t)0x0040) /* Port x Reset bit 6 */ +#define GPIO_BCR_BR7 ((uint16_t)0x0080) /* Port x Reset bit 7 */ +#define GPIO_BCR_BR8 ((uint16_t)0x0100) /* Port x Reset bit 8 */ +#define GPIO_BCR_BR9 ((uint16_t)0x0200) /* Port x Reset bit 9 */ +#define GPIO_BCR_BR10 ((uint16_t)0x0400) /* Port x Reset bit 10 */ +#define GPIO_BCR_BR11 ((uint16_t)0x0800) /* Port x Reset bit 11 */ +#define GPIO_BCR_BR12 ((uint16_t)0x1000) /* Port x Reset bit 12 */ +#define GPIO_BCR_BR13 ((uint16_t)0x2000) /* Port x Reset bit 13 */ +#define GPIO_BCR_BR14 ((uint16_t)0x4000) /* Port x Reset bit 14 */ +#define GPIO_BCR_BR15 ((uint16_t)0x8000) /* Port x Reset bit 15 */ + +/****************** Bit definition for GPIO_LCKR register *******************/ +#define GPIO_LCK0 ((uint32_t)0x00000001) /* Port x Lock bit 0 */ +#define GPIO_LCK1 ((uint32_t)0x00000002) /* Port x Lock bit 1 */ +#define GPIO_LCK2 ((uint32_t)0x00000004) /* Port x Lock bit 2 */ +#define GPIO_LCK3 ((uint32_t)0x00000008) /* Port x Lock bit 3 */ +#define GPIO_LCK4 ((uint32_t)0x00000010) /* Port x Lock bit 4 */ +#define GPIO_LCK5 ((uint32_t)0x00000020) /* Port x Lock bit 5 */ +#define GPIO_LCK6 ((uint32_t)0x00000040) /* Port x Lock bit 6 */ +#define GPIO_LCK7 ((uint32_t)0x00000080) /* Port x Lock bit 7 */ +#define GPIO_LCK8 ((uint32_t)0x00000100) /* Port x Lock bit 8 */ +#define GPIO_LCK9 ((uint32_t)0x00000200) /* Port x Lock bit 9 */ +#define GPIO_LCK10 ((uint32_t)0x00000400) /* Port x Lock bit 10 */ +#define GPIO_LCK11 ((uint32_t)0x00000800) /* Port x Lock bit 11 */ +#define GPIO_LCK12 ((uint32_t)0x00001000) /* Port x Lock bit 12 */ +#define GPIO_LCK13 ((uint32_t)0x00002000) /* Port x Lock bit 13 */ +#define GPIO_LCK14 ((uint32_t)0x00004000) /* Port x Lock bit 14 */ +#define GPIO_LCK15 ((uint32_t)0x00008000) /* Port x Lock bit 15 */ +#define GPIO_LCKK ((uint32_t)0x00010000) /* Lock key */ + +/****************** Bit definition for AFIO_ECR register *******************/ +#define AFIO_ECR_PIN ((uint8_t)0x0F) /* PIN[3:0] bits (Pin selection) */ +#define AFIO_ECR_PIN_0 ((uint8_t)0x01) /* Bit 0 */ +#define AFIO_ECR_PIN_1 ((uint8_t)0x02) /* Bit 1 */ +#define AFIO_ECR_PIN_2 ((uint8_t)0x04) /* Bit 2 */ +#define AFIO_ECR_PIN_3 ((uint8_t)0x08) /* Bit 3 */ + +#define AFIO_ECR_PIN_PX0 ((uint8_t)0x00) /* Pin 0 selected */ +#define AFIO_ECR_PIN_PX1 ((uint8_t)0x01) /* Pin 1 selected */ +#define AFIO_ECR_PIN_PX2 ((uint8_t)0x02) /* Pin 2 selected */ +#define AFIO_ECR_PIN_PX3 ((uint8_t)0x03) /* Pin 3 selected */ +#define AFIO_ECR_PIN_PX4 ((uint8_t)0x04) /* Pin 4 selected */ +#define AFIO_ECR_PIN_PX5 ((uint8_t)0x05) /* Pin 5 selected */ +#define AFIO_ECR_PIN_PX6 ((uint8_t)0x06) /* Pin 6 selected */ +#define AFIO_ECR_PIN_PX7 ((uint8_t)0x07) /* Pin 7 selected */ +#define AFIO_ECR_PIN_PX8 ((uint8_t)0x08) /* Pin 8 selected */ +#define AFIO_ECR_PIN_PX9 ((uint8_t)0x09) /* Pin 9 selected */ +#define AFIO_ECR_PIN_PX10 ((uint8_t)0x0A) /* Pin 10 selected */ +#define AFIO_ECR_PIN_PX11 ((uint8_t)0x0B) /* Pin 11 selected */ +#define AFIO_ECR_PIN_PX12 ((uint8_t)0x0C) /* Pin 12 selected */ +#define AFIO_ECR_PIN_PX13 ((uint8_t)0x0D) /* Pin 13 selected */ +#define AFIO_ECR_PIN_PX14 ((uint8_t)0x0E) /* Pin 14 selected */ +#define AFIO_ECR_PIN_PX15 ((uint8_t)0x0F) /* Pin 15 selected */ + +#define AFIO_ECR_PORT ((uint8_t)0x70) /* PORT[2:0] bits (Port selection) */ +#define AFIO_ECR_PORT_0 ((uint8_t)0x10) /* Bit 0 */ +#define AFIO_ECR_PORT_1 ((uint8_t)0x20) /* Bit 1 */ +#define AFIO_ECR_PORT_2 ((uint8_t)0x40) /* Bit 2 */ + +#define AFIO_ECR_PORT_PA ((uint8_t)0x00) /* Port A selected */ +#define AFIO_ECR_PORT_PB ((uint8_t)0x10) /* Port B selected */ +#define AFIO_ECR_PORT_PC ((uint8_t)0x20) /* Port C selected */ +#define AFIO_ECR_PORT_PD ((uint8_t)0x30) /* Port D selected */ +#define AFIO_ECR_PORT_PE ((uint8_t)0x40) /* Port E selected */ + +#define AFIO_ECR_EVOE ((uint8_t)0x80) /* Event Output Enable */ + +/****************** Bit definition for AFIO_PCFR1register *******************/ +#define AFIO_PCFR1_SPI1_REMAP ((uint32_t)0x00000001) /* SPI1 remapping */ +#define AFIO_PCFR1_I2C1_REMAP ((uint32_t)0x00000002) /* I2C1 remapping */ +#define AFIO_PCFR1_USART1_REMAP ((uint32_t)0x00000004) /* USART1 remapping */ +#define AFIO_PCFR1_USART2_REMAP ((uint32_t)0x00000008) /* USART2 remapping */ + +#define AFIO_PCFR1_USART3_REMAP ((uint32_t)0x00000030) /* USART3_REMAP[1:0] bits (USART3 remapping) */ +#define AFIO_PCFR1_USART3_REMAP_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define AFIO_PCFR1_USART3_REMAP_1 ((uint32_t)0x00000020) /* Bit 1 */ + +#define AFIO_PCFR1_USART3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (TX/PB10, RX/PB11, CK/PB12, CTS/PB13, RTS/PB14) */ +#define AFIO_PCFR1_USART3_REMAP_PARTIALREMAP ((uint32_t)0x00000010) /* Partial remap (TX/PC10, RX/PC11, CK/PC12, CTS/PB13, RTS/PB14) */ +#define AFIO_PCFR1_USART3_REMAP_FULLREMAP ((uint32_t)0x00000030) /* Full remap (TX/PD8, RX/PD9, CK/PD10, CTS/PD11, RTS/PD12) */ + +#define AFIO_PCFR1_TIM1_REMAP ((uint32_t)0x000000C0) /* TIM1_REMAP[1:0] bits (TIM1 remapping) */ +#define AFIO_PCFR1_TIM1_REMAP_0 ((uint32_t)0x00000040) /* Bit 0 */ +#define AFIO_PCFR1_TIM1_REMAP_1 ((uint32_t)0x00000080) /* Bit 1 */ + +#define AFIO_PCFR1_TIM1_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PB12, CH1N/PB13, CH2N/PB14, CH3N/PB15) */ +#define AFIO_PCFR1_TIM1_REMAP_PARTIALREMAP ((uint32_t)0x00000040) /* Partial remap (ETR/PA12, CH1/PA8, CH2/PA9, CH3/PA10, CH4/PA11, BKIN/PA6, CH1N/PA7, CH2N/PB0, CH3N/PB1) */ +#define AFIO_PCFR1_TIM1_REMAP_FULLREMAP ((uint32_t)0x000000C0) /* Full remap (ETR/PE7, CH1/PE9, CH2/PE11, CH3/PE13, CH4/PE14, BKIN/PE15, CH1N/PE8, CH2N/PE10, CH3N/PE12) */ + +#define AFIO_PCFR1_TIM2_REMAP ((uint32_t)0x00000300) /* TIM2_REMAP[1:0] bits (TIM2 remapping) */ +#define AFIO_PCFR1_TIM2_REMAP_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define AFIO_PCFR1_TIM2_REMAP_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define AFIO_PCFR1_TIM2_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/ETR/PA0, CH2/PA1, CH3/PA2, CH4/PA3) */ +#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP1 ((uint32_t)0x00000100) /* Partial remap (CH1/ETR/PA15, CH2/PB3, CH3/PA2, CH4/PA3) */ +#define AFIO_PCFR1_TIM2_REMAP_PARTIALREMAP2 ((uint32_t)0x00000200) /* Partial remap (CH1/ETR/PA0, CH2/PA1, CH3/PB10, CH4/PB11) */ +#define AFIO_PCFR1_TIM2_REMAP_FULLREMAP ((uint32_t)0x00000300) /* Full remap (CH1/ETR/PA15, CH2/PB3, CH3/PB10, CH4/PB11) */ + +#define AFIO_PCFR1_TIM3_REMAP ((uint32_t)0x00000C00) /* TIM3_REMAP[1:0] bits (TIM3 remapping) */ +#define AFIO_PCFR1_TIM3_REMAP_0 ((uint32_t)0x00000400) /* Bit 0 */ +#define AFIO_PCFR1_TIM3_REMAP_1 ((uint32_t)0x00000800) /* Bit 1 */ + +#define AFIO_PCFR1_TIM3_REMAP_NOREMAP ((uint32_t)0x00000000) /* No remap (CH1/PA6, CH2/PA7, CH3/PB0, CH4/PB1) */ +#define AFIO_PCFR1_TIM3_REMAP_PARTIALREMAP ((uint32_t)0x00000800) /* Partial remap (CH1/PB4, CH2/PB5, CH3/PB0, CH4/PB1) */ +#define AFIO_PCFR1_TIM3_REMAP_FULLREMAP ((uint32_t)0x00000C00) /* Full remap (CH1/PC6, CH2/PC7, CH3/PC8, CH4/PC9) */ + +#define AFIO_PCFR1_TIM4_REMAP ((uint32_t)0x00001000) /* TIM4_REMAP bit (TIM4 remapping) */ + +#define AFIO_PCFR1_CAN_REMAP ((uint32_t)0x00006000) /* CAN_REMAP[1:0] bits (CAN Alternate function remapping) */ +#define AFIO_PCFR1_CAN_REMAP_0 ((uint32_t)0x00002000) /* Bit 0 */ +#define AFIO_PCFR1_CAN_REMAP_1 ((uint32_t)0x00004000) /* Bit 1 */ + +#define AFIO_PCFR1_CAN_REMAP_REMAP1 ((uint32_t)0x00000000) /* CANRX mapped to PA11, CANTX mapped to PA12 */ +#define AFIO_PCFR1_CAN_REMAP_REMAP2 ((uint32_t)0x00004000) /* CANRX mapped to PB8, CANTX mapped to PB9 */ +#define AFIO_PCFR1_CAN_REMAP_REMAP3 ((uint32_t)0x00006000) /* CANRX mapped to PD0, CANTX mapped to PD1 */ + +#define AFIO_PCFR1_PD01_REMAP ((uint32_t)0x00008000) /* Port D0/Port D1 mapping on OSC_IN/OSC_OUT */ +#define AFIO_PCFR1_TIM5CH4_IREMAP ((uint32_t)0x00010000) /* TIM5 Channel4 Internal Remap */ +#define AFIO_PCFR1_ADC1_ETRGINJ_REMAP ((uint32_t)0x00020000) /* ADC 1 External Trigger Injected Conversion remapping */ +#define AFIO_PCFR1_ADC1_ETRGREG_REMAP ((uint32_t)0x00040000) /* ADC 1 External Trigger Regular Conversion remapping */ +#define AFIO_PCFR1_ADC2_ETRGINJ_REMAP ((uint32_t)0x00080000) /* ADC 2 External Trigger Injected Conversion remapping */ +#define AFIO_PCFR1_ADC2_ETRGREG_REMAP ((uint32_t)0x00100000) /* ADC 2 External Trigger Regular Conversion remapping */ + +#define AFIO_PCFR1_SWJ_CFG ((uint32_t)0x07000000) /* SWJ_CFG[2:0] bits (Serial Wire JTAG configuration) */ +#define AFIO_PCFR1_SWJ_CFG_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define AFIO_PCFR1_SWJ_CFG_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define AFIO_PCFR1_SWJ_CFG_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define AFIO_PCFR1_SWJ_CFG_RESET ((uint32_t)0x00000000) +#define AFIO_PCFR1_SWJ_CFG_DISABLE ((uint32_t)0x04000000) + +/***************** Bit definition for AFIO_EXTICR1 register *****************/ +#define AFIO_EXTICR1_EXTI0 ((uint16_t)0x000F) /* EXTI 0 configuration */ +#define AFIO_EXTICR1_EXTI1 ((uint16_t)0x00F0) /* EXTI 1 configuration */ +#define AFIO_EXTICR1_EXTI2 ((uint16_t)0x0F00) /* EXTI 2 configuration */ +#define AFIO_EXTICR1_EXTI3 ((uint16_t)0xF000) /* EXTI 3 configuration */ + +#define AFIO_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /* PA[0] pin */ +#define AFIO_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /* PB[0] pin */ +#define AFIO_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /* PC[0] pin */ +#define AFIO_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /* PD[0] pin */ +#define AFIO_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /* PE[0] pin */ +#define AFIO_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /* PF[0] pin */ +#define AFIO_EXTICR1_EXTI0_PG ((uint16_t)0x0006) /* PG[0] pin */ + +#define AFIO_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /* PA[1] pin */ +#define AFIO_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /* PB[1] pin */ +#define AFIO_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /* PC[1] pin */ +#define AFIO_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /* PD[1] pin */ +#define AFIO_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /* PE[1] pin */ +#define AFIO_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /* PF[1] pin */ +#define AFIO_EXTICR1_EXTI1_PG ((uint16_t)0x0060) /* PG[1] pin */ + +#define AFIO_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /* PA[2] pin */ +#define AFIO_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /* PB[2] pin */ +#define AFIO_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /* PC[2] pin */ +#define AFIO_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /* PD[2] pin */ +#define AFIO_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /* PE[2] pin */ +#define AFIO_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /* PF[2] pin */ +#define AFIO_EXTICR1_EXTI2_PG ((uint16_t)0x0600) /* PG[2] pin */ + +#define AFIO_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /* PA[3] pin */ +#define AFIO_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /* PB[3] pin */ +#define AFIO_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /* PC[3] pin */ +#define AFIO_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /* PD[3] pin */ +#define AFIO_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /* PE[3] pin */ +#define AFIO_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /* PF[3] pin */ +#define AFIO_EXTICR1_EXTI3_PG ((uint16_t)0x6000) /* PG[3] pin */ + +/***************** Bit definition for AFIO_EXTICR2 register *****************/ +#define AFIO_EXTICR2_EXTI4 ((uint16_t)0x000F) /* EXTI 4 configuration */ +#define AFIO_EXTICR2_EXTI5 ((uint16_t)0x00F0) /* EXTI 5 configuration */ +#define AFIO_EXTICR2_EXTI6 ((uint16_t)0x0F00) /* EXTI 6 configuration */ +#define AFIO_EXTICR2_EXTI7 ((uint16_t)0xF000) /* EXTI 7 configuration */ + +#define AFIO_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /* PA[4] pin */ +#define AFIO_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /* PB[4] pin */ +#define AFIO_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /* PC[4] pin */ +#define AFIO_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /* PD[4] pin */ +#define AFIO_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /* PE[4] pin */ +#define AFIO_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /* PF[4] pin */ +#define AFIO_EXTICR2_EXTI4_PG ((uint16_t)0x0006) /* PG[4] pin */ + +#define AFIO_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /* PA[5] pin */ +#define AFIO_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /* PB[5] pin */ +#define AFIO_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /* PC[5] pin */ +#define AFIO_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /* PD[5] pin */ +#define AFIO_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /* PE[5] pin */ +#define AFIO_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /* PF[5] pin */ +#define AFIO_EXTICR2_EXTI5_PG ((uint16_t)0x0060) /* PG[5] pin */ + +#define AFIO_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /* PA[6] pin */ +#define AFIO_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /* PB[6] pin */ +#define AFIO_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /* PC[6] pin */ +#define AFIO_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /* PD[6] pin */ +#define AFIO_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /* PE[6] pin */ +#define AFIO_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /* PF[6] pin */ +#define AFIO_EXTICR2_EXTI6_PG ((uint16_t)0x0600) /* PG[6] pin */ + +#define AFIO_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /* PA[7] pin */ +#define AFIO_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /* PB[7] pin */ +#define AFIO_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /* PC[7] pin */ +#define AFIO_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /* PD[7] pin */ +#define AFIO_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /* PE[7] pin */ +#define AFIO_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /* PF[7] pin */ +#define AFIO_EXTICR2_EXTI7_PG ((uint16_t)0x6000) /* PG[7] pin */ + +/***************** Bit definition for AFIO_EXTICR3 register *****************/ +#define AFIO_EXTICR3_EXTI8 ((uint16_t)0x000F) /* EXTI 8 configuration */ +#define AFIO_EXTICR3_EXTI9 ((uint16_t)0x00F0) /* EXTI 9 configuration */ +#define AFIO_EXTICR3_EXTI10 ((uint16_t)0x0F00) /* EXTI 10 configuration */ +#define AFIO_EXTICR3_EXTI11 ((uint16_t)0xF000) /* EXTI 11 configuration */ + +#define AFIO_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /* PA[8] pin */ +#define AFIO_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /* PB[8] pin */ +#define AFIO_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /* PC[8] pin */ +#define AFIO_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /* PD[8] pin */ +#define AFIO_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /* PE[8] pin */ +#define AFIO_EXTICR3_EXTI8_PF ((uint16_t)0x0005) /* PF[8] pin */ +#define AFIO_EXTICR3_EXTI8_PG ((uint16_t)0x0006) /* PG[8] pin */ + +#define AFIO_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /* PA[9] pin */ +#define AFIO_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /* PB[9] pin */ +#define AFIO_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /* PC[9] pin */ +#define AFIO_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /* PD[9] pin */ +#define AFIO_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /* PE[9] pin */ +#define AFIO_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /* PF[9] pin */ +#define AFIO_EXTICR3_EXTI9_PG ((uint16_t)0x0060) /* PG[9] pin */ + +#define AFIO_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /* PA[10] pin */ +#define AFIO_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /* PB[10] pin */ +#define AFIO_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /* PC[10] pin */ +#define AFIO_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /* PD[10] pin */ +#define AFIO_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /* PE[10] pin */ +#define AFIO_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /* PF[10] pin */ +#define AFIO_EXTICR3_EXTI10_PG ((uint16_t)0x0600) /* PG[10] pin */ + +#define AFIO_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /* PA[11] pin */ +#define AFIO_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /* PB[11] pin */ +#define AFIO_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /* PC[11] pin */ +#define AFIO_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /* PD[11] pin */ +#define AFIO_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /* PE[11] pin */ +#define AFIO_EXTICR3_EXTI11_PF ((uint16_t)0x5000) /* PF[11] pin */ +#define AFIO_EXTICR3_EXTI11_PG ((uint16_t)0x6000) /* PG[11] pin */ + +/***************** Bit definition for AFIO_EXTICR4 register *****************/ +#define AFIO_EXTICR4_EXTI12 ((uint16_t)0x000F) /* EXTI 12 configuration */ +#define AFIO_EXTICR4_EXTI13 ((uint16_t)0x00F0) /* EXTI 13 configuration */ +#define AFIO_EXTICR4_EXTI14 ((uint16_t)0x0F00) /* EXTI 14 configuration */ +#define AFIO_EXTICR4_EXTI15 ((uint16_t)0xF000) /* EXTI 15 configuration */ + +#define AFIO_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /* PA[12] pin */ +#define AFIO_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /* PB[12] pin */ +#define AFIO_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /* PC[12] pin */ +#define AFIO_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /* PD[12] pin */ +#define AFIO_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /* PE[12] pin */ +#define AFIO_EXTICR4_EXTI12_PF ((uint16_t)0x0005) /* PF[12] pin */ +#define AFIO_EXTICR4_EXTI12_PG ((uint16_t)0x0006) /* PG[12] pin */ + +#define AFIO_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /* PA[13] pin */ +#define AFIO_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /* PB[13] pin */ +#define AFIO_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /* PC[13] pin */ +#define AFIO_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /* PD[13] pin */ +#define AFIO_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /* PE[13] pin */ +#define AFIO_EXTICR4_EXTI13_PF ((uint16_t)0x0050) /* PF[13] pin */ +#define AFIO_EXTICR4_EXTI13_PG ((uint16_t)0x0060) /* PG[13] pin */ + +#define AFIO_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /* PA[14] pin */ +#define AFIO_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /* PB[14] pin */ +#define AFIO_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /* PC[14] pin */ +#define AFIO_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /* PD[14] pin */ +#define AFIO_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /* PE[14] pin */ +#define AFIO_EXTICR4_EXTI14_PF ((uint16_t)0x0500) /* PF[14] pin */ +#define AFIO_EXTICR4_EXTI14_PG ((uint16_t)0x0600) /* PG[14] pin */ + +#define AFIO_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /* PA[15] pin */ +#define AFIO_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /* PB[15] pin */ +#define AFIO_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /* PC[15] pin */ +#define AFIO_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /* PD[15] pin */ +#define AFIO_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /* PE[15] pin */ +#define AFIO_EXTICR4_EXTI15_PF ((uint16_t)0x5000) /* PF[15] pin */ +#define AFIO_EXTICR4_EXTI15_PG ((uint16_t)0x6000) /* PG[15] pin */ + +/******************************************************************************/ +/* Independent WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for IWDG_CTLR register ********************/ +#define IWDG_KEY ((uint16_t)0xFFFF) /* Key value (write only, read 0000h) */ + +/******************* Bit definition for IWDG_PSCR register ********************/ +#define IWDG_PR ((uint8_t)0x07) /* PR[2:0] (Prescaler divider) */ +#define IWDG_PR_0 ((uint8_t)0x01) /* Bit 0 */ +#define IWDG_PR_1 ((uint8_t)0x02) /* Bit 1 */ +#define IWDG_PR_2 ((uint8_t)0x04) /* Bit 2 */ + +/******************* Bit definition for IWDG_RLDR register *******************/ +#define IWDG_RL ((uint16_t)0x0FFF) /* Watchdog counter reload value */ + +/******************* Bit definition for IWDG_STATR register ********************/ +#define IWDG_PVU ((uint8_t)0x01) /* Watchdog prescaler value update */ +#define IWDG_RVU ((uint8_t)0x02) /* Watchdog counter reload value update */ + +/******************************************************************************/ +/* Inter-integrated Circuit Interface */ +/******************************************************************************/ + +/******************* Bit definition for I2C_CTLR1 register ********************/ +#define I2C_CTLR1_PE ((uint16_t)0x0001) /* Peripheral Enable */ +#define I2C_CTLR1_SMBUS ((uint16_t)0x0002) /* SMBus Mode */ +#define I2C_CTLR1_SMBTYPE ((uint16_t)0x0008) /* SMBus Type */ +#define I2C_CTLR1_ENARP ((uint16_t)0x0010) /* ARP Enable */ +#define I2C_CTLR1_ENPEC ((uint16_t)0x0020) /* PEC Enable */ +#define I2C_CTLR1_ENGC ((uint16_t)0x0040) /* General Call Enable */ +#define I2C_CTLR1_NOSTRETCH ((uint16_t)0x0080) /* Clock Stretching Disable (Slave mode) */ +#define I2C_CTLR1_START ((uint16_t)0x0100) /* Start Generation */ +#define I2C_CTLR1_STOP ((uint16_t)0x0200) /* Stop Generation */ +#define I2C_CTLR1_ACK ((uint16_t)0x0400) /* Acknowledge Enable */ +#define I2C_CTLR1_POS ((uint16_t)0x0800) /* Acknowledge/PEC Position (for data reception) */ +#define I2C_CTLR1_PEC ((uint16_t)0x1000) /* Packet Error Checking */ +#define I2C_CTLR1_ALERT ((uint16_t)0x2000) /* SMBus Alert */ +#define I2C_CTLR1_SWRST ((uint16_t)0x8000) /* Software Reset */ + +/******************* Bit definition for I2C_CTLR2 register ********************/ +#define I2C_CTLR2_FREQ ((uint16_t)0x003F) /* FREQ[5:0] bits (Peripheral Clock Frequency) */ +#define I2C_CTLR2_FREQ_0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_CTLR2_FREQ_1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_CTLR2_FREQ_2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_CTLR2_FREQ_3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_CTLR2_FREQ_4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_CTLR2_FREQ_5 ((uint16_t)0x0020) /* Bit 5 */ + +#define I2C_CTLR2_ITERREN ((uint16_t)0x0100) /* Error Interrupt Enable */ +#define I2C_CTLR2_ITEVTEN ((uint16_t)0x0200) /* Event Interrupt Enable */ +#define I2C_CTLR2_ITBUFEN ((uint16_t)0x0400) /* Buffer Interrupt Enable */ +#define I2C_CTLR2_DMAEN ((uint16_t)0x0800) /* DMA Requests Enable */ +#define I2C_CTLR2_LAST ((uint16_t)0x1000) /* DMA Last Transfer */ + +/******************* Bit definition for I2C_OADDR1 register *******************/ +#define I2C_OADDR1_ADD1_7 ((uint16_t)0x00FE) /* Interface Address */ +#define I2C_OADDR1_ADD8_9 ((uint16_t)0x0300) /* Interface Address */ + +#define I2C_OADDR1_ADD0 ((uint16_t)0x0001) /* Bit 0 */ +#define I2C_OADDR1_ADD1 ((uint16_t)0x0002) /* Bit 1 */ +#define I2C_OADDR1_ADD2 ((uint16_t)0x0004) /* Bit 2 */ +#define I2C_OADDR1_ADD3 ((uint16_t)0x0008) /* Bit 3 */ +#define I2C_OADDR1_ADD4 ((uint16_t)0x0010) /* Bit 4 */ +#define I2C_OADDR1_ADD5 ((uint16_t)0x0020) /* Bit 5 */ +#define I2C_OADDR1_ADD6 ((uint16_t)0x0040) /* Bit 6 */ +#define I2C_OADDR1_ADD7 ((uint16_t)0x0080) /* Bit 7 */ +#define I2C_OADDR1_ADD8 ((uint16_t)0x0100) /* Bit 8 */ +#define I2C_OADDR1_ADD9 ((uint16_t)0x0200) /* Bit 9 */ + +#define I2C_OADDR1_ADDMODE ((uint16_t)0x8000) /* Addressing Mode (Slave mode) */ + +/******************* Bit definition for I2C_OADDR2 register *******************/ +#define I2C_OADDR2_ENDUAL ((uint8_t)0x01) /* Dual addressing mode enable */ +#define I2C_OADDR2_ADD2 ((uint8_t)0xFE) /* Interface address */ + +/******************** Bit definition for I2C_DATAR register ********************/ +#define I2C_DR_DATAR ((uint8_t)0xFF) /* 8-bit Data Register */ + +/******************* Bit definition for I2C_STAR1 register ********************/ +#define I2C_STAR1_SB ((uint16_t)0x0001) /* Start Bit (Master mode) */ +#define I2C_STAR1_ADDR ((uint16_t)0x0002) /* Address sent (master mode)/matched (slave mode) */ +#define I2C_STAR1_BTF ((uint16_t)0x0004) /* Byte Transfer Finished */ +#define I2C_STAR1_ADD10 ((uint16_t)0x0008) /* 10-bit header sent (Master mode) */ +#define I2C_STAR1_STOPF ((uint16_t)0x0010) /* Stop detection (Slave mode) */ +#define I2C_STAR1_RXNE ((uint16_t)0x0040) /* Data Register not Empty (receivers) */ +#define I2C_STAR1_TXE ((uint16_t)0x0080) /* Data Register Empty (transmitters) */ +#define I2C_STAR1_BERR ((uint16_t)0x0100) /* Bus Error */ +#define I2C_STAR1_ARLO ((uint16_t)0x0200) /* Arbitration Lost (master mode) */ +#define I2C_STAR1_AF ((uint16_t)0x0400) /* Acknowledge Failure */ +#define I2C_STAR1_OVR ((uint16_t)0x0800) /* Overrun/Underrun */ +#define I2C_STAR1_PECERR ((uint16_t)0x1000) /* PEC Error in reception */ +#define I2C_STAR1_TIMEOUT ((uint16_t)0x4000) /* Timeout or Tlow Error */ +#define I2C_STAR1_SMBALERT ((uint16_t)0x8000) /* SMBus Alert */ + +/******************* Bit definition for I2C_STAR2 register ********************/ +#define I2C_STAR2_MSL ((uint16_t)0x0001) /* Master/Slave */ +#define I2C_STAR2_BUSY ((uint16_t)0x0002) /* Bus Busy */ +#define I2C_STAR2_TRA ((uint16_t)0x0004) /* Transmitter/Receiver */ +#define I2C_STAR2_GENCALL ((uint16_t)0x0010) /* General Call Address (Slave mode) */ +#define I2C_STAR2_SMBDEFAULT ((uint16_t)0x0020) /* SMBus Device Default Address (Slave mode) */ +#define I2C_STAR2_SMBHOST ((uint16_t)0x0040) /* SMBus Host Header (Slave mode) */ +#define I2C_STAR2_DUALF ((uint16_t)0x0080) /* Dual Flag (Slave mode) */ +#define I2C_STAR2_PEC ((uint16_t)0xFF00) /* Packet Error Checking Register */ + +/******************* Bit definition for I2C_CKCFGR register ********************/ +#define I2C_CKCFGR_CCR ((uint16_t)0x0FFF) /* Clock Control Register in Fast/Standard mode (Master mode) */ +#define I2C_CKCFGR_DUTY ((uint16_t)0x4000) /* Fast Mode Duty Cycle */ +#define I2C_CKCFGR_FS ((uint16_t)0x8000) /* I2C Master Mode Selection */ + +/****************** Bit definition for I2C_RTR register *******************/ +#define I2C_RTR_TRISE ((uint8_t)0x3F) /* Maximum Rise Time in Fast/Standard mode (Master mode) */ + +/******************************************************************************/ +/* Power Control */ +/******************************************************************************/ + +/******************** Bit definition for PWR_CTLR register ********************/ +#define PWR_CTLR_LPDS ((uint16_t)0x0001) /* Low-Power Deepsleep */ +#define PWR_CTLR_PDDS ((uint16_t)0x0002) /* Power Down Deepsleep */ +#define PWR_CTLR_CWUF ((uint16_t)0x0004) /* Clear Wakeup Flag */ +#define PWR_CTLR_CSBF ((uint16_t)0x0008) /* Clear Standby Flag */ +#define PWR_CTLR_PVDE ((uint16_t)0x0010) /* Power Voltage Detector Enable */ + +#define PWR_CTLR_PLS ((uint16_t)0x00E0) /* PLS[2:0] bits (PVD Level Selection) */ +#define PWR_CTLR_PLS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define PWR_CTLR_PLS_1 ((uint16_t)0x0040) /* Bit 1 */ +#define PWR_CTLR_PLS_2 ((uint16_t)0x0080) /* Bit 2 */ + +#define PWR_CTLR_PLS_MODE0 ((uint16_t)0x0000) +#define PWR_CTLR_PLS_MODE1 ((uint16_t)0x0020) +#define PWR_CTLR_PLS_MODE2 ((uint16_t)0x0040) +#define PWR_CTLR_PLS_MODE3 ((uint16_t)0x0060) +#define PWR_CTLR_PLS_MODE4 ((uint16_t)0x0080) +#define PWR_CTLR_PLS_MODE5 ((uint16_t)0x00A0) +#define PWR_CTLR_PLS_MODE6 ((uint16_t)0x00C0) +#define PWR_CTLR_PLS_MODE7 ((uint16_t)0x00E0) + +#define PWR_CTLR_PLS_2V2 PWR_CTLR_PLS_MODE0 +#define PWR_CTLR_PLS_2V3 PWR_CTLR_PLS_MODE1 +#define PWR_CTLR_PLS_2V4 PWR_CTLR_PLS_MODE2 +#define PWR_CTLR_PLS_2V5 PWR_CTLR_PLS_MODE3 +#define PWR_CTLR_PLS_2V6 PWR_CTLR_PLS_MODE4 +#define PWR_CTLR_PLS_2V7 PWR_CTLR_PLS_MODE5 +#define PWR_CTLR_PLS_2V8 PWR_CTLR_PLS_MODE6 +#define PWR_CTLR_PLS_2V9 PWR_CTLR_PLS_MODE7 + +#define PWR_CTLR_DBP ((uint16_t)0x0100) /* Disable Backup Domain write protection */ + +/******************* Bit definition for PWR_CSR register ********************/ +#define PWR_CSR_WUF ((uint16_t)0x0001) /* Wakeup Flag */ +#define PWR_CSR_SBF ((uint16_t)0x0002) /* Standby Flag */ +#define PWR_CSR_PVDO ((uint16_t)0x0004) /* PVD Output */ +#define PWR_CSR_EWUP ((uint16_t)0x0100) /* Enable WKUP pin */ + +/******************************************************************************/ +/* Reset and Clock Control */ +/******************************************************************************/ + +/******************** Bit definition for RCC_CTLR register ********************/ +#define RCC_HSION ((uint32_t)0x00000001) /* Internal High Speed clock enable */ +#define RCC_HSIRDY ((uint32_t)0x00000002) /* Internal High Speed clock ready flag */ +#define RCC_HSITRIM ((uint32_t)0x000000F8) /* Internal High Speed clock trimming */ +#define RCC_HSICAL ((uint32_t)0x0000FF00) /* Internal High Speed clock Calibration */ +#define RCC_HSEON ((uint32_t)0x00010000) /* External High Speed clock enable */ +#define RCC_HSERDY ((uint32_t)0x00020000) /* External High Speed clock ready flag */ +#define RCC_HSEBYP ((uint32_t)0x00040000) /* External High Speed clock Bypass */ +#define RCC_CSSON ((uint32_t)0x00080000) /* Clock Security System enable */ +#define RCC_PLLON ((uint32_t)0x01000000) /* PLL enable */ +#define RCC_PLLRDY ((uint32_t)0x02000000) /* PLL clock ready flag */ + +/******************* Bit definition for RCC_CFGR0 register *******************/ +#define RCC_SW ((uint32_t)0x00000003) /* SW[1:0] bits (System clock Switch) */ +#define RCC_SW_0 ((uint32_t)0x00000001) /* Bit 0 */ +#define RCC_SW_1 ((uint32_t)0x00000002) /* Bit 1 */ + +#define RCC_SW_HSI ((uint32_t)0x00000000) /* HSI selected as system clock */ +#define RCC_SW_HSE ((uint32_t)0x00000001) /* HSE selected as system clock */ +#define RCC_SW_PLL ((uint32_t)0x00000002) /* PLL selected as system clock */ + +#define RCC_SWS ((uint32_t)0x0000000C) /* SWS[1:0] bits (System Clock Switch Status) */ +#define RCC_SWS_0 ((uint32_t)0x00000004) /* Bit 0 */ +#define RCC_SWS_1 ((uint32_t)0x00000008) /* Bit 1 */ + +#define RCC_SWS_HSI ((uint32_t)0x00000000) /* HSI oscillator used as system clock */ +#define RCC_SWS_HSE ((uint32_t)0x00000004) /* HSE oscillator used as system clock */ +#define RCC_SWS_PLL ((uint32_t)0x00000008) /* PLL used as system clock */ + +#define RCC_HPRE ((uint32_t)0x000000F0) /* HPRE[3:0] bits (AHB prescaler) */ +#define RCC_HPRE_0 ((uint32_t)0x00000010) /* Bit 0 */ +#define RCC_HPRE_1 ((uint32_t)0x00000020) /* Bit 1 */ +#define RCC_HPRE_2 ((uint32_t)0x00000040) /* Bit 2 */ +#define RCC_HPRE_3 ((uint32_t)0x00000080) /* Bit 3 */ + +#define RCC_HPRE_DIV1 ((uint32_t)0x00000000) /* SYSCLK not divided */ +#define RCC_HPRE_DIV2 ((uint32_t)0x00000080) /* SYSCLK divided by 2 */ +#define RCC_HPRE_DIV4 ((uint32_t)0x00000090) /* SYSCLK divided by 4 */ +#define RCC_HPRE_DIV8 ((uint32_t)0x000000A0) /* SYSCLK divided by 8 */ +#define RCC_HPRE_DIV16 ((uint32_t)0x000000B0) /* SYSCLK divided by 16 */ +#define RCC_HPRE_DIV64 ((uint32_t)0x000000C0) /* SYSCLK divided by 64 */ +#define RCC_HPRE_DIV128 ((uint32_t)0x000000D0) /* SYSCLK divided by 128 */ +#define RCC_HPRE_DIV256 ((uint32_t)0x000000E0) /* SYSCLK divided by 256 */ +#define RCC_HPRE_DIV512 ((uint32_t)0x000000F0) /* SYSCLK divided by 512 */ + +#define RCC_PPRE1 ((uint32_t)0x00000700) /* PRE1[2:0] bits (APB1 prescaler) */ +#define RCC_PPRE1_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define RCC_PPRE1_1 ((uint32_t)0x00000200) /* Bit 1 */ +#define RCC_PPRE1_2 ((uint32_t)0x00000400) /* Bit 2 */ + +#define RCC_PPRE1_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */ +#define RCC_PPRE1_DIV2 ((uint32_t)0x00000400) /* HCLK divided by 2 */ +#define RCC_PPRE1_DIV4 ((uint32_t)0x00000500) /* HCLK divided by 4 */ +#define RCC_PPRE1_DIV8 ((uint32_t)0x00000600) /* HCLK divided by 8 */ +#define RCC_PPRE1_DIV16 ((uint32_t)0x00000700) /* HCLK divided by 16 */ + +#define RCC_PPRE2 ((uint32_t)0x00003800) /* PRE2[2:0] bits (APB2 prescaler) */ +#define RCC_PPRE2_0 ((uint32_t)0x00000800) /* Bit 0 */ +#define RCC_PPRE2_1 ((uint32_t)0x00001000) /* Bit 1 */ +#define RCC_PPRE2_2 ((uint32_t)0x00002000) /* Bit 2 */ + +#define RCC_PPRE2_DIV1 ((uint32_t)0x00000000) /* HCLK not divided */ +#define RCC_PPRE2_DIV2 ((uint32_t)0x00002000) /* HCLK divided by 2 */ +#define RCC_PPRE2_DIV4 ((uint32_t)0x00002800) /* HCLK divided by 4 */ +#define RCC_PPRE2_DIV8 ((uint32_t)0x00003000) /* HCLK divided by 8 */ +#define RCC_PPRE2_DIV16 ((uint32_t)0x00003800) /* HCLK divided by 16 */ + +#define RCC_ADCPRE ((uint32_t)0x0000C000) /* ADCPRE[1:0] bits (ADC prescaler) */ +#define RCC_ADCPRE_0 ((uint32_t)0x00004000) /* Bit 0 */ +#define RCC_ADCPRE_1 ((uint32_t)0x00008000) /* Bit 1 */ + +#define RCC_ADCPRE_DIV2 ((uint32_t)0x00000000) /* PCLK2 divided by 2 */ +#define RCC_ADCPRE_DIV4 ((uint32_t)0x00004000) /* PCLK2 divided by 4 */ +#define RCC_ADCPRE_DIV6 ((uint32_t)0x00008000) /* PCLK2 divided by 6 */ +#define RCC_ADCPRE_DIV8 ((uint32_t)0x0000C000) /* PCLK2 divided by 8 */ + +#define RCC_PLLSRC ((uint32_t)0x00010000) /* PLL entry clock source */ + +#define RCC_PLLXTPRE ((uint32_t)0x00020000) /* HSE divider for PLL entry */ + +#define RCC_PLLMULL ((uint32_t)0x003C0000) /* PLLMUL[3:0] bits (PLL multiplication factor) */ +#define RCC_PLLMULL_0 ((uint32_t)0x00040000) /* Bit 0 */ +#define RCC_PLLMULL_1 ((uint32_t)0x00080000) /* Bit 1 */ +#define RCC_PLLMULL_2 ((uint32_t)0x00100000) /* Bit 2 */ +#define RCC_PLLMULL_3 ((uint32_t)0x00200000) /* Bit 3 */ + +#define RCC_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /* HSI clock divided by 2 selected as PLL entry clock source */ +#define RCC_PLLSRC_HSE ((uint32_t)0x00010000) /* HSE clock selected as PLL entry clock source */ + +#define RCC_PLLXTPRE_HSE ((uint32_t)0x00000000) /* HSE clock not divided for PLL entry */ +#define RCC_PLLXTPRE_HSE_Div2 ((uint32_t)0x00020000) /* HSE clock divided by 2 for PLL entry */ + +#define RCC_PLLMULL2 ((uint32_t)0x00000000) /* PLL input clock*2 */ +#define RCC_PLLMULL3 ((uint32_t)0x00040000) /* PLL input clock*3 */ +#define RCC_PLLMULL4 ((uint32_t)0x00080000) /* PLL input clock*4 */ +#define RCC_PLLMULL5 ((uint32_t)0x000C0000) /* PLL input clock*5 */ +#define RCC_PLLMULL6 ((uint32_t)0x00100000) /* PLL input clock*6 */ +#define RCC_PLLMULL7 ((uint32_t)0x00140000) /* PLL input clock*7 */ +#define RCC_PLLMULL8 ((uint32_t)0x00180000) /* PLL input clock*8 */ +#define RCC_PLLMULL9 ((uint32_t)0x001C0000) /* PLL input clock*9 */ +#define RCC_PLLMULL10 ((uint32_t)0x00200000) /* PLL input clock10 */ +#define RCC_PLLMULL11 ((uint32_t)0x00240000) /* PLL input clock*11 */ +#define RCC_PLLMULL12 ((uint32_t)0x00280000) /* PLL input clock*12 */ +#define RCC_PLLMULL13 ((uint32_t)0x002C0000) /* PLL input clock*13 */ +#define RCC_PLLMULL14 ((uint32_t)0x00300000) /* PLL input clock*14 */ +#define RCC_PLLMULL15 ((uint32_t)0x00340000) /* PLL input clock*15 */ +#define RCC_PLLMULL16 ((uint32_t)0x00380000) /* PLL input clock*16 */ +#define RCC_USBPRE ((uint32_t)0x00400000) /* USB Device prescaler */ + +#define RCC_CFGR0_MCO ((uint32_t)0x07000000) /* MCO[2:0] bits (Microcontroller Clock Output) */ +#define RCC_MCO_0 ((uint32_t)0x01000000) /* Bit 0 */ +#define RCC_MCO_1 ((uint32_t)0x02000000) /* Bit 1 */ +#define RCC_MCO_2 ((uint32_t)0x04000000) /* Bit 2 */ + +#define RCC_MCO_NOCLOCK ((uint32_t)0x00000000) /* No clock */ +#define RCC_CFGR0_MCO_SYSCLK ((uint32_t)0x04000000) /* System clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSI ((uint32_t)0x05000000) /* HSI clock selected as MCO source */ +#define RCC_CFGR0_MCO_HSE ((uint32_t)0x06000000) /* HSE clock selected as MCO source */ +#define RCC_CFGR0_MCO_PLL ((uint32_t)0x07000000) /* PLL clock divided by 2 selected as MCO source */ + +/******************* Bit definition for RCC_INTR register ********************/ +#define RCC_LSIRDYF ((uint32_t)0x00000001) /* LSI Ready Interrupt flag */ +#define RCC_LSERDYF ((uint32_t)0x00000002) /* LSE Ready Interrupt flag */ +#define RCC_HSIRDYF ((uint32_t)0x00000004) /* HSI Ready Interrupt flag */ +#define RCC_HSERDYF ((uint32_t)0x00000008) /* HSE Ready Interrupt flag */ +#define RCC_PLLRDYF ((uint32_t)0x00000010) /* PLL Ready Interrupt flag */ +#define RCC_CSSF ((uint32_t)0x00000080) /* Clock Security System Interrupt flag */ +#define RCC_LSIRDYIE ((uint32_t)0x00000100) /* LSI Ready Interrupt Enable */ +#define RCC_LSERDYIE ((uint32_t)0x00000200) /* LSE Ready Interrupt Enable */ +#define RCC_HSIRDYIE ((uint32_t)0x00000400) /* HSI Ready Interrupt Enable */ +#define RCC_HSERDYIE ((uint32_t)0x00000800) /* HSE Ready Interrupt Enable */ +#define RCC_PLLRDYIE ((uint32_t)0x00001000) /* PLL Ready Interrupt Enable */ +#define RCC_LSIRDYC ((uint32_t)0x00010000) /* LSI Ready Interrupt Clear */ +#define RCC_LSERDYC ((uint32_t)0x00020000) /* LSE Ready Interrupt Clear */ +#define RCC_HSIRDYC ((uint32_t)0x00040000) /* HSI Ready Interrupt Clear */ +#define RCC_HSERDYC ((uint32_t)0x00080000) /* HSE Ready Interrupt Clear */ +#define RCC_PLLRDYC ((uint32_t)0x00100000) /* PLL Ready Interrupt Clear */ +#define RCC_CSSC ((uint32_t)0x00800000) /* Clock Security System Interrupt Clear */ + +/***************** Bit definition for RCC_APB2PRSTR register *****************/ +#define RCC_AFIORST ((uint32_t)0x00000001) /* Alternate Function I/O reset */ +#define RCC_IOPARST ((uint32_t)0x00000004) /* I/O port A reset */ +#define RCC_IOPBRST ((uint32_t)0x00000008) /* I/O port B reset */ +#define RCC_IOPCRST ((uint32_t)0x00000010) /* I/O port C reset */ +#define RCC_IOPDRST ((uint32_t)0x00000020) /* I/O port D reset */ +#define RCC_ADC1RST ((uint32_t)0x00000200) /* ADC 1 interface reset */ + +#define RCC_ADC2RST ((uint32_t)0x00000400) /* ADC 2 interface reset */ + +#define RCC_TIM1RST ((uint32_t)0x00000800) /* TIM1 Timer reset */ +#define RCC_SPI1RST ((uint32_t)0x00001000) /* SPI 1 reset */ +#define RCC_USART1RST ((uint32_t)0x00004000) /* USART1 reset */ + +/***************** Bit definition for RCC_APB1PRSTR register *****************/ +#define RCC_TIM2RST ((uint32_t)0x00000001) /* Timer 2 reset */ +#define RCC_TIM3RST ((uint32_t)0x00000002) /* Timer 3 reset */ +#define RCC_WWDGRST ((uint32_t)0x00000800) /* Window Watchdog reset */ +#define RCC_USART2RST ((uint32_t)0x00020000) /* USART 2 reset */ +#define RCC_I2C1RST ((uint32_t)0x00200000) /* I2C 1 reset */ + +#define RCC_CAN1RST ((uint32_t)0x02000000) /* CAN1 reset */ + +#define RCC_BKPRST ((uint32_t)0x08000000) /* Backup interface reset */ +#define RCC_PWRRST ((uint32_t)0x10000000) /* Power interface reset */ + +#define RCC_TIM4RST ((uint32_t)0x00000004) /* Timer 4 reset */ +#define RCC_SPI2RST ((uint32_t)0x00004000) /* SPI 2 reset */ +#define RCC_USART3RST ((uint32_t)0x00040000) /* USART 3 reset */ +#define RCC_I2C2RST ((uint32_t)0x00400000) /* I2C 2 reset */ + +#define RCC_USBRST ((uint32_t)0x00800000) /* USB Device reset */ + +/****************** Bit definition for RCC_AHBPCENR register ******************/ +#define RCC_DMA1EN ((uint16_t)0x0001) /* DMA1 clock enable */ +#define RCC_SRAMEN ((uint16_t)0x0004) /* SRAM interface clock enable */ +#define RCC_FLITFEN ((uint16_t)0x0010) /* FLITF clock enable */ +#define RCC_CRCEN ((uint16_t)0x0040) /* CRC clock enable */ +#define RCC_USBHD ((uint16_t)0x1000) + +/****************** Bit definition for RCC_APB2PCENR register *****************/ +#define RCC_AFIOEN ((uint32_t)0x00000001) /* Alternate Function I/O clock enable */ +#define RCC_IOPAEN ((uint32_t)0x00000004) /* I/O port A clock enable */ +#define RCC_IOPBEN ((uint32_t)0x00000008) /* I/O port B clock enable */ +#define RCC_IOPCEN ((uint32_t)0x00000010) /* I/O port C clock enable */ +#define RCC_IOPDEN ((uint32_t)0x00000020) /* I/O port D clock enable */ +#define RCC_ADC1EN ((uint32_t)0x00000200) /* ADC 1 interface clock enable */ + +#define RCC_ADC2EN ((uint32_t)0x00000400) /* ADC 2 interface clock enable */ + +#define RCC_TIM1EN ((uint32_t)0x00000800) /* TIM1 Timer clock enable */ +#define RCC_SPI1EN ((uint32_t)0x00001000) /* SPI 1 clock enable */ +#define RCC_USART1EN ((uint32_t)0x00004000) /* USART1 clock enable */ + +/***************** Bit definition for RCC_APB1PCENR register ******************/ +#define RCC_TIM2EN ((uint32_t)0x00000001) /* Timer 2 clock enabled*/ +#define RCC_TIM3EN ((uint32_t)0x00000002) /* Timer 3 clock enable */ +#define RCC_WWDGEN ((uint32_t)0x00000800) /* Window Watchdog clock enable */ +#define RCC_USART2EN ((uint32_t)0x00020000) /* USART 2 clock enable */ +#define RCC_I2C1EN ((uint32_t)0x00200000) /* I2C 1 clock enable */ + +#define RCC_BKPEN ((uint32_t)0x08000000) /* Backup interface clock enable */ +#define RCC_PWREN ((uint32_t)0x10000000) /* Power interface clock enable */ + +#define RCC_USBEN ((uint32_t)0x00800000) /* USB Device clock enable */ + +/******************* Bit definition for RCC_BDCTLR register *******************/ +#define RCC_LSEON ((uint32_t)0x00000001) /* External Low Speed oscillator enable */ +#define RCC_LSERDY ((uint32_t)0x00000002) /* External Low Speed oscillator Ready */ +#define RCC_LSEBYP ((uint32_t)0x00000004) /* External Low Speed oscillator Bypass */ + +#define RCC_RTCSEL ((uint32_t)0x00000300) /* RTCSEL[1:0] bits (RTC clock source selection) */ +#define RCC_RTCSEL_0 ((uint32_t)0x00000100) /* Bit 0 */ +#define RCC_RTCSEL_1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define RCC_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /* No clock */ +#define RCC_RTCSEL_LSE ((uint32_t)0x00000100) /* LSE oscillator clock used as RTC clock */ +#define RCC_RTCSEL_LSI ((uint32_t)0x00000200) /* LSI oscillator clock used as RTC clock */ +#define RCC_RTCSEL_HSE ((uint32_t)0x00000300) /* HSE oscillator clock divided by 128 used as RTC clock */ + +#define RCC_RTCEN ((uint32_t)0x00008000) /* RTC clock enable */ +#define RCC_BDRST ((uint32_t)0x00010000) /* Backup domain software reset */ + +/******************* Bit definition for RCC_RSTSCKR register ********************/ +#define RCC_LSION ((uint32_t)0x00000001) /* Internal Low Speed oscillator enable */ +#define RCC_LSIRDY ((uint32_t)0x00000002) /* Internal Low Speed oscillator Ready */ +#define RCC_RMVF ((uint32_t)0x01000000) /* Remove reset flag */ +#define RCC_PINRSTF ((uint32_t)0x04000000) /* PIN reset flag */ +#define RCC_PORRSTF ((uint32_t)0x08000000) /* POR/PDR reset flag */ +#define RCC_SFTRSTF ((uint32_t)0x10000000) /* Software Reset flag */ +#define RCC_IWDGRSTF ((uint32_t)0x20000000) /* Independent Watchdog reset flag */ +#define RCC_WWDGRSTF ((uint32_t)0x40000000) /* Window watchdog reset flag */ +#define RCC_LPWRRSTF ((uint32_t)0x80000000) /* Low-Power reset flag */ + +/******************************************************************************/ +/* Real-Time Clock */ +/******************************************************************************/ + +/******************* Bit definition for RTC_CTLRH register ********************/ +#define RTC_CTLRH_SECIE ((uint8_t)0x01) /* Second Interrupt Enable */ +#define RTC_CTLRH_ALRIE ((uint8_t)0x02) /* Alarm Interrupt Enable */ +#define RTC_CTLRH_OWIE ((uint8_t)0x04) /* OverfloW Interrupt Enable */ + +/******************* Bit definition for RTC_CTLRL register ********************/ +#define RTC_CTLRL_SECF ((uint8_t)0x01) /* Second Flag */ +#define RTC_CTLRL_ALRF ((uint8_t)0x02) /* Alarm Flag */ +#define RTC_CTLRL_OWF ((uint8_t)0x04) /* OverfloW Flag */ +#define RTC_CTLRL_RSF ((uint8_t)0x08) /* Registers Synchronized Flag */ +#define RTC_CTLRL_CNF ((uint8_t)0x10) /* Configuration Flag */ +#define RTC_CTLRL_RTOFF ((uint8_t)0x20) /* RTC operation OFF */ + +/******************* Bit definition for RTC_PSCH register *******************/ +#define RTC_PSCH_PRL ((uint16_t)0x000F) /* RTC Prescaler Reload Value High */ + +/******************* Bit definition for RTC_PRLL register *******************/ +#define RTC_PSCL_PRL ((uint16_t)0xFFFF) /* RTC Prescaler Reload Value Low */ + +/******************* Bit definition for RTC_DIVH register *******************/ +#define RTC_DIVH_RTC_DIV ((uint16_t)0x000F) /* RTC Clock Divider High */ + +/******************* Bit definition for RTC_DIVL register *******************/ +#define RTC_DIVL_RTC_DIV ((uint16_t)0xFFFF) /* RTC Clock Divider Low */ + +/******************* Bit definition for RTC_CNTH register *******************/ +#define RTC_CNTH_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter High */ + +/******************* Bit definition for RTC_CNTL register *******************/ +#define RTC_CNTL_RTC_CNT ((uint16_t)0xFFFF) /* RTC Counter Low */ + +/******************* Bit definition for RTC_ALRMH register *******************/ +#define RTC_ALRMH_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm High */ + +/******************* Bit definition for RTC_ALRML register *******************/ +#define RTC_ALRML_RTC_ALRM ((uint16_t)0xFFFF) /* RTC Alarm Low */ + +/******************************************************************************/ +/* Serial Peripheral Interface */ +/******************************************************************************/ + +/******************* Bit definition for SPI_CTLR1 register ********************/ +#define SPI_CTLR1_CPHA ((uint16_t)0x0001) /* Clock Phase */ +#define SPI_CTLR1_CPOL ((uint16_t)0x0002) /* Clock Polarity */ +#define SPI_CTLR1_MSTR ((uint16_t)0x0004) /* Master Selection */ + +#define SPI_CTLR1_BR ((uint16_t)0x0038) /* BR[2:0] bits (Baud Rate Control) */ +#define SPI_CTLR1_BR_0 ((uint16_t)0x0008) /* Bit 0 */ +#define SPI_CTLR1_BR_1 ((uint16_t)0x0010) /* Bit 1 */ +#define SPI_CTLR1_BR_2 ((uint16_t)0x0020) /* Bit 2 */ + +#define SPI_CTLR1_SPE ((uint16_t)0x0040) /* SPI Enable */ +#define SPI_CTLR1_LSBFIRST ((uint16_t)0x0080) /* Frame Format */ +#define SPI_CTLR1_SSI ((uint16_t)0x0100) /* Internal slave select */ +#define SPI_CTLR1_SSM ((uint16_t)0x0200) /* Software slave management */ +#define SPI_CTLR1_RXONLY ((uint16_t)0x0400) /* Receive only */ +#define SPI_CTLR1_DFF ((uint16_t)0x0800) /* Data Frame Format */ +#define SPI_CTLR1_CRCNEXT ((uint16_t)0x1000) /* Transmit CRC next */ +#define SPI_CTLR1_CRCEN ((uint16_t)0x2000) /* Hardware CRC calculation enable */ +#define SPI_CTLR1_BIDIOE ((uint16_t)0x4000) /* Output enable in bidirectional mode */ +#define SPI_CTLR1_BIDIMODE ((uint16_t)0x8000) /* Bidirectional data mode enable */ + +/******************* Bit definition for SPI_CTLR2 register ********************/ +#define SPI_CTLR2_RXDMAEN ((uint8_t)0x01) /* Rx Buffer DMA Enable */ +#define SPI_CTLR2_TXDMAEN ((uint8_t)0x02) /* Tx Buffer DMA Enable */ +#define SPI_CTLR2_SSOE ((uint8_t)0x04) /* SS Output Enable */ +#define SPI_CTLR2_ERRIE ((uint8_t)0x20) /* Error Interrupt Enable */ +#define SPI_CTLR2_RXNEIE ((uint8_t)0x40) /* RX buffer Not Empty Interrupt Enable */ +#define SPI_CTLR2_TXEIE ((uint8_t)0x80) /* Tx buffer Empty Interrupt Enable */ + +/******************** Bit definition for SPI_STATR register ********************/ +#define SPI_STATR_RXNE ((uint8_t)0x01) /* Receive buffer Not Empty */ +#define SPI_STATR_TXE ((uint8_t)0x02) /* Transmit buffer Empty */ +#define SPI_STATR_CHSIDE ((uint8_t)0x04) /* Channel side */ +#define SPI_STATR_UDR ((uint8_t)0x08) /* Underrun flag */ +#define SPI_STATR_CRCERR ((uint8_t)0x10) /* CRC Error flag */ +#define SPI_STATR_MODF ((uint8_t)0x20) /* Mode fault */ +#define SPI_STATR_OVR ((uint8_t)0x40) /* Overrun flag */ +#define SPI_STATR_BSY ((uint8_t)0x80) /* Busy flag */ + +/******************** Bit definition for SPI_DATAR register ********************/ +#define SPI_DATAR_DR ((uint16_t)0xFFFF) /* Data Register */ + +/******************* Bit definition for SPI_CRCR register ******************/ +#define SPI_CRCR_CRCPOLY ((uint16_t)0xFFFF) /* CRC polynomial register */ + +/****************** Bit definition for SPI_RCRCR register ******************/ +#define SPI_RCRCR_RXCRC ((uint16_t)0xFFFF) /* Rx CRC Register */ + +/****************** Bit definition for SPI_TCRCR register ******************/ +#define SPI_TCRCR_TXCRC ((uint16_t)0xFFFF) /* Tx CRC Register */ + +/****************** Bit definition for SPI_HSCR register *****************/ +#define SPI_HSCR_HSRXEN ((uint16_t)0x0001) + +/******************************************************************************/ +/* TIM */ +/******************************************************************************/ + +/******************* Bit definition for TIM_CTLR1 register ********************/ +#define TIM_CEN ((uint16_t)0x0001) /* Counter enable */ +#define TIM_UDIS ((uint16_t)0x0002) /* Update disable */ +#define TIM_URS ((uint16_t)0x0004) /* Update request source */ +#define TIM_OPM ((uint16_t)0x0008) /* One pulse mode */ +#define TIM_DIR ((uint16_t)0x0010) /* Direction */ + +#define TIM_CMS ((uint16_t)0x0060) /* CMS[1:0] bits (Center-aligned mode selection) */ +#define TIM_CMS_0 ((uint16_t)0x0020) /* Bit 0 */ +#define TIM_CMS_1 ((uint16_t)0x0040) /* Bit 1 */ + +#define TIM_ARPE ((uint16_t)0x0080) /* Auto-reload preload enable */ + +#define TIM_CTLR1_CKD ((uint16_t)0x0300) /* CKD[1:0] bits (clock division) */ +#define TIM_CKD_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CKD_1 ((uint16_t)0x0200) /* Bit 1 */ + +/******************* Bit definition for TIM_CTLR2 register ********************/ +#define TIM_CCPC ((uint16_t)0x0001) /* Capture/Compare Preloaded Control */ +#define TIM_CCUS ((uint16_t)0x0004) /* Capture/Compare Control Update Selection */ +#define TIM_CCDS ((uint16_t)0x0008) /* Capture/Compare DMA Selection */ + +#define TIM_MMS ((uint16_t)0x0070) /* MMS[2:0] bits (Master Mode Selection) */ +#define TIM_MMS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_MMS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_MMS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_TI1S ((uint16_t)0x0080) /* TI1 Selection */ +#define TIM_OIS1 ((uint16_t)0x0100) /* Output Idle state 1 (OC1 output) */ +#define TIM_OIS1N ((uint16_t)0x0200) /* Output Idle state 1 (OC1N output) */ +#define TIM_OIS2 ((uint16_t)0x0400) /* Output Idle state 2 (OC2 output) */ +#define TIM_OIS2N ((uint16_t)0x0800) /* Output Idle state 2 (OC2N output) */ +#define TIM_OIS3 ((uint16_t)0x1000) /* Output Idle state 3 (OC3 output) */ +#define TIM_OIS3N ((uint16_t)0x2000) /* Output Idle state 3 (OC3N output) */ +#define TIM_OIS4 ((uint16_t)0x4000) /* Output Idle state 4 (OC4 output) */ + +/******************* Bit definition for TIM_SMCFGR register *******************/ +#define TIM_SMS ((uint16_t)0x0007) /* SMS[2:0] bits (Slave mode selection) */ +#define TIM_SMS_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_SMS_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_SMS_2 ((uint16_t)0x0004) /* Bit 2 */ + +#define TIM_TS ((uint16_t)0x0070) /* TS[2:0] bits (Trigger selection) */ +#define TIM_TS_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_TS_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_TS_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_MSM ((uint16_t)0x0080) /* Master/slave mode */ + +#define TIM_ETF ((uint16_t)0x0F00) /* ETF[3:0] bits (External trigger filter) */ +#define TIM_ETF_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_ETF_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_ETF_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_ETF_3 ((uint16_t)0x0800) /* Bit 3 */ + +#define TIM_ETPS ((uint16_t)0x3000) /* ETPS[1:0] bits (External trigger prescaler) */ +#define TIM_ETPS_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_ETPS_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define TIM_ECE ((uint16_t)0x4000) /* External clock enable */ +#define TIM_ETP ((uint16_t)0x8000) /* External trigger polarity */ + +/******************* Bit definition for TIM_DMAINTENR register *******************/ +#define TIM_UIE ((uint16_t)0x0001) /* Update interrupt enable */ +#define TIM_CC1IE ((uint16_t)0x0002) /* Capture/Compare 1 interrupt enable */ +#define TIM_CC2IE ((uint16_t)0x0004) /* Capture/Compare 2 interrupt enable */ +#define TIM_CC3IE ((uint16_t)0x0008) /* Capture/Compare 3 interrupt enable */ +#define TIM_CC4IE ((uint16_t)0x0010) /* Capture/Compare 4 interrupt enable */ +#define TIM_COMIE ((uint16_t)0x0020) /* COM interrupt enable */ +#define TIM_TIE ((uint16_t)0x0040) /* Trigger interrupt enable */ +#define TIM_BIE ((uint16_t)0x0080) /* Break interrupt enable */ +#define TIM_UDE ((uint16_t)0x0100) /* Update DMA request enable */ +#define TIM_CC1DE ((uint16_t)0x0200) /* Capture/Compare 1 DMA request enable */ +#define TIM_CC2DE ((uint16_t)0x0400) /* Capture/Compare 2 DMA request enable */ +#define TIM_CC3DE ((uint16_t)0x0800) /* Capture/Compare 3 DMA request enable */ +#define TIM_CC4DE ((uint16_t)0x1000) /* Capture/Compare 4 DMA request enable */ +#define TIM_COMDE ((uint16_t)0x2000) /* COM DMA request enable */ +#define TIM_TDE ((uint16_t)0x4000) /* Trigger DMA request enable */ + +/******************** Bit definition for TIM_INTFR register ********************/ +#define TIM_UIF ((uint16_t)0x0001) /* Update interrupt Flag */ +#define TIM_CC1IF ((uint16_t)0x0002) /* Capture/Compare 1 interrupt Flag */ +#define TIM_CC2IF ((uint16_t)0x0004) /* Capture/Compare 2 interrupt Flag */ +#define TIM_CC3IF ((uint16_t)0x0008) /* Capture/Compare 3 interrupt Flag */ +#define TIM_CC4IF ((uint16_t)0x0010) /* Capture/Compare 4 interrupt Flag */ +#define TIM_COMIF ((uint16_t)0x0020) /* COM interrupt Flag */ +#define TIM_TIF ((uint16_t)0x0040) /* Trigger interrupt Flag */ +#define TIM_BIF ((uint16_t)0x0080) /* Break interrupt Flag */ +#define TIM_CC1OF ((uint16_t)0x0200) /* Capture/Compare 1 Overcapture Flag */ +#define TIM_CC2OF ((uint16_t)0x0400) /* Capture/Compare 2 Overcapture Flag */ +#define TIM_CC3OF ((uint16_t)0x0800) /* Capture/Compare 3 Overcapture Flag */ +#define TIM_CC4OF ((uint16_t)0x1000) /* Capture/Compare 4 Overcapture Flag */ + +/******************* Bit definition for TIM_SWEVGR register ********************/ +#define TIM_UG ((uint8_t)0x01) /* Update Generation */ +#define TIM_CC1G ((uint8_t)0x02) /* Capture/Compare 1 Generation */ +#define TIM_CC2G ((uint8_t)0x04) /* Capture/Compare 2 Generation */ +#define TIM_CC3G ((uint8_t)0x08) /* Capture/Compare 3 Generation */ +#define TIM_CC4G ((uint8_t)0x10) /* Capture/Compare 4 Generation */ +#define TIM_COMG ((uint8_t)0x20) /* Capture/Compare Control Update Generation */ +#define TIM_TG ((uint8_t)0x40) /* Trigger Generation */ +#define TIM_BG ((uint8_t)0x80) /* Break Generation */ + +/****************** Bit definition for TIM_CHCTLR1 register *******************/ +#define TIM_CC1S ((uint16_t)0x0003) /* CC1S[1:0] bits (Capture/Compare 1 Selection) */ +#define TIM_CC1S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC1S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC1FE ((uint16_t)0x0004) /* Output Compare 1 Fast enable */ +#define TIM_OC1PE ((uint16_t)0x0008) /* Output Compare 1 Preload enable */ + +#define TIM_OC1M ((uint16_t)0x0070) /* OC1M[2:0] bits (Output Compare 1 Mode) */ +#define TIM_OC1M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC1M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC1M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC1CE ((uint16_t)0x0080) /* Output Compare 1Clear Enable */ + +#define TIM_CC2S ((uint16_t)0x0300) /* CC2S[1:0] bits (Capture/Compare 2 Selection) */ +#define TIM_CC2S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC2S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC2FE ((uint16_t)0x0400) /* Output Compare 2 Fast enable */ +#define TIM_OC2PE ((uint16_t)0x0800) /* Output Compare 2 Preload enable */ + +#define TIM_OC2M ((uint16_t)0x7000) /* OC2M[2:0] bits (Output Compare 2 Mode) */ +#define TIM_OC2M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC2M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC2M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC2CE ((uint16_t)0x8000) /* Output Compare 2 Clear Enable */ + +#define TIM_IC1PSC ((uint16_t)0x000C) /* IC1PSC[1:0] bits (Input Capture 1 Prescaler) */ +#define TIM_IC1PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC1PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC1F ((uint16_t)0x00F0) /* IC1F[3:0] bits (Input Capture 1 Filter) */ +#define TIM_IC1F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC1F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC1F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC1F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC2PSC ((uint16_t)0x0C00) /* IC2PSC[1:0] bits (Input Capture 2 Prescaler) */ +#define TIM_IC2PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC2PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC2F ((uint16_t)0xF000) /* IC2F[3:0] bits (Input Capture 2 Filter) */ +#define TIM_IC2F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC2F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC2F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC2F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/****************** Bit definition for TIM_CHCTLR2 register *******************/ +#define TIM_CC3S ((uint16_t)0x0003) /* CC3S[1:0] bits (Capture/Compare 3 Selection) */ +#define TIM_CC3S_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_CC3S_1 ((uint16_t)0x0002) /* Bit 1 */ + +#define TIM_OC3FE ((uint16_t)0x0004) /* Output Compare 3 Fast enable */ +#define TIM_OC3PE ((uint16_t)0x0008) /* Output Compare 3 Preload enable */ + +#define TIM_OC3M ((uint16_t)0x0070) /* OC3M[2:0] bits (Output Compare 3 Mode) */ +#define TIM_OC3M_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_OC3M_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_OC3M_2 ((uint16_t)0x0040) /* Bit 2 */ + +#define TIM_OC3CE ((uint16_t)0x0080) /* Output Compare 3 Clear Enable */ + +#define TIM_CC4S ((uint16_t)0x0300) /* CC4S[1:0] bits (Capture/Compare 4 Selection) */ +#define TIM_CC4S_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_CC4S_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OC4FE ((uint16_t)0x0400) /* Output Compare 4 Fast enable */ +#define TIM_OC4PE ((uint16_t)0x0800) /* Output Compare 4 Preload enable */ + +#define TIM_OC4M ((uint16_t)0x7000) /* OC4M[2:0] bits (Output Compare 4 Mode) */ +#define TIM_OC4M_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_OC4M_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_OC4M_2 ((uint16_t)0x4000) /* Bit 2 */ + +#define TIM_OC4CE ((uint16_t)0x8000) /* Output Compare 4 Clear Enable */ + +#define TIM_IC3PSC ((uint16_t)0x000C) /* IC3PSC[1:0] bits (Input Capture 3 Prescaler) */ +#define TIM_IC3PSC_0 ((uint16_t)0x0004) /* Bit 0 */ +#define TIM_IC3PSC_1 ((uint16_t)0x0008) /* Bit 1 */ + +#define TIM_IC3F ((uint16_t)0x00F0) /* IC3F[3:0] bits (Input Capture 3 Filter) */ +#define TIM_IC3F_0 ((uint16_t)0x0010) /* Bit 0 */ +#define TIM_IC3F_1 ((uint16_t)0x0020) /* Bit 1 */ +#define TIM_IC3F_2 ((uint16_t)0x0040) /* Bit 2 */ +#define TIM_IC3F_3 ((uint16_t)0x0080) /* Bit 3 */ + +#define TIM_IC4PSC ((uint16_t)0x0C00) /* IC4PSC[1:0] bits (Input Capture 4 Prescaler) */ +#define TIM_IC4PSC_0 ((uint16_t)0x0400) /* Bit 0 */ +#define TIM_IC4PSC_1 ((uint16_t)0x0800) /* Bit 1 */ + +#define TIM_IC4F ((uint16_t)0xF000) /* IC4F[3:0] bits (Input Capture 4 Filter) */ +#define TIM_IC4F_0 ((uint16_t)0x1000) /* Bit 0 */ +#define TIM_IC4F_1 ((uint16_t)0x2000) /* Bit 1 */ +#define TIM_IC4F_2 ((uint16_t)0x4000) /* Bit 2 */ +#define TIM_IC4F_3 ((uint16_t)0x8000) /* Bit 3 */ + +/******************* Bit definition for TIM_CCER register *******************/ +#define TIM_CC1E ((uint16_t)0x0001) /* Capture/Compare 1 output enable */ +#define TIM_CC1P ((uint16_t)0x0002) /* Capture/Compare 1 output Polarity */ +#define TIM_CC1NE ((uint16_t)0x0004) /* Capture/Compare 1 Complementary output enable */ +#define TIM_CC1NP ((uint16_t)0x0008) /* Capture/Compare 1 Complementary output Polarity */ +#define TIM_CC2E ((uint16_t)0x0010) /* Capture/Compare 2 output enable */ +#define TIM_CC2P ((uint16_t)0x0020) /* Capture/Compare 2 output Polarity */ +#define TIM_CC2NE ((uint16_t)0x0040) /* Capture/Compare 2 Complementary output enable */ +#define TIM_CC2NP ((uint16_t)0x0080) /* Capture/Compare 2 Complementary output Polarity */ +#define TIM_CC3E ((uint16_t)0x0100) /* Capture/Compare 3 output enable */ +#define TIM_CC3P ((uint16_t)0x0200) /* Capture/Compare 3 output Polarity */ +#define TIM_CC3NE ((uint16_t)0x0400) /* Capture/Compare 3 Complementary output enable */ +#define TIM_CC3NP ((uint16_t)0x0800) /* Capture/Compare 3 Complementary output Polarity */ +#define TIM_CC4E ((uint16_t)0x1000) /* Capture/Compare 4 output enable */ +#define TIM_CC4P ((uint16_t)0x2000) /* Capture/Compare 4 output Polarity */ +#define TIM_CC4NP ((uint16_t)0x8000) /* Capture/Compare 4 Complementary output Polarity */ + +/******************* Bit definition for TIM_CNT register ********************/ +#define TIM_CNT ((uint16_t)0xFFFF) /* Counter Value */ + +/******************* Bit definition for TIM_PSC register ********************/ +#define TIM_PSC ((uint16_t)0xFFFF) /* Prescaler Value */ + +/******************* Bit definition for TIM_ATRLR register ********************/ +#define TIM_ARR ((uint16_t)0xFFFF) /* actual auto-reload Value */ + +/******************* Bit definition for TIM_RPTCR register ********************/ +#define TIM_REP ((uint8_t)0xFF) /* Repetition Counter Value */ + +/******************* Bit definition for TIM_CH1CVR register *******************/ +#define TIM_CCR1 ((uint16_t)0xFFFF) /* Capture/Compare 1 Value */ + +/******************* Bit definition for TIM_CH2CVR register *******************/ +#define TIM_CCR2 ((uint16_t)0xFFFF) /* Capture/Compare 2 Value */ + +/******************* Bit definition for TIM_CH3CVR register *******************/ +#define TIM_CCR3 ((uint16_t)0xFFFF) /* Capture/Compare 3 Value */ + +/******************* Bit definition for TIM_CH4CVR register *******************/ +#define TIM_CCR4 ((uint16_t)0xFFFF) /* Capture/Compare 4 Value */ + +/******************* Bit definition for TIM_BDTR register *******************/ +#define TIM_DTG ((uint16_t)0x00FF) /* DTG[0:7] bits (Dead-Time Generator set-up) */ +#define TIM_DTG_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DTG_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DTG_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DTG_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DTG_4 ((uint16_t)0x0010) /* Bit 4 */ +#define TIM_DTG_5 ((uint16_t)0x0020) /* Bit 5 */ +#define TIM_DTG_6 ((uint16_t)0x0040) /* Bit 6 */ +#define TIM_DTG_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define TIM_LOCK ((uint16_t)0x0300) /* LOCK[1:0] bits (Lock Configuration) */ +#define TIM_LOCK_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_LOCK_1 ((uint16_t)0x0200) /* Bit 1 */ + +#define TIM_OSSI ((uint16_t)0x0400) /* Off-State Selection for Idle mode */ +#define TIM_OSSR ((uint16_t)0x0800) /* Off-State Selection for Run mode */ +#define TIM_BKE ((uint16_t)0x1000) /* Break enable */ +#define TIM_BKP ((uint16_t)0x2000) /* Break Polarity */ +#define TIM_AOE ((uint16_t)0x4000) /* Automatic Output enable */ +#define TIM_MOE ((uint16_t)0x8000) /* Main Output enable */ + +/******************* Bit definition for TIM_DMACFGR register ********************/ +#define TIM_DBA ((uint16_t)0x001F) /* DBA[4:0] bits (DMA Base Address) */ +#define TIM_DBA_0 ((uint16_t)0x0001) /* Bit 0 */ +#define TIM_DBA_1 ((uint16_t)0x0002) /* Bit 1 */ +#define TIM_DBA_2 ((uint16_t)0x0004) /* Bit 2 */ +#define TIM_DBA_3 ((uint16_t)0x0008) /* Bit 3 */ +#define TIM_DBA_4 ((uint16_t)0x0010) /* Bit 4 */ + +#define TIM_DBL ((uint16_t)0x1F00) /* DBL[4:0] bits (DMA Burst Length) */ +#define TIM_DBL_0 ((uint16_t)0x0100) /* Bit 0 */ +#define TIM_DBL_1 ((uint16_t)0x0200) /* Bit 1 */ +#define TIM_DBL_2 ((uint16_t)0x0400) /* Bit 2 */ +#define TIM_DBL_3 ((uint16_t)0x0800) /* Bit 3 */ +#define TIM_DBL_4 ((uint16_t)0x1000) /* Bit 4 */ + +/******************* Bit definition for TIM_DMAADR register *******************/ +#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /* DMA register for burst accesses */ + +/******************************************************************************/ +/* Universal Synchronous Asynchronous Receiver Transmitter */ +/******************************************************************************/ + +/******************* Bit definition for USART_STATR register *******************/ +#define USART_STATR_PE ((uint16_t)0x0001) /* Parity Error */ +#define USART_STATR_FE ((uint16_t)0x0002) /* Framing Error */ +#define USART_STATR_NE ((uint16_t)0x0004) /* Noise Error Flag */ +#define USART_STATR_ORE ((uint16_t)0x0008) /* OverRun Error */ +#define USART_STATR_IDLE ((uint16_t)0x0010) /* IDLE line detected */ +#define USART_STATR_RXNE ((uint16_t)0x0020) /* Read Data Register Not Empty */ +#define USART_STATR_TC ((uint16_t)0x0040) /* Transmission Complete */ +#define USART_STATR_TXE ((uint16_t)0x0080) /* Transmit Data Register Empty */ +#define USART_STATR_LBD ((uint16_t)0x0100) /* LIN Break Detection Flag */ +#define USART_STATR_CTS ((uint16_t)0x0200) /* CTS Flag */ + +/******************* Bit definition for USART_DATAR register *******************/ +#define USART_DATAR_DR ((uint16_t)0x01FF) /* Data value */ + +/****************** Bit definition for USART_BRR register *******************/ +#define USART_BRR_DIV_Fraction ((uint16_t)0x000F) /* Fraction of USARTDIV */ +#define USART_BRR_DIV_Mantissa ((uint16_t)0xFFF0) /* Mantissa of USARTDIV */ + +/****************** Bit definition for USART_CTLR1 register *******************/ +#define USART_CTLR1_SBK ((uint16_t)0x0001) /* Send Break */ +#define USART_CTLR1_RWU ((uint16_t)0x0002) /* Receiver wakeup */ +#define USART_CTLR1_RE ((uint16_t)0x0004) /* Receiver Enable */ +#define USART_CTLR1_TE ((uint16_t)0x0008) /* Transmitter Enable */ +#define USART_CTLR1_IDLEIE ((uint16_t)0x0010) /* IDLE Interrupt Enable */ +#define USART_CTLR1_RXNEIE ((uint16_t)0x0020) /* RXNE Interrupt Enable */ +#define USART_CTLR1_TCIE ((uint16_t)0x0040) /* Transmission Complete Interrupt Enable */ +#define USART_CTLR1_TXEIE ((uint16_t)0x0080) /* PE Interrupt Enable */ +#define USART_CTLR1_PEIE ((uint16_t)0x0100) /* PE Interrupt Enable */ +#define USART_CTLR1_PS ((uint16_t)0x0200) /* Parity Selection */ +#define USART_CTLR1_PCE ((uint16_t)0x0400) /* Parity Control Enable */ +#define USART_CTLR1_WAKE ((uint16_t)0x0800) /* Wakeup method */ +#define USART_CTLR1_M ((uint16_t)0x1000) /* Word length */ +#define USART_CTLR1_UE ((uint16_t)0x2000) /* USART Enable */ +#define USART_CTLR1_OVER8 ((uint16_t)0x8000) /* USART Oversmapling 8-bits */ + +/****************** Bit definition for USART_CTLR2 register *******************/ +#define USART_CTLR2_ADD ((uint16_t)0x000F) /* Address of the USART node */ +#define USART_CTLR2_LBDL ((uint16_t)0x0020) /* LIN Break Detection Length */ +#define USART_CTLR2_LBDIE ((uint16_t)0x0040) /* LIN Break Detection Interrupt Enable */ +#define USART_CTLR2_LBCL ((uint16_t)0x0100) /* Last Bit Clock pulse */ +#define USART_CTLR2_CPHA ((uint16_t)0x0200) /* Clock Phase */ +#define USART_CTLR2_CPOL ((uint16_t)0x0400) /* Clock Polarity */ +#define USART_CTLR2_CLKEN ((uint16_t)0x0800) /* Clock Enable */ + +#define USART_CTLR2_STOP ((uint16_t)0x3000) /* STOP[1:0] bits (STOP bits) */ +#define USART_CTLR2_STOP_0 ((uint16_t)0x1000) /* Bit 0 */ +#define USART_CTLR2_STOP_1 ((uint16_t)0x2000) /* Bit 1 */ + +#define USART_CTLR2_LINEN ((uint16_t)0x4000) /* LIN mode enable */ + +/****************** Bit definition for USART_CTLR3 register *******************/ +#define USART_CTLR3_EIE ((uint16_t)0x0001) /* Error Interrupt Enable */ +#define USART_CTLR3_IREN ((uint16_t)0x0002) /* IrDA mode Enable */ +#define USART_CTLR3_IRLP ((uint16_t)0x0004) /* IrDA Low-Power */ +#define USART_CTLR3_HDSEL ((uint16_t)0x0008) /* Half-Duplex Selection */ +#define USART_CTLR3_NACK ((uint16_t)0x0010) /* Smartcard NACK enable */ +#define USART_CTLR3_SCEN ((uint16_t)0x0020) /* Smartcard mode enable */ +#define USART_CTLR3_DMAR ((uint16_t)0x0040) /* DMA Enable Receiver */ +#define USART_CTLR3_DMAT ((uint16_t)0x0080) /* DMA Enable Transmitter */ +#define USART_CTLR3_RTSE ((uint16_t)0x0100) /* RTS Enable */ +#define USART_CTLR3_CTSE ((uint16_t)0x0200) /* CTS Enable */ +#define USART_CTLR3_CTSIE ((uint16_t)0x0400) /* CTS Interrupt Enable */ +#define USART_CTLR3_ONEBIT ((uint16_t)0x0800) /* One Bit method */ + +/****************** Bit definition for USART_GPR register ******************/ +#define USART_GPR_PSC ((uint16_t)0x00FF) /* PSC[7:0] bits (Prescaler value) */ +#define USART_GPR_PSC_0 ((uint16_t)0x0001) /* Bit 0 */ +#define USART_GPR_PSC_1 ((uint16_t)0x0002) /* Bit 1 */ +#define USART_GPR_PSC_2 ((uint16_t)0x0004) /* Bit 2 */ +#define USART_GPR_PSC_3 ((uint16_t)0x0008) /* Bit 3 */ +#define USART_GPR_PSC_4 ((uint16_t)0x0010) /* Bit 4 */ +#define USART_GPR_PSC_5 ((uint16_t)0x0020) /* Bit 5 */ +#define USART_GPR_PSC_6 ((uint16_t)0x0040) /* Bit 6 */ +#define USART_GPR_PSC_7 ((uint16_t)0x0080) /* Bit 7 */ + +#define USART_GPR_GT ((uint16_t)0xFF00) /* Guard time value */ + +/******************************************************************************/ +/* Window WATCHDOG */ +/******************************************************************************/ + +/******************* Bit definition for WWDG_CTLR register ********************/ +#define WWDG_CTLR_T ((uint8_t)0x7F) /* T[6:0] bits (7-Bit counter (MSB to LSB)) */ +#define WWDG_CTLR_T0 ((uint8_t)0x01) /* Bit 0 */ +#define WWDG_CTLR_T1 ((uint8_t)0x02) /* Bit 1 */ +#define WWDG_CTLR_T2 ((uint8_t)0x04) /* Bit 2 */ +#define WWDG_CTLR_T3 ((uint8_t)0x08) /* Bit 3 */ +#define WWDG_CTLR_T4 ((uint8_t)0x10) /* Bit 4 */ +#define WWDG_CTLR_T5 ((uint8_t)0x20) /* Bit 5 */ +#define WWDG_CTLR_T6 ((uint8_t)0x40) /* Bit 6 */ + +#define WWDG_CTLR_WDGA ((uint8_t)0x80) /* Activation bit */ + +/******************* Bit definition for WWDG_CFGR register *******************/ +#define WWDG_CFGR_W ((uint16_t)0x007F) /* W[6:0] bits (7-bit window value) */ +#define WWDG_CFGR_W0 ((uint16_t)0x0001) /* Bit 0 */ +#define WWDG_CFGR_W1 ((uint16_t)0x0002) /* Bit 1 */ +#define WWDG_CFGR_W2 ((uint16_t)0x0004) /* Bit 2 */ +#define WWDG_CFGR_W3 ((uint16_t)0x0008) /* Bit 3 */ +#define WWDG_CFGR_W4 ((uint16_t)0x0010) /* Bit 4 */ +#define WWDG_CFGR_W5 ((uint16_t)0x0020) /* Bit 5 */ +#define WWDG_CFGR_W6 ((uint16_t)0x0040) /* Bit 6 */ + +#define WWDG_CFGR_WDGTB ((uint16_t)0x0180) /* WDGTB[1:0] bits (Timer Base) */ +#define WWDG_CFGR_WDGTB0 ((uint16_t)0x0080) /* Bit 0 */ +#define WWDG_CFGR_WDGTB1 ((uint16_t)0x0100) /* Bit 1 */ + +#define WWDG_CFGR_EWI ((uint16_t)0x0200) /* Early Wakeup Interrupt */ + +/******************* Bit definition for WWDG_STATR register ********************/ +#define WWDG_STATR_EWIF ((uint8_t)0x01) /* Early Wakeup Interrupt Flag */ + +/******************************************************************************/ +/* ENHANCED FUNNCTION */ +/******************************************************************************/ + +/**************************** Enhanced register *****************************/ +#define EXTEN_USBD_LS ((uint32_t)0x00000001) /* Bit 0 */ +#define EXTEN_USBD_PU_EN ((uint32_t)0x00000002) /* Bit 1 */ +#define EXTEN_USBFS_IO_EN ((uint32_t)0x00000004) /* Bit 2 */ +#define EXTEN_USB_5V_SEL ((uint32_t)0x00000008) /* Bit 3 */ +#define EXTEN_PLL_HSI_PRE ((uint32_t)0x00000010) /* Bit 4 */ +#define EXTEN_LOCKUP_EN ((uint32_t)0x00000040) /* Bit 5 */ +#define EXTEN_LOCKUP_RSTF ((uint32_t)0x00000080) /* Bit 7 */ +#define EXTEN_USBHD_IO_EN EXTEN_USBFS_IO_EN + +#define EXTEN_ULLDO_TRIM ((uint32_t)0x00000300) /* ULLDO_TRIM[1:0] bits */ +#define EXTEN_ULLDO_TRIM0 ((uint32_t)0x00000100) /* Bit 0 */ +#define EXTEN_ULLDO_TRIM1 ((uint32_t)0x00000200) /* Bit 1 */ + +#define EXTEN_IDO_TRIM ((uint32_t)0x00000400) /* Bit 10 */ +#define EXTEN_WRITE_EN ((uint32_t)0x00004000) /* Bit 14 */ +#define EXTEN_SHORT_WAKE ((uint32_t)0x00008000) /* Bit 15 */ + +#define EXTEN_FLASH_CLK_TRIM ((uint32_t)0x00070000) /* FLASH_CLK_TRIM[2:0] bits */ +#define EXTEN_FLASH_CLK_TRIM0 ((uint32_t)0x00010000) /* Bit 0 */ +#define EXTEN_FLASH_CLK_TRIM1 ((uint32_t)0x00020000) /* Bit 1 */ +#define EXTEN_FLASH_CLK_TRIM2 ((uint32_t)0x00040000) /* Bit 2 */ + +#include "ch32v10x_conf.h" + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V10x_H */ diff --git a/ch32v103_hallarray_controller/src/periph/ch32v10x_adc.c b/ch32v103_hallarray_controller/src/periph/ch32v10x_adc.c new file mode 100644 index 0000000..be52908 --- /dev/null +++ b/ch32v103_hallarray_controller/src/periph/ch32v10x_adc.c @@ -0,0 +1,1147 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_adc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : This file provides all the ADC firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v10x_adc.h" +#include "ch32v10x_rcc.h" + +/* ADC DISCNUM mask */ +#define CTLR1_DISCNUM_Reset ((uint32_t)0xFFFF1FFF) + +/* ADC DISCEN mask */ +#define CTLR1_DISCEN_Set ((uint32_t)0x00000800) +#define CTLR1_DISCEN_Reset ((uint32_t)0xFFFFF7FF) + +/* ADC JAUTO mask */ +#define CTLR1_JAUTO_Set ((uint32_t)0x00000400) +#define CTLR1_JAUTO_Reset ((uint32_t)0xFFFFFBFF) + +/* ADC JDISCEN mask */ +#define CTLR1_JDISCEN_Set ((uint32_t)0x00001000) +#define CTLR1_JDISCEN_Reset ((uint32_t)0xFFFFEFFF) + +/* ADC AWDCH mask */ +#define CTLR1_AWDCH_Reset ((uint32_t)0xFFFFFFE0) + +/* ADC Analog watchdog enable mode mask */ +#define CTLR1_AWDMode_Reset ((uint32_t)0xFF3FFDFF) + +/* CTLR1 register Mask */ +#define CTLR1_CLEAR_Mask ((uint32_t)0xFFF0FEFF) + +/* ADC ADON mask */ +#define CTLR2_ADON_Set ((uint32_t)0x00000001) +#define CTLR2_ADON_Reset ((uint32_t)0xFFFFFFFE) + +/* ADC DMA mask */ +#define CTLR2_DMA_Set ((uint32_t)0x00000100) +#define CTLR2_DMA_Reset ((uint32_t)0xFFFFFEFF) + +/* ADC RSTCAL mask */ +#define CTLR2_RSTCAL_Set ((uint32_t)0x00000008) + +/* ADC CAL mask */ +#define CTLR2_CAL_Set ((uint32_t)0x00000004) + +/* ADC SWSTART mask */ +#define CTLR2_SWSTART_Set ((uint32_t)0x00400000) + +/* ADC EXTTRIG mask */ +#define CTLR2_EXTTRIG_Set ((uint32_t)0x00100000) +#define CTLR2_EXTTRIG_Reset ((uint32_t)0xFFEFFFFF) + +/* ADC Software start mask */ +#define CTLR2_EXTTRIG_SWSTART_Set ((uint32_t)0x00500000) +#define CTLR2_EXTTRIG_SWSTART_Reset ((uint32_t)0xFFAFFFFF) + +/* ADC JEXTSEL mask */ +#define CTLR2_JEXTSEL_Reset ((uint32_t)0xFFFF8FFF) + +/* ADC JEXTTRIG mask */ +#define CTLR2_JEXTTRIG_Set ((uint32_t)0x00008000) +#define CTLR2_JEXTTRIG_Reset ((uint32_t)0xFFFF7FFF) + +/* ADC JSWSTART mask */ +#define CTLR2_JSWSTART_Set ((uint32_t)0x00200000) + +/* ADC injected software start mask */ +#define CTLR2_JEXTTRIG_JSWSTART_Set ((uint32_t)0x00208000) +#define CTLR2_JEXTTRIG_JSWSTART_Reset ((uint32_t)0xFFDF7FFF) + +/* ADC TSPD mask */ +#define CTLR2_TSVREFE_Set ((uint32_t)0x00800000) +#define CTLR2_TSVREFE_Reset ((uint32_t)0xFF7FFFFF) + +/* CTLR2 register Mask */ +#define CTLR2_CLEAR_Mask ((uint32_t)0xFFF1F7FD) + +/* ADC SQx mask */ +#define RSQR3_SQ_Set ((uint32_t)0x0000001F) +#define RSQR2_SQ_Set ((uint32_t)0x0000001F) +#define RSQR1_SQ_Set ((uint32_t)0x0000001F) + +/* RSQR1 register Mask */ +#define RSQR1_CLEAR_Mask ((uint32_t)0xFF0FFFFF) + +/* ADC JSQx mask */ +#define ISQR_JSQ_Set ((uint32_t)0x0000001F) + +/* ADC JL mask */ +#define ISQR_JL_Set ((uint32_t)0x00300000) +#define ISQR_JL_Reset ((uint32_t)0xFFCFFFFF) + +/* ADC SMPx mask */ +#define SAMPTR1_SMP_Set ((uint32_t)0x00000007) +#define SAMPTR2_SMP_Set ((uint32_t)0x00000007) + +/* ADC IDATARx registers offset */ +#define IDATAR_Offset ((uint8_t)0x28) + +/* ADC1 RDATAR register base address */ +#define RDATAR_ADDRESS ((uint32_t)0x4001244C) + +/********************************************************************* + * @fn ADC_DeInit + * + * @brief Deinitializes the ADCx peripheral registers to their default + * reset values. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return none + */ +void ADC_DeInit(ADC_TypeDef *ADCx) +{ + if(ADCx == ADC1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC1, DISABLE); + } +} + +/********************************************************************* + * @fn ADC_Init + * + * @brief Initializes the ADCx peripheral according to the specified + * parameters in the ADC_InitStruct. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_InitStruct - pointer to an ADC_InitTypeDef structure that + * contains the configuration information for the specified ADC + * peripheral. + * + * @return none + */ +void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct) +{ + uint32_t tmpreg1 = 0; + uint8_t tmpreg2 = 0; + + tmpreg1 = ADCx->CTLR1; + tmpreg1 &= CTLR1_CLEAR_Mask; + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_Mode | ((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8)); + ADCx->CTLR1 = tmpreg1; + + tmpreg1 = ADCx->CTLR2; + tmpreg1 &= CTLR2_CLEAR_Mask; + tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | ADC_InitStruct->ADC_ExternalTrigConv | + ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1)); + ADCx->CTLR2 = tmpreg1; + + tmpreg1 = ADCx->RSQR1; + tmpreg1 &= RSQR1_CLEAR_Mask; + tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfChannel - (uint8_t)1); + tmpreg1 |= (uint32_t)tmpreg2 << 20; + ADCx->RSQR1 = tmpreg1; +} + +/********************************************************************* + * @fn ADC_StructInit + * + * @brief Fills each ADC_InitStruct member with its default value. + * + * @param ADC_InitStruct - pointer to an ADC_InitTypeDef structure that + * contains the configuration information for the specified ADC + * peripheral. + * + * @return none + */ +void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct) +{ + ADC_InitStruct->ADC_Mode = ADC_Mode_Independent; + ADC_InitStruct->ADC_ScanConvMode = DISABLE; + ADC_InitStruct->ADC_ContinuousConvMode = DISABLE; + ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1; + ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right; + ADC_InitStruct->ADC_NbrOfChannel = 1; +} + +/********************************************************************* + * @fn ADC_Cmd + * + * @brief Enables or disables the specified ADC peripheral. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_ADON_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_ADON_Reset; + } +} + +/********************************************************************* + * @fn ADC_DMACmd + * + * @brief Enables or disables the specified ADC DMA request. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_DMA_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_DMA_Reset; + } +} + +/********************************************************************* + * @fn ADC_ITConfig + * + * @brief Enables or disables the specified ADC interrupts. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt sources to be enabled or disabled. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState) +{ + uint8_t itmask = 0; + + itmask = (uint8_t)ADC_IT; + + if(NewState != DISABLE) + { + ADCx->CTLR1 |= itmask; + } + else + { + ADCx->CTLR1 &= (~(uint32_t)itmask); + } +} + +/********************************************************************* + * @fn ADC_ResetCalibration + * + * @brief Resets the selected ADC calibration registers. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return none + */ +void ADC_ResetCalibration(ADC_TypeDef *ADCx) +{ + ADCx->CTLR2 |= CTLR2_RSTCAL_Set; +} + +/********************************************************************* + * @fn ADC_GetResetCalibrationStatus + * + * @brief Gets the selected ADC reset calibration registers status. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_RSTCAL_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_StartCalibration + * + * @brief Starts the selected ADC calibration process. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return None + */ +void ADC_StartCalibration(ADC_TypeDef *ADCx) +{ + ADCx->CTLR2 |= CTLR2_CAL_Set; +} + +/********************************************************************* + * @fn ADC_GetCalibrationStatus + * + * @brief Gets the selected ADC calibration status. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_CAL_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_SoftwareStartConvCmd + * + * @brief Enables or disables the selected ADC software start conversion. + * + * @param ADCx - where x can be 1 or 2 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_EXTTRIG_SWSTART_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_EXTTRIG_SWSTART_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetSoftwareStartConvStatus + * + * @brief Gets the selected ADC Software start conversion Status. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_SWSTART_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_DiscModeChannelCountConfig + * + * @brief Configures the discontinuous mode for the selected ADC regular + * group channel. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * Number - specifies the discontinuous mode regular channel + * count value(1-8). + * + * @return None + */ +void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + + tmpreg1 = ADCx->CTLR1; + tmpreg1 &= CTLR1_DISCNUM_Reset; + tmpreg2 = Number - 1; + tmpreg1 |= tmpreg2 << 13; + ADCx->CTLR1 = tmpreg1; +} + +/********************************************************************* + * @fn ADC_DiscModeCmd + * + * @brief Enables or disables the discontinuous mode on regular group + * channel for the specified ADC. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_DISCEN_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_DISCEN_Reset; + } +} + +/********************************************************************* + * @fn ADC_RegularChannelConfig + * + * @brief Configures for the selected ADC regular channel its corresponding + * rank in the sequencer and its sample time. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_10 - ADC Channel10 selected. + * ADC_Channel_11 - ADC Channel11 selected. + * ADC_Channel_12 - ADC Channel12 selected. + * ADC_Channel_13 - ADC Channel13 selected. + * ADC_Channel_14 - ADC Channel14 selected. + * ADC_Channel_15 - ADC Channel15 selected. + * ADC_Channel_16 - ADC Channel16 selected. + * ADC_Channel_17 - ADC Channel17 selected. + * Rank - The rank in the regular group sequencer. + * This parameter must be between 1 to 16. + * ADC_SampleTime - The sample time value to be set for the selected channel. + * ADC_SampleTime_1Cycles5 - Sample time equal to 1.5 cycles. + * ADC_SampleTime_7Cycles5 - Sample time equal to 7.5 cycles. + * ADC_SampleTime_13Cycles5 - Sample time equal to 13.5 cycles. + * ADC_SampleTime_28Cycles5 - Sample time equal to 28.5 cycles. + * ADC_SampleTime_41Cycles5 - Sample time equal to 41.5 cycles. + * ADC_SampleTime_55Cycles5 - Sample time equal to 55.5 cycles. + * ADC_SampleTime_71Cycles5 - Sample time equal to 71.5 cycles. + * ADC_SampleTime_239Cycles5 - Sample time equal to 239.5 cycles. + * + * @return None + */ +void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0; + + if(ADC_Channel > ADC_Channel_9) + { + tmpreg1 = ADCx->SAMPTR1; + tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR1 = tmpreg1; + } + else + { + tmpreg1 = ADCx->SAMPTR2; + tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR2 = tmpreg1; + } + + if(Rank < 7) + { + tmpreg1 = ADCx->RSQR3; + tmpreg2 = RSQR3_SQ_Set << (5 * (Rank - 1)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1)); + tmpreg1 |= tmpreg2; + ADCx->RSQR3 = tmpreg1; + } + else if(Rank < 13) + { + tmpreg1 = ADCx->RSQR2; + tmpreg2 = RSQR2_SQ_Set << (5 * (Rank - 7)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7)); + tmpreg1 |= tmpreg2; + ADCx->RSQR2 = tmpreg1; + } + else + { + tmpreg1 = ADCx->RSQR1; + tmpreg2 = RSQR1_SQ_Set << (5 * (Rank - 13)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13)); + tmpreg1 |= tmpreg2; + ADCx->RSQR1 = tmpreg1; + } +} + +/********************************************************************* + * @fn ADC_ExternalTrigConvCmd + * + * @brief Enables or disables the ADCx conversion through external trigger. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_EXTTRIG_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_EXTTRIG_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetConversionValue + * + * @brief Returns the last ADCx conversion result data for regular channel. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return ADCx->RDATAR - The Data conversion value. + */ +uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx) +{ + return (uint16_t)ADCx->RDATAR; +} + +/********************************************************************* + * @fn ADC_GetDualModeConversionValue + * + * @brief Returns the last ADC1 and ADC2 conversion result data in dual mode. + * + * @return RDATAR_ADDRESS - The Data conversion value. + */ +uint32_t ADC_GetDualModeConversionValue(void) +{ + return (*(__IO uint32_t *)RDATAR_ADDRESS); +} + +/********************************************************************* + * @fn ADC_AutoInjectedConvCmd + * + * @brief Enables or disables the selected ADC automatic injected group + * conversion after regular one. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_JAUTO_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_JAUTO_Reset; + } +} + +/********************************************************************* + * @fn ADC_InjectedDiscModeCmd + * + * @brief Enables or disables the discontinuous mode for injected group + * channel for the specified ADC. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR1 |= CTLR1_JDISCEN_Set; + } + else + { + ADCx->CTLR1 &= CTLR1_JDISCEN_Reset; + } +} + +/********************************************************************* + * @fn ADC_ExternalTrigInjectedConvConfig + * + * @brief Configures the ADCx external trigger for injected channels conversion. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_ExternalTrigInjecConv - specifies the ADC trigger to start + * injected conversion. + * ADC_ExternalTrigInjecConv_T1_TRGO - Timer1 TRGO event selected. + * ADC_ExternalTrigInjecConv_T1_CC4 - Timer1 capture compare4 selected. + * ADC_ExternalTrigInjecConv_T2_TRGO - Timer2 TRGO event selected. + * ADC_ExternalTrigInjecConv_T2_CC1 - Timer2 capture compare1 selected. + * ADC_ExternalTrigInjecConv_T3_CC4 - Timer3 capture compare4 selected. + * ADC_ExternalTrigInjecConv_T4_TRGO - Timer4 TRGO event selected. + * ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 - External interrupt + * line 15 event selected. + * ADC_ExternalTrigInjecConv_None: Injected conversion started + * by software and not by external trigger. + * + * @return None + */ +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR2; + tmpreg &= CTLR2_JEXTSEL_Reset; + tmpreg |= ADC_ExternalTrigInjecConv; + ADCx->CTLR2 = tmpreg; +} + +/********************************************************************* + * @fn ADC_ExternalTrigInjectedConvCmd + * + * @brief Enables or disables the ADCx injected channels conversion through + * external trigger. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_JEXTTRIG_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_JEXTTRIG_Reset; + } +} + +/********************************************************************* + * @fn ADC_SoftwareStartInjectedConvCmd + * + * @brief Enables or disables the selected ADC start of the injected + * channels conversion. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * NewState - ENABLE or DISABLE. + * + * @return None + */ +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADCx->CTLR2 |= CTLR2_JEXTTRIG_JSWSTART_Set; + } + else + { + ADCx->CTLR2 &= CTLR2_JEXTTRIG_JSWSTART_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetSoftwareStartInjectedConvCmdStatus + * + * @brief Gets the selected ADC Software start injected conversion Status. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->CTLR2 & CTLR2_JSWSTART_Set) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_InjectedChannelConfig + * + * @brief Configures for the selected ADC injected channel its corresponding + * rank in the sequencer and its sample time. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_10 - ADC Channel10 selected. + * ADC_Channel_11 - ADC Channel11 selected. + * ADC_Channel_12 - ADC Channel12 selected. + * ADC_Channel_13 - ADC Channel13 selected. + * ADC_Channel_14 - ADC Channel14 selected. + * ADC_Channel_15 - ADC Channel15 selected. + * ADC_Channel_16 - ADC Channel16 selected. + * ADC_Channel_17 - ADC Channel17 selected. + * Rank - The rank in the regular group sequencer. + * This parameter must be between 1 to 4. + * ADC_SampleTime - The sample time value to be set for the selected channel. + * ADC_SampleTime_1Cycles5 - Sample time equal to 1.5 cycles. + * ADC_SampleTime_7Cycles5 - Sample time equal to 7.5 cycles. + * ADC_SampleTime_13Cycles5 - Sample time equal to 13.5 cycles. + * ADC_SampleTime_28Cycles5 - Sample time equal to 28.5 cycles. + * ADC_SampleTime_41Cycles5 - Sample time equal to 41.5 cycles. + * ADC_SampleTime_55Cycles5 - Sample time equal to 55.5 cycles. + * ADC_SampleTime_71Cycles5 - Sample time equal to 71.5 cycles. + * ADC_SampleTime_239Cycles5 - Sample time equal to 239.5 cycles. + * + * @return None + */ +void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime) +{ + uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0; + + if(ADC_Channel > ADC_Channel_9) + { + tmpreg1 = ADCx->SAMPTR1; + tmpreg2 = SAMPTR1_SMP_Set << (3 * (ADC_Channel - 10)); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10)); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR1 = tmpreg1; + } + else + { + tmpreg1 = ADCx->SAMPTR2; + tmpreg2 = SAMPTR2_SMP_Set << (3 * ADC_Channel); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel); + tmpreg1 |= tmpreg2; + ADCx->SAMPTR2 = tmpreg1; + } + + tmpreg1 = ADCx->ISQR; + tmpreg3 = (tmpreg1 & ISQR_JL_Set) >> 20; + tmpreg2 = ISQR_JSQ_Set << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + tmpreg1 &= ~tmpreg2; + tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1))); + tmpreg1 |= tmpreg2; + ADCx->ISQR = tmpreg1; +} + +/********************************************************************* + * @fn ADC_InjectedSequencerLengthConfig + * + * @brief Configures the sequencer length for injected channels. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * Length - The sequencer length. + * This parameter must be a number between 1 to 4. + * + * @return None + */ +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length) +{ + uint32_t tmpreg1 = 0; + uint32_t tmpreg2 = 0; + + tmpreg1 = ADCx->ISQR; + tmpreg1 &= ISQR_JL_Reset; + tmpreg2 = Length - 1; + tmpreg1 |= tmpreg2 << 20; + ADCx->ISQR = tmpreg1; +} + +/********************************************************************* + * @fn ADC_SetInjectedOffset + * + * @brief Set the injected channels conversion value offset. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_InjectedChannel: the ADC injected channel to set its offset. + * ADC_InjectedChannel_1 - Injected Channel1 selected. + * ADC_InjectedChannel_2 - Injected Channel2 selected. + * ADC_InjectedChannel_3 - Injected Channel3 selected. + * ADC_InjectedChannel_4 - Injected Channel4 selected. + * Offset - the offset value for the selected ADC injected channel. + * This parameter must be a 12bit value. + * + * @return None + */ +void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel; + + *(__IO uint32_t *)tmp = (uint32_t)Offset; +} + +/********************************************************************* + * @fn ADC_GetInjectedConversionValue + * + * @brief Returns the ADC injected channel conversion result. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_InjectedChannel - the ADC injected channel to set its offset. + * ADC_InjectedChannel_1 - Injected Channel1 selected. + * ADC_InjectedChannel_2 - Injected Channel2 selected. + * ADC_InjectedChannel_3 - Injected Channel3 selected. + * ADC_InjectedChannel_4 - Injected Channel4 selected. + * + * @return tmp - The Data conversion value. + */ +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel) +{ + __IO uint32_t tmp = 0; + + tmp = (uint32_t)ADCx; + tmp += ADC_InjectedChannel + IDATAR_Offset; + + return (uint16_t)(*(__IO uint32_t *)tmp); +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogCmd + * + * @brief Enables or disables the analog watchdog on single/all regular + * or injected channels. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_AnalogWatchdog - the ADC analog watchdog configuration. + * ADC_AnalogWatchdog_SingleRegEnable - Analog watchdog on a + * single regular channel. + * ADC_AnalogWatchdog_SingleInjecEnable - Analog watchdog on a + * single injected channel. + * ADC_AnalogWatchdog_SingleRegOrInjecEnable - Analog watchdog + * on a single regular or injected channel. + * ADC_AnalogWatchdog_AllRegEnable - Analog watchdog on all + * regular channel. + * ADC_AnalogWatchdog_AllInjecEnable - Analog watchdog on all + * injected channel. + * ADC_AnalogWatchdog_AllRegAllInjecEnable - Analog watchdog on + * all regular and injected channels. + * ADC_AnalogWatchdog_None - No channel guarded by the analog + * watchdog. + * + * @return none + */ +void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR1; + tmpreg &= CTLR1_AWDMode_Reset; + tmpreg |= ADC_AnalogWatchdog; + ADCx->CTLR1 = tmpreg; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogThresholdsConfig + * + * @brief Configures the high and low thresholds of the analog watchdog. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * HighThreshold - the ADC analog watchdog High threshold value. + * This parameter must be a 12bit value. + * LowThreshold - the ADC analog watchdog Low threshold value. + * This parameter must be a 12bit value. + * + * @return none + */ +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, + uint16_t LowThreshold) +{ + ADCx->WDHTR = HighThreshold; + ADCx->WDLTR = LowThreshold; +} + +/********************************************************************* + * @fn ADC_AnalogWatchdogSingleChannelConfig + * + * @brief Configures the analog watchdog guarded single channel. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_Channel - the ADC channel to configure. + * ADC_Channel_0 - ADC Channel0 selected. + * ADC_Channel_1 - ADC Channel1 selected. + * ADC_Channel_2 - ADC Channel2 selected. + * ADC_Channel_3 - ADC Channel3 selected. + * ADC_Channel_4 - ADC Channel4 selected. + * ADC_Channel_5 - ADC Channel5 selected. + * ADC_Channel_6 - ADC Channel6 selected. + * ADC_Channel_7 - ADC Channel7 selected. + * ADC_Channel_8 - ADC Channel8 selected. + * ADC_Channel_9 - ADC Channel9 selected. + * ADC_Channel_10 - ADC Channel10 selected. + * ADC_Channel_11 - ADC Channel11 selected. + * ADC_Channel_12 - ADC Channel12 selected. + * ADC_Channel_13 - ADC Channel13 selected. + * ADC_Channel_14 - ADC Channel14 selected. + * ADC_Channel_15 - ADC Channel15 selected. + * ADC_Channel_16 - ADC Channel16 selected. + * ADC_Channel_17 - ADC Channel17 selected. + * + * @return None + */ +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel) +{ + uint32_t tmpreg = 0; + + tmpreg = ADCx->CTLR1; + tmpreg &= CTLR1_AWDCH_Reset; + tmpreg |= ADC_Channel; + ADCx->CTLR1 = tmpreg; +} + +/********************************************************************* + * @fn ADC_TempSensorVrefintCmd + * + * @brief Enables or disables the temperature sensor and Vrefint channel. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void ADC_TempSensorVrefintCmd(FunctionalState NewState) +{ + if(NewState != DISABLE) + { + ADC1->CTLR2 |= CTLR2_TSVREFE_Set; + } + else + { + ADC1->CTLR2 &= CTLR2_TSVREFE_Reset; + } +} + +/********************************************************************* + * @fn ADC_GetFlagStatus + * + * @brief Checks whether the specified ADC flag is set or not. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_FLAG - specifies the flag to check. + * ADC_FLAG_AWD - Analog watchdog flag. + * ADC_FLAG_EOC - End of conversion flag. + * ADC_FLAG_JEOC - End of injected group conversion flag. + * ADC_FLAG_JSTRT - Start of injected group conversion flag. + * ADC_FLAG_STRT - Start of regular group conversion flag. + * + * @return FlagStatus: SET or RESET. + */ +FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((ADCx->STATR & ADC_FLAG) != (uint8_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_ClearFlag + * + * @brief Clears the ADCx's pending flags. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_FLAG - specifies the flag to clear. + * ADC_FLAG_AWD - Analog watchdog flag. + * ADC_FLAG_EOC - End of conversion flag. + * ADC_FLAG_JEOC - End of injected group conversion flag. + * ADC_FLAG_JSTRT - Start of injected group conversion flag. + * ADC_FLAG_STRT - Start of regular group conversion flag. + * + * @return none + */ +void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG) +{ + ADCx->STATR = ~(uint32_t)ADC_FLAG; +} + +/********************************************************************* + * @fn ADC_GetITStatus + * + * @brief Checks whether the specified ADC interrupt has occurred or not. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt source to check. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * + * @return ITStatus: SET or RESET. + */ +ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT) +{ + ITStatus bitstatus = RESET; + uint32_t itmask = 0, enablestatus = 0; + + itmask = ADC_IT >> 8; + enablestatus = (ADCx->CTLR1 & (uint8_t)ADC_IT); + + if(((ADCx->STATR & itmask) != (uint32_t)RESET) && enablestatus) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn ADC_ClearITPendingBit + * + * @brief Clears the ADCx's interrupt pending bits. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * ADC_IT - specifies the ADC interrupt pending bit to clear. + * ADC_IT_EOC - End of conversion interrupt mask. + * ADC_IT_AWD - Analog watchdog interrupt mask. + * ADC_IT_JEOC - End of injected conversion interrupt mask. + * + * @return none + */ +void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT) +{ + uint8_t itmask = 0; + + itmask = (uint8_t)(ADC_IT >> 8); + ADCx->STATR = ~(uint32_t)itmask; +} + +/********************************************************************* + * @fn TempSensor_Volt_To_Temper + * + * @brief Internal Temperature Sensor Voltage to temperature. + * + * @param Value - Voltage Value(mv). + * + * @return Temper - Temperature Value. + */ +s32 TempSensor_Volt_To_Temper(s32 Value) +{ + s32 Temper, Refer_Volt, Refer_Temper; + s32 k = 43; + + Refer_Volt = (s32)((*(u32 *)0x1FFFF898) & 0x0000FFFF); + Refer_Temper = (s32)(((*(u32 *)0x1FFFF898) >> 16) & 0x0000FFFF); + + Temper = Refer_Temper + ((Value - Refer_Volt) * 10 + (k >> 1)) / k; + + return Temper; +} + +/********************************************************************* + * @fn Get_CalibrationValue + * + * @brief Get ADCx Calibration Value. + * + * @param ADCx - where x can be 1 to select the ADC peripheral. + * + * @return CalibrationValue + */ +int16_t Get_CalibrationValue(ADC_TypeDef *ADCx) +{ + __IO uint8_t i, j; + uint16_t buf[10]; + __IO uint16_t t; + + for(i = 0; i < 10; i++){ + ADC_ResetCalibration(ADCx); + while(ADC_GetResetCalibrationStatus(ADCx)); + ADC_StartCalibration(ADCx); + while(ADC_GetCalibrationStatus(ADCx)); + buf[i] = ADCx->RDATAR; + } + + for(i = 0; i < 10; i++){ + for(j = 0; j < 9; j++){ + if(buf[j] > buf[j + 1]){ + t = buf[j]; + buf[j] = buf[j + 1]; + buf[j+1] = t; + } + } + } + + t = 0; + for(i = 0; i < 6; i++){ + t += buf[i + 2]; + } + + t = (t / 6) + ((t % 6) / 3); + + return (int16_t)(2048 - (int16_t)t); +} diff --git a/ch32v103_hallarray_controller/src/periph/ch32v10x_adc.h b/ch32v103_hallarray_controller/src/periph/ch32v10x_adc.h new file mode 100644 index 0000000..15fac0e --- /dev/null +++ b/ch32v103_hallarray_controller/src/periph/ch32v10x_adc.h @@ -0,0 +1,190 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_adc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : This file contains all the functions prototypes for the + * ADC firmware library. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#ifndef __CH32V10x_ADC_H +#define __CH32V10x_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v10x.h" + +/* ADC Init structure definition */ +typedef struct +{ + uint32_t ADC_Mode; /* Configures the ADC to operate in independent or + dual mode. + This parameter can be a value of @ref ADC_mode */ + + FunctionalState ADC_ScanConvMode; /* Specifies whether the conversion is performed in + Scan (multichannels) or Single (one channel) mode. + This parameter can be set to ENABLE or DISABLE */ + + FunctionalState ADC_ContinuousConvMode; /* Specifies whether the conversion is performed in + Continuous or Single mode. + This parameter can be set to ENABLE or DISABLE. */ + + uint32_t ADC_ExternalTrigConv; /* Defines the external trigger used to start the analog + to digital conversion of regular channels. This parameter + can be a value of @ref ADC_external_trigger_sources_for_regular_channels_conversion */ + + uint32_t ADC_DataAlign; /* Specifies whether the ADC data alignment is left or right. + This parameter can be a value of @ref ADC_data_align */ + + uint8_t ADC_NbrOfChannel; /* Specifies the number of ADC channels that will be converted + using the sequencer for regular channel group. + This parameter must range from 1 to 16. */ +} ADC_InitTypeDef; + +/* ADC_mode */ +#define ADC_Mode_Independent ((uint32_t)0x00000000) +#define ADC_Mode_RegInjecSimult ((uint32_t)0x00010000) +#define ADC_Mode_RegSimult_AlterTrig ((uint32_t)0x00020000) +#define ADC_Mode_InjecSimult_FastInterl ((uint32_t)0x00030000) +#define ADC_Mode_InjecSimult_SlowInterl ((uint32_t)0x00040000) +#define ADC_Mode_InjecSimult ((uint32_t)0x00050000) +#define ADC_Mode_RegSimult ((uint32_t)0x00060000) +#define ADC_Mode_FastInterl ((uint32_t)0x00070000) +#define ADC_Mode_SlowInterl ((uint32_t)0x00080000) +#define ADC_Mode_AlterTrig ((uint32_t)0x00090000) + +/* ADC_external_trigger_sources_for_regular_channels_conversion */ +#define ADC_ExternalTrigConv_T1_CC1 ((uint32_t)0x00000000) +#define ADC_ExternalTrigConv_T1_CC2 ((uint32_t)0x00020000) +#define ADC_ExternalTrigConv_T2_CC2 ((uint32_t)0x00060000) +#define ADC_ExternalTrigConv_T3_TRGO ((uint32_t)0x00080000) +#define ADC_ExternalTrigConv_T4_CC4 ((uint32_t)0x000A0000) +#define ADC_ExternalTrigConv_Ext_IT11_TIM8_TRGO ((uint32_t)0x000C0000) + +#define ADC_ExternalTrigConv_T1_CC3 ((uint32_t)0x00040000) +#define ADC_ExternalTrigConv_None ((uint32_t)0x000E0000) + +/* ADC_data_align */ +#define ADC_DataAlign_Right ((uint32_t)0x00000000) +#define ADC_DataAlign_Left ((uint32_t)0x00000800) + +/* ADC_channels */ +#define ADC_Channel_0 ((uint8_t)0x00) +#define ADC_Channel_1 ((uint8_t)0x01) +#define ADC_Channel_2 ((uint8_t)0x02) +#define ADC_Channel_3 ((uint8_t)0x03) +#define ADC_Channel_4 ((uint8_t)0x04) +#define ADC_Channel_5 ((uint8_t)0x05) +#define ADC_Channel_6 ((uint8_t)0x06) +#define ADC_Channel_7 ((uint8_t)0x07) +#define ADC_Channel_8 ((uint8_t)0x08) +#define ADC_Channel_9 ((uint8_t)0x09) +#define ADC_Channel_10 ((uint8_t)0x0A) +#define ADC_Channel_11 ((uint8_t)0x0B) +#define ADC_Channel_12 ((uint8_t)0x0C) +#define ADC_Channel_13 ((uint8_t)0x0D) +#define ADC_Channel_14 ((uint8_t)0x0E) +#define ADC_Channel_15 ((uint8_t)0x0F) +#define ADC_Channel_16 ((uint8_t)0x10) +#define ADC_Channel_17 ((uint8_t)0x11) + +#define ADC_Channel_TempSensor ((uint8_t)ADC_Channel_16) +#define ADC_Channel_Vrefint ((uint8_t)ADC_Channel_17) + +/* ADC_sampling_time */ +#define ADC_SampleTime_1Cycles5 ((uint8_t)0x00) +#define ADC_SampleTime_7Cycles5 ((uint8_t)0x01) +#define ADC_SampleTime_13Cycles5 ((uint8_t)0x02) +#define ADC_SampleTime_28Cycles5 ((uint8_t)0x03) +#define ADC_SampleTime_41Cycles5 ((uint8_t)0x04) +#define ADC_SampleTime_55Cycles5 ((uint8_t)0x05) +#define ADC_SampleTime_71Cycles5 ((uint8_t)0x06) +#define ADC_SampleTime_239Cycles5 ((uint8_t)0x07) + +/* ADC_external_trigger_sources_for_injected_channels_conversion */ +#define ADC_ExternalTrigInjecConv_T2_TRGO ((uint32_t)0x00002000) +#define ADC_ExternalTrigInjecConv_T2_CC1 ((uint32_t)0x00003000) +#define ADC_ExternalTrigInjecConv_T3_CC4 ((uint32_t)0x00004000) +#define ADC_ExternalTrigInjecConv_T4_TRGO ((uint32_t)0x00005000) +#define ADC_ExternalTrigInjecConv_Ext_IT15_TIM8_CC4 ((uint32_t)0x00006000) + +#define ADC_ExternalTrigInjecConv_T1_TRGO ((uint32_t)0x00000000) +#define ADC_ExternalTrigInjecConv_T1_CC4 ((uint32_t)0x00001000) +#define ADC_ExternalTrigInjecConv_None ((uint32_t)0x00007000) + +/* ADC_injected_channel_selection */ +#define ADC_InjectedChannel_1 ((uint8_t)0x14) +#define ADC_InjectedChannel_2 ((uint8_t)0x18) +#define ADC_InjectedChannel_3 ((uint8_t)0x1C) +#define ADC_InjectedChannel_4 ((uint8_t)0x20) + +/* ADC_analog_watchdog_selection */ +#define ADC_AnalogWatchdog_SingleRegEnable ((uint32_t)0x00800200) +#define ADC_AnalogWatchdog_SingleInjecEnable ((uint32_t)0x00400200) +#define ADC_AnalogWatchdog_SingleRegOrInjecEnable ((uint32_t)0x00C00200) +#define ADC_AnalogWatchdog_AllRegEnable ((uint32_t)0x00800000) +#define ADC_AnalogWatchdog_AllInjecEnable ((uint32_t)0x00400000) +#define ADC_AnalogWatchdog_AllRegAllInjecEnable ((uint32_t)0x00C00000) +#define ADC_AnalogWatchdog_None ((uint32_t)0x00000000) + +/* ADC_interrupts_definition */ +#define ADC_IT_EOC ((uint16_t)0x0220) +#define ADC_IT_AWD ((uint16_t)0x0140) +#define ADC_IT_JEOC ((uint16_t)0x0480) + +/* ADC_flags_definition */ +#define ADC_FLAG_AWD ((uint8_t)0x01) +#define ADC_FLAG_EOC ((uint8_t)0x02) +#define ADC_FLAG_JEOC ((uint8_t)0x04) +#define ADC_FLAG_JSTRT ((uint8_t)0x08) +#define ADC_FLAG_STRT ((uint8_t)0x10) + +void ADC_DeInit(ADC_TypeDef *ADCx); +void ADC_Init(ADC_TypeDef *ADCx, ADC_InitTypeDef *ADC_InitStruct); +void ADC_StructInit(ADC_InitTypeDef *ADC_InitStruct); +void ADC_Cmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_DMACmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_ITConfig(ADC_TypeDef *ADCx, uint16_t ADC_IT, FunctionalState NewState); +void ADC_ResetCalibration(ADC_TypeDef *ADCx); +FlagStatus ADC_GetResetCalibrationStatus(ADC_TypeDef *ADCx); +void ADC_StartCalibration(ADC_TypeDef *ADCx); +FlagStatus ADC_GetCalibrationStatus(ADC_TypeDef *ADCx); +void ADC_SoftwareStartConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef *ADCx); +void ADC_DiscModeChannelCountConfig(ADC_TypeDef *ADCx, uint8_t Number); +void ADC_DiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_RegularChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_ExternalTrigConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +uint16_t ADC_GetConversionValue(ADC_TypeDef *ADCx); +uint32_t ADC_GetDualModeConversionValue(void); +void ADC_AutoInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_InjectedDiscModeCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef *ADCx, uint32_t ADC_ExternalTrigInjecConv); +void ADC_ExternalTrigInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +void ADC_SoftwareStartInjectedConvCmd(ADC_TypeDef *ADCx, FunctionalState NewState); +FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef *ADCx); +void ADC_InjectedChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime); +void ADC_InjectedSequencerLengthConfig(ADC_TypeDef *ADCx, uint8_t Length); +void ADC_SetInjectedOffset(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset); +uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef *ADCx, uint8_t ADC_InjectedChannel); +void ADC_AnalogWatchdogCmd(ADC_TypeDef *ADCx, uint32_t ADC_AnalogWatchdog); +void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef *ADCx, uint16_t HighThreshold, uint16_t LowThreshold); +void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef *ADCx, uint8_t ADC_Channel); +void ADC_TempSensorVrefintCmd(FunctionalState NewState); +FlagStatus ADC_GetFlagStatus(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); +void ADC_ClearFlag(ADC_TypeDef *ADCx, uint8_t ADC_FLAG); +ITStatus ADC_GetITStatus(ADC_TypeDef *ADCx, uint16_t ADC_IT); +void ADC_ClearITPendingBit(ADC_TypeDef *ADCx, uint16_t ADC_IT); +s32 TempSensor_Volt_To_Temper(s32 Value); +int16_t Get_CalibrationValue(ADC_TypeDef *ADCx); + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32V10x_ADC_H */ diff --git a/ch32v103_hallarray_controller/src/periph/ch32v10x_dma.c b/ch32v103_hallarray_controller/src/periph/ch32v10x_dma.c new file mode 100644 index 0000000..0ade3e1 --- /dev/null +++ b/ch32v103_hallarray_controller/src/periph/ch32v10x_dma.c @@ -0,0 +1,552 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_dma.c + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : This file provides all the DMA firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v10x_dma.h" +#include "ch32v10x_rcc.h" + +/* DMA1 Channelx interrupt pending bit masks */ +#define DMA1_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) +#define DMA1_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) +#define DMA1_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) +#define DMA1_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) +#define DMA1_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) +#define DMA1_Channel6_IT_Mask ((uint32_t)(DMA_GIF6 | DMA_TCIF6 | DMA_HTIF6 | DMA_TEIF6)) +#define DMA1_Channel7_IT_Mask ((uint32_t)(DMA_GIF7 | DMA_TCIF7 | DMA_HTIF7 | DMA_TEIF7)) + +/* DMA2 Channelx interrupt pending bit masks */ +#define DMA2_Channel1_IT_Mask ((uint32_t)(DMA_GIF1 | DMA_TCIF1 | DMA_HTIF1 | DMA_TEIF1)) +#define DMA2_Channel2_IT_Mask ((uint32_t)(DMA_GIF2 | DMA_TCIF2 | DMA_HTIF2 | DMA_TEIF2)) +#define DMA2_Channel3_IT_Mask ((uint32_t)(DMA_GIF3 | DMA_TCIF3 | DMA_HTIF3 | DMA_TEIF3)) +#define DMA2_Channel4_IT_Mask ((uint32_t)(DMA_GIF4 | DMA_TCIF4 | DMA_HTIF4 | DMA_TEIF4)) +#define DMA2_Channel5_IT_Mask ((uint32_t)(DMA_GIF5 | DMA_TCIF5 | DMA_HTIF5 | DMA_TEIF5)) + +/* DMA2 FLAG mask */ +#define FLAG_Mask ((uint32_t)0x10000000) + +/* DMA registers Masks */ +#define CFGR_CLEAR_Mask ((uint32_t)0xFFFF800F) + +/********************************************************************* + * @fn DMA_DeInit + * + * @brief Deinitializes the DMAy Channelx registers to their default + * reset values. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * + * @return none + */ +void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx) +{ + DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); + DMAy_Channelx->CFGR = 0; + DMAy_Channelx->CNTR = 0; + DMAy_Channelx->PADDR = 0; + DMAy_Channelx->MADDR = 0; + if(DMAy_Channelx == DMA1_Channel1) + { + DMA1->INTFCR |= DMA1_Channel1_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel2) + { + DMA1->INTFCR |= DMA1_Channel2_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel3) + { + DMA1->INTFCR |= DMA1_Channel3_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel4) + { + DMA1->INTFCR |= DMA1_Channel4_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel5) + { + DMA1->INTFCR |= DMA1_Channel5_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel6) + { + DMA1->INTFCR |= DMA1_Channel6_IT_Mask; + } + else if(DMAy_Channelx == DMA1_Channel7) + { + DMA1->INTFCR |= DMA1_Channel7_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel1) + { + DMA2->INTFCR |= DMA2_Channel1_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel2) + { + DMA2->INTFCR |= DMA2_Channel2_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel3) + { + DMA2->INTFCR |= DMA2_Channel3_IT_Mask; + } + else if(DMAy_Channelx == DMA2_Channel4) + { + DMA2->INTFCR |= DMA2_Channel4_IT_Mask; + } + else + { + if(DMAy_Channelx == DMA2_Channel5) + { + DMA2->INTFCR |= DMA2_Channel5_IT_Mask; + } + } +} + +/********************************************************************* + * @fn DMA_Init + * + * @brief Initializes the DMAy Channelx according to the specified + * parameters in the DMA_InitStruct. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains + * contains the configuration information for the specified DMA Channel. + * + * @return none + */ +void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct) +{ + uint32_t tmpreg = 0; + + tmpreg = DMAy_Channelx->CFGR; + tmpreg &= CFGR_CLEAR_Mask; + tmpreg |= DMA_InitStruct->DMA_DIR | DMA_InitStruct->DMA_Mode | + DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc | + DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize | + DMA_InitStruct->DMA_Priority | DMA_InitStruct->DMA_M2M; + + DMAy_Channelx->CFGR = tmpreg; + DMAy_Channelx->CNTR = DMA_InitStruct->DMA_BufferSize; + DMAy_Channelx->PADDR = DMA_InitStruct->DMA_PeripheralBaseAddr; + DMAy_Channelx->MADDR = DMA_InitStruct->DMA_MemoryBaseAddr; +} + +/********************************************************************* + * @fn DMA_StructInit + * + * @brief Fills each DMA_InitStruct member with its default value. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * DMA_InitStruct - pointer to a DMA_InitTypeDef structure that contains + * contains the configuration information for the specified DMA Channel. + * + * @return none + */ +void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct) +{ + DMA_InitStruct->DMA_PeripheralBaseAddr = 0; + DMA_InitStruct->DMA_MemoryBaseAddr = 0; + DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralSRC; + DMA_InitStruct->DMA_BufferSize = 0; + DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable; + DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; + DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; + DMA_InitStruct->DMA_Mode = DMA_Mode_Normal; + DMA_InitStruct->DMA_Priority = DMA_Priority_Low; + DMA_InitStruct->DMA_M2M = DMA_M2M_Disable; +} + +/********************************************************************* + * @fn DMA_Cmd + * + * @brief Enables or disables the specified DMAy Channelx. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). + * + * @return none + */ +void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMAy_Channelx->CFGR |= DMA_CFGR1_EN; + } + else + { + DMAy_Channelx->CFGR &= (uint16_t)(~DMA_CFGR1_EN); + } +} + +/********************************************************************* + * @fn DMA_ITConfig + * + * @brief Enables or disables the specified DMAy Channelx interrupts. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * DMA_IT - specifies the DMA interrupts sources to be enabled + * or disabled. + * DMA_IT_TC - Transfer complete interrupt mask + * DMA_IT_HT - Half transfer interrupt mask + * DMA_IT_TE - Transfer error interrupt mask + * NewState - new state of the DMAy Channelx(ENABLE or DISABLE). + * + * @return none + */ +void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + DMAy_Channelx->CFGR |= DMA_IT; + } + else + { + DMAy_Channelx->CFGR &= ~DMA_IT; + } +} + +/********************************************************************* + * @fn DMA_SetCurrDataCounter + * + * @brief Sets the number of data units in the current DMAy Channelx transfer. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * DataNumber - The number of data units in the current DMAy Channelx + * transfer. + * + * @return none + */ +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber) +{ + DMAy_Channelx->CNTR = DataNumber; +} + +/********************************************************************* + * @fn DMA_GetCurrDataCounter + * + * @brief Returns the number of remaining data units in the current + * DMAy Channelx transfer. + * + * @param DMAy_Channelx - here y can be 1 or 2 to select the DMA and x can be + * 1 to 7 for DMA1 and 1 to 5 for DMA2 to select the DMA Channel. + * + * @return DataNumber - The number of remaining data units in the current + * DMAy Channelx transfer. + */ +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx) +{ + return ((uint16_t)(DMAy_Channelx->CNTR)); +} + +/********************************************************************* + * @fn DMA_GetFlagStatus + * + * @brief Checks whether the specified DMAy Channelx flag is set or not. + * + * @param DMAy_FLAG - specifies the flag to check. + * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. + * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. + * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. + * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. + * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. + * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. + * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. + * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. + * DMA2_FLAG_GL1 - DMA2 Channel1 global flag. + * DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag. + * DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag. + * DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag. + * DMA2_FLAG_GL2 - DMA2 Channel2 global flag. + * DMA2_FLAG_TC2 - DMA2 Channel2 transfer complete flag. + * DMA2_FLAG_HT2 - DMA2 Channel2 half transfer flag. + * DMA2_FLAG_TE2 - DMA2 Channel2 transfer error flag. + * DMA2_FLAG_GL3 - DMA2 Channel3 global flag. + * DMA2_FLAG_TC3 - DMA2 Channel3 transfer complete flag. + * DMA2_FLAG_HT3 - DMA2 Channel3 half transfer flag. + * DMA2_FLAG_TE3 - DMA2 Channel3 transfer error flag. + * DMA2_FLAG_GL4 - DMA2 Channel4 global flag. + * DMA2_FLAG_TC4 - DMA2 Channel4 transfer complete flag. + * DMA2_FLAG_HT4 - DMA2 Channel4 half transfer flag. + * DMA2_FLAG_TE4 - DMA2 Channel4 transfer error flag. + * DMA2_FLAG_GL5 - DMA2 Channel5 global flag. + * DMA2_FLAG_TC5 - DMA2 Channel5 transfer complete flag. + * DMA2_FLAG_HT5 - DMA2 Channel5 half transfer flag. + * DMA2_FLAG_TE5 - DMA2 Channel5 transfer error flag. + * + * @return The new state of DMAy_FLAG (SET or RESET). + */ +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG) +{ + FlagStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + if((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET) + { + tmpreg = DMA2->INTFR; + } + else + { + tmpreg = DMA1->INTFR; + } + + if((tmpreg & DMAy_FLAG) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn DMA_ClearFlag + * + * @brief Clears the DMAy Channelx's pending flags. + * + * @param DMAy_FLAG - specifies the flag to check. + * DMA1_FLAG_GL1 - DMA1 Channel1 global flag. + * DMA1_FLAG_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_FLAG_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_FLAG_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_FLAG_GL2 - DMA1 Channel2 global flag. + * DMA1_FLAG_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_FLAG_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_FLAG_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_FLAG_GL3 - DMA1 Channel3 global flag. + * DMA1_FLAG_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_FLAG_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_FLAG_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_FLAG_GL4 - DMA1 Channel4 global flag. + * DMA1_FLAG_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_FLAG_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_FLAG_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_FLAG_GL5 - DMA1 Channel5 global flag. + * DMA1_FLAG_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_FLAG_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_FLAG_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_FLAG_GL6 - DMA1 Channel6 global flag. + * DMA1_FLAG_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_FLAG_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_FLAG_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_FLAG_GL7 - DMA1 Channel7 global flag. + * DMA1_FLAG_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_FLAG_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_FLAG_TE7 - DMA1 Channel7 transfer error flag. + * DMA2_FLAG_GL1 - DMA2 Channel1 global flag. + * DMA2_FLAG_TC1 - DMA2 Channel1 transfer complete flag. + * DMA2_FLAG_HT1 - DMA2 Channel1 half transfer flag. + * DMA2_FLAG_TE1 - DMA2 Channel1 transfer error flag. + * DMA2_FLAG_GL2 - DMA2 Channel2 global flag. + * DMA2_FLAG_TC2 - DMA2 Channel2 transfer complete flag. + * DMA2_FLAG_HT2 - DMA2 Channel2 half transfer flag. + * DMA2_FLAG_TE2 - DMA2 Channel2 transfer error flag. + * DMA2_FLAG_GL3 - DMA2 Channel3 global flag. + * DMA2_FLAG_TC3 - DMA2 Channel3 transfer complete flag. + * DMA2_FLAG_HT3 - DMA2 Channel3 half transfer flag. + * DMA2_FLAG_TE3 - DMA2 Channel3 transfer error flag. + * DMA2_FLAG_GL4 - DMA2 Channel4 global flag. + * DMA2_FLAG_TC4 - DMA2 Channel4 transfer complete flag. + * DMA2_FLAG_HT4 - DMA2 Channel4 half transfer flag. + * DMA2_FLAG_TE4 - DMA2 Channel4 transfer error flag. + * DMA2_FLAG_GL5 - DMA2 Channel5 global flag. + * DMA2_FLAG_TC5 - DMA2 Channel5 transfer complete flag. + * DMA2_FLAG_HT5 - DMA2 Channel5 half transfer flag. + * DMA2_FLAG_TE5 - DMA2 Channel5 transfer error flag. + * + * @return none + */ +void DMA_ClearFlag(uint32_t DMAy_FLAG) +{ + if((DMAy_FLAG & FLAG_Mask) != (uint32_t)RESET) + { + DMA2->INTFCR = DMAy_FLAG; + } + else + { + DMA1->INTFCR = DMAy_FLAG; + } +} + +/********************************************************************* + * @fn DMA_GetITStatus + * + * @brief Checks whether the specified DMAy Channelx interrupt has + * occurred or not. + * + * @param DMAy_IT - specifies the DMAy interrupt source to check. + * DMA1_IT_GL1 - DMA1 Channel1 global flag. + * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_IT_GL2 - DMA1 Channel2 global flag. + * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_IT_GL3 - DMA1 Channel3 global flag. + * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_IT_GL4 - DMA1 Channel4 global flag. + * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_IT_GL5 - DMA1 Channel5 global flag. + * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_IT_GL6 - DMA1 Channel6 global flag. + * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_IT_GL7 - DMA1 Channel7 global flag. + * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. + * DMA2_IT_GL1 - DMA2 Channel1 global flag. + * DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag. + * DMA2_IT_HT1 - DMA2 Channel1 half transfer flag. + * DMA2_IT_TE1 - DMA2 Channel1 transfer error flag. + * DMA2_IT_GL2 - DMA2 Channel2 global flag. + * DMA2_IT_TC2 - DMA2 Channel2 transfer complete flag. + * DMA2_IT_HT2 - DMA2 Channel2 half transfer flag. + * DMA2_IT_TE2 - DMA2 Channel2 transfer error flag. + * DMA2_IT_GL3 - DMA2 Channel3 global flag. + * DMA2_IT_TC3 - DMA2 Channel3 transfer complete flag. + * DMA2_IT_HT3 - DMA2 Channel3 half transfer flag. + * DMA2_IT_TE3 - DMA2 Channel3 transfer error flag. + * DMA2_IT_GL4 - DMA2 Channel4 global flag. + * DMA2_IT_TC4 - DMA2 Channel4 transfer complete flag. + * DMA2_IT_HT4 - DMA2 Channel4 half transfer flag. + * DMA2_IT_TE4 - DMA2 Channel4 transfer error flag. + * DMA2_IT_GL5 - DMA2 Channel5 global flag. + * DMA2_IT_TC5 - DMA2 Channel5 transfer complete flag. + * DMA2_IT_HT5 - DMA2 Channel5 half transfer flag. + * DMA2_IT_TE5 - DMA2 Channel5 transfer error flag. + * + * @return The new state of DMAy_IT (SET or RESET). + */ +ITStatus DMA_GetITStatus(uint32_t DMAy_IT) +{ + ITStatus bitstatus = RESET; + uint32_t tmpreg = 0; + + if((DMAy_IT & FLAG_Mask) != (uint32_t)RESET) + { + tmpreg = DMA2->INTFR; + } + else + { + tmpreg = DMA1->INTFR; + } + + if((tmpreg & DMAy_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn DMA_ClearITPendingBit + * + * @brief Clears the DMAy Channelx's interrupt pending bits. + * + * @param DMAy_IT - specifies the DMAy interrupt source to check. + * DMA1_IT_GL1 - DMA1 Channel1 global flag. + * DMA1_IT_TC1 - DMA1 Channel1 transfer complete flag. + * DMA1_IT_HT1 - DMA1 Channel1 half transfer flag. + * DMA1_IT_TE1 - DMA1 Channel1 transfer error flag. + * DMA1_IT_GL2 - DMA1 Channel2 global flag. + * DMA1_IT_TC2 - DMA1 Channel2 transfer complete flag. + * DMA1_IT_HT2 - DMA1 Channel2 half transfer flag. + * DMA1_IT_TE2 - DMA1 Channel2 transfer error flag. + * DMA1_IT_GL3 - DMA1 Channel3 global flag. + * DMA1_IT_TC3 - DMA1 Channel3 transfer complete flag. + * DMA1_IT_HT3 - DMA1 Channel3 half transfer flag. + * DMA1_IT_TE3 - DMA1 Channel3 transfer error flag. + * DMA1_IT_GL4 - DMA1 Channel4 global flag. + * DMA1_IT_TC4 - DMA1 Channel4 transfer complete flag. + * DMA1_IT_HT4 - DMA1 Channel4 half transfer flag. + * DMA1_IT_TE4 - DMA1 Channel4 transfer error flag. + * DMA1_IT_GL5 - DMA1 Channel5 global flag. + * DMA1_IT_TC5 - DMA1 Channel5 transfer complete flag. + * DMA1_IT_HT5 - DMA1 Channel5 half transfer flag. + * DMA1_IT_TE5 - DMA1 Channel5 transfer error flag. + * DMA1_IT_GL6 - DMA1 Channel6 global flag. + * DMA1_IT_TC6 - DMA1 Channel6 transfer complete flag. + * DMA1_IT_HT6 - DMA1 Channel6 half transfer flag. + * DMA1_IT_TE6 - DMA1 Channel6 transfer error flag. + * DMA1_IT_GL7 - DMA1 Channel7 global flag. + * DMA1_IT_TC7 - DMA1 Channel7 transfer complete flag. + * DMA1_IT_HT7 - DMA1 Channel7 half transfer flag. + * DMA1_IT_TE7 - DMA1 Channel7 transfer error flag. + * DMA2_IT_GL1 - DMA2 Channel1 global flag. + * DMA2_IT_TC1 - DMA2 Channel1 transfer complete flag. + * DMA2_IT_HT1 - DMA2 Channel1 half transfer flag. + * DMA2_IT_TE1 - DMA2 Channel1 transfer error flag. + * DMA2_IT_GL2 - DMA2 Channel2 global flag. + * DMA2_IT_TC2 - DMA2 Channel2 transfer complete flag. + * DMA2_IT_HT2 - DMA2 Channel2 half transfer flag. + * DMA2_IT_TE2 - DMA2 Channel2 transfer error flag. + * DMA2_IT_GL3 - DMA2 Channel3 global flag. + * DMA2_IT_TC3 - DMA2 Channel3 transfer complete flag. + * DMA2_IT_HT3 - DMA2 Channel3 half transfer flag. + * DMA2_IT_TE3 - DMA2 Channel3 transfer error flag. + * DMA2_IT_GL4 - DMA2 Channel4 global flag. + * DMA2_IT_TC4 - DMA2 Channel4 transfer complete flag. + * DMA2_IT_HT4 - DMA2 Channel4 half transfer flag. + * DMA2_IT_TE4 - DMA2 Channel4 transfer error flag. + * DMA2_IT_GL5 - DMA2 Channel5 global flag. + * DMA2_IT_TC5 - DMA2 Channel5 transfer complete flag. + * DMA2_IT_HT5 - DMA2 Channel5 half transfer flag. + * DMA2_IT_TE5 - DMA2 Channel5 transfer error flag. + * + * @return none + */ +void DMA_ClearITPendingBit(uint32_t DMAy_IT) +{ + if((DMAy_IT & FLAG_Mask) != (uint32_t)RESET) + { + DMA2->INTFCR = DMAy_IT; + } + else + { + DMA1->INTFCR = DMAy_IT; + } +} diff --git a/ch32v103_hallarray_controller/src/periph/ch32v10x_dma.h b/ch32v103_hallarray_controller/src/periph/ch32v10x_dma.h new file mode 100644 index 0000000..fc3689b --- /dev/null +++ b/ch32v103_hallarray_controller/src/periph/ch32v10x_dma.h @@ -0,0 +1,218 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_dma.h + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : This file contains all the functions prototypes for the + * DMA firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V10x_DMA_H +#define __CH32V10x_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v10x.h" + +/* DMA Init structure definition */ +typedef struct +{ + uint32_t DMA_PeripheralBaseAddr; /* Specifies the peripheral base address for DMAy Channelx. */ + + uint32_t DMA_MemoryBaseAddr; /* Specifies the memory base address for DMAy Channelx. */ + + uint32_t DMA_DIR; /* Specifies if the peripheral is the source or destination. + This parameter can be a value of @ref DMA_data_transfer_direction */ + + uint32_t DMA_BufferSize; /* Specifies the buffer size, in data unit, of the specified Channel. + The data unit is equal to the configuration set in DMA_PeripheralDataSize + or DMA_MemoryDataSize members depending in the transfer direction. */ + + uint32_t DMA_PeripheralInc; /* Specifies whether the Peripheral address register is incremented or not. + This parameter can be a value of @ref DMA_peripheral_incremented_mode */ + + uint32_t DMA_MemoryInc; /* Specifies whether the memory address register is incremented or not. + This parameter can be a value of @ref DMA_memory_incremented_mode */ + + uint32_t DMA_PeripheralDataSize; /* Specifies the Peripheral data width. + This parameter can be a value of @ref DMA_peripheral_data_size */ + + uint32_t DMA_MemoryDataSize; /* Specifies the Memory data width. + This parameter can be a value of @ref DMA_memory_data_size */ + + uint32_t DMA_Mode; /* Specifies the operation mode of the DMAy Channelx. + This parameter can be a value of @ref DMA_circular_normal_mode. + @note: The circular buffer mode cannot be used if the memory-to-memory + data transfer is configured on the selected Channel */ + + uint32_t DMA_Priority; /* Specifies the software priority for the DMAy Channelx. + This parameter can be a value of @ref DMA_priority_level */ + + uint32_t DMA_M2M; /* Specifies if the DMAy Channelx will be used in memory-to-memory transfer. + This parameter can be a value of @ref DMA_memory_to_memory */ +} DMA_InitTypeDef; + +/* DMA_data_transfer_direction */ +#define DMA_DIR_PeripheralDST ((uint32_t)0x00000010) +#define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) + +/* DMA_peripheral_incremented_mode */ +#define DMA_PeripheralInc_Enable ((uint32_t)0x00000040) +#define DMA_PeripheralInc_Disable ((uint32_t)0x00000000) + +/* DMA_memory_incremented_mode */ +#define DMA_MemoryInc_Enable ((uint32_t)0x00000080) +#define DMA_MemoryInc_Disable ((uint32_t)0x00000000) + +/* DMA_peripheral_data_size */ +#define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) +#define DMA_PeripheralDataSize_HalfWord ((uint32_t)0x00000100) +#define DMA_PeripheralDataSize_Word ((uint32_t)0x00000200) + +/* DMA_memory_data_size */ +#define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) +#define DMA_MemoryDataSize_HalfWord ((uint32_t)0x00000400) +#define DMA_MemoryDataSize_Word ((uint32_t)0x00000800) + +/* DMA_circular_normal_mode */ +#define DMA_Mode_Circular ((uint32_t)0x00000020) +#define DMA_Mode_Normal ((uint32_t)0x00000000) + +/* DMA_priority_level */ +#define DMA_Priority_VeryHigh ((uint32_t)0x00003000) +#define DMA_Priority_High ((uint32_t)0x00002000) +#define DMA_Priority_Medium ((uint32_t)0x00001000) +#define DMA_Priority_Low ((uint32_t)0x00000000) + +/* DMA_memory_to_memory */ +#define DMA_M2M_Enable ((uint32_t)0x00004000) +#define DMA_M2M_Disable ((uint32_t)0x00000000) + +/* DMA_interrupts_definition */ +#define DMA_IT_TC ((uint32_t)0x00000002) +#define DMA_IT_HT ((uint32_t)0x00000004) +#define DMA_IT_TE ((uint32_t)0x00000008) + +#define DMA1_IT_GL1 ((uint32_t)0x00000001) +#define DMA1_IT_TC1 ((uint32_t)0x00000002) +#define DMA1_IT_HT1 ((uint32_t)0x00000004) +#define DMA1_IT_TE1 ((uint32_t)0x00000008) +#define DMA1_IT_GL2 ((uint32_t)0x00000010) +#define DMA1_IT_TC2 ((uint32_t)0x00000020) +#define DMA1_IT_HT2 ((uint32_t)0x00000040) +#define DMA1_IT_TE2 ((uint32_t)0x00000080) +#define DMA1_IT_GL3 ((uint32_t)0x00000100) +#define DMA1_IT_TC3 ((uint32_t)0x00000200) +#define DMA1_IT_HT3 ((uint32_t)0x00000400) +#define DMA1_IT_TE3 ((uint32_t)0x00000800) +#define DMA1_IT_GL4 ((uint32_t)0x00001000) +#define DMA1_IT_TC4 ((uint32_t)0x00002000) +#define DMA1_IT_HT4 ((uint32_t)0x00004000) +#define DMA1_IT_TE4 ((uint32_t)0x00008000) +#define DMA1_IT_GL5 ((uint32_t)0x00010000) +#define DMA1_IT_TC5 ((uint32_t)0x00020000) +#define DMA1_IT_HT5 ((uint32_t)0x00040000) +#define DMA1_IT_TE5 ((uint32_t)0x00080000) +#define DMA1_IT_GL6 ((uint32_t)0x00100000) +#define DMA1_IT_TC6 ((uint32_t)0x00200000) +#define DMA1_IT_HT6 ((uint32_t)0x00400000) +#define DMA1_IT_TE6 ((uint32_t)0x00800000) +#define DMA1_IT_GL7 ((uint32_t)0x01000000) +#define DMA1_IT_TC7 ((uint32_t)0x02000000) +#define DMA1_IT_HT7 ((uint32_t)0x04000000) +#define DMA1_IT_TE7 ((uint32_t)0x08000000) + +#define DMA2_IT_GL1 ((uint32_t)0x10000001) +#define DMA2_IT_TC1 ((uint32_t)0x10000002) +#define DMA2_IT_HT1 ((uint32_t)0x10000004) +#define DMA2_IT_TE1 ((uint32_t)0x10000008) +#define DMA2_IT_GL2 ((uint32_t)0x10000010) +#define DMA2_IT_TC2 ((uint32_t)0x10000020) +#define DMA2_IT_HT2 ((uint32_t)0x10000040) +#define DMA2_IT_TE2 ((uint32_t)0x10000080) +#define DMA2_IT_GL3 ((uint32_t)0x10000100) +#define DMA2_IT_TC3 ((uint32_t)0x10000200) +#define DMA2_IT_HT3 ((uint32_t)0x10000400) +#define DMA2_IT_TE3 ((uint32_t)0x10000800) +#define DMA2_IT_GL4 ((uint32_t)0x10001000) +#define DMA2_IT_TC4 ((uint32_t)0x10002000) +#define DMA2_IT_HT4 ((uint32_t)0x10004000) +#define DMA2_IT_TE4 ((uint32_t)0x10008000) +#define DMA2_IT_GL5 ((uint32_t)0x10010000) +#define DMA2_IT_TC5 ((uint32_t)0x10020000) +#define DMA2_IT_HT5 ((uint32_t)0x10040000) +#define DMA2_IT_TE5 ((uint32_t)0x10080000) + +/* DMA_flags_definition */ +#define DMA1_FLAG_GL1 ((uint32_t)0x00000001) +#define DMA1_FLAG_TC1 ((uint32_t)0x00000002) +#define DMA1_FLAG_HT1 ((uint32_t)0x00000004) +#define DMA1_FLAG_TE1 ((uint32_t)0x00000008) +#define DMA1_FLAG_GL2 ((uint32_t)0x00000010) +#define DMA1_FLAG_TC2 ((uint32_t)0x00000020) +#define DMA1_FLAG_HT2 ((uint32_t)0x00000040) +#define DMA1_FLAG_TE2 ((uint32_t)0x00000080) +#define DMA1_FLAG_GL3 ((uint32_t)0x00000100) +#define DMA1_FLAG_TC3 ((uint32_t)0x00000200) +#define DMA1_FLAG_HT3 ((uint32_t)0x00000400) +#define DMA1_FLAG_TE3 ((uint32_t)0x00000800) +#define DMA1_FLAG_GL4 ((uint32_t)0x00001000) +#define DMA1_FLAG_TC4 ((uint32_t)0x00002000) +#define DMA1_FLAG_HT4 ((uint32_t)0x00004000) +#define DMA1_FLAG_TE4 ((uint32_t)0x00008000) +#define DMA1_FLAG_GL5 ((uint32_t)0x00010000) +#define DMA1_FLAG_TC5 ((uint32_t)0x00020000) +#define DMA1_FLAG_HT5 ((uint32_t)0x00040000) +#define DMA1_FLAG_TE5 ((uint32_t)0x00080000) +#define DMA1_FLAG_GL6 ((uint32_t)0x00100000) +#define DMA1_FLAG_TC6 ((uint32_t)0x00200000) +#define DMA1_FLAG_HT6 ((uint32_t)0x00400000) +#define DMA1_FLAG_TE6 ((uint32_t)0x00800000) +#define DMA1_FLAG_GL7 ((uint32_t)0x01000000) +#define DMA1_FLAG_TC7 ((uint32_t)0x02000000) +#define DMA1_FLAG_HT7 ((uint32_t)0x04000000) +#define DMA1_FLAG_TE7 ((uint32_t)0x08000000) + +#define DMA2_FLAG_GL1 ((uint32_t)0x10000001) +#define DMA2_FLAG_TC1 ((uint32_t)0x10000002) +#define DMA2_FLAG_HT1 ((uint32_t)0x10000004) +#define DMA2_FLAG_TE1 ((uint32_t)0x10000008) +#define DMA2_FLAG_GL2 ((uint32_t)0x10000010) +#define DMA2_FLAG_TC2 ((uint32_t)0x10000020) +#define DMA2_FLAG_HT2 ((uint32_t)0x10000040) +#define DMA2_FLAG_TE2 ((uint32_t)0x10000080) +#define DMA2_FLAG_GL3 ((uint32_t)0x10000100) +#define DMA2_FLAG_TC3 ((uint32_t)0x10000200) +#define DMA2_FLAG_HT3 ((uint32_t)0x10000400) +#define DMA2_FLAG_TE3 ((uint32_t)0x10000800) +#define DMA2_FLAG_GL4 ((uint32_t)0x10001000) +#define DMA2_FLAG_TC4 ((uint32_t)0x10002000) +#define DMA2_FLAG_HT4 ((uint32_t)0x10004000) +#define DMA2_FLAG_TE4 ((uint32_t)0x10008000) +#define DMA2_FLAG_GL5 ((uint32_t)0x10010000) +#define DMA2_FLAG_TC5 ((uint32_t)0x10020000) +#define DMA2_FLAG_HT5 ((uint32_t)0x10040000) +#define DMA2_FLAG_TE5 ((uint32_t)0x10080000) + +void DMA_DeInit(DMA_Channel_TypeDef *DMAy_Channelx); +void DMA_Init(DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct); +void DMA_StructInit(DMA_InitTypeDef *DMA_InitStruct); +void DMA_Cmd(DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState); +void DMA_ITConfig(DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState); +void DMA_SetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber); +uint16_t DMA_GetCurrDataCounter(DMA_Channel_TypeDef *DMAy_Channelx); +FlagStatus DMA_GetFlagStatus(uint32_t DMAy_FLAG); +void DMA_ClearFlag(uint32_t DMAy_FLAG); +ITStatus DMA_GetITStatus(uint32_t DMAy_IT); +void DMA_ClearITPendingBit(uint32_t DMAy_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32V10x_DMA_H */ diff --git a/ch32v103_hallarray_controller/src/periph/ch32v10x_gpio.c b/ch32v103_hallarray_controller/src/periph/ch32v10x_gpio.c new file mode 100644 index 0000000..a52fb2c --- /dev/null +++ b/ch32v103_hallarray_controller/src/periph/ch32v10x_gpio.c @@ -0,0 +1,578 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_gpio.c + * Author : WCH + * Version : V1.0.1 + * Date : 2025/01/02 + * Description : This file provides all the GPIO firmware functions. + ********************************************************************************* + * Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. + * Attention: This software (modified or not) and binary are used for + * microcontroller manufactured by Nanjing Qinheng Microelectronics. + *******************************************************************************/ +#include "ch32v10x_gpio.h" +#include "ch32v10x_rcc.h" + +/* MASK */ +#define ECR_PORTPINCONFIG_MASK ((uint16_t)0xFF80) +#define LSB_MASK ((uint16_t)0xFFFF) +#define DBGAFR_POSITION_MASK ((uint32_t)0x000F0000) +#define DBGAFR_SWJCFG_MASK ((uint32_t)0xF0FFFFFF) +#define DBGAFR_LOCATION_MASK ((uint32_t)0x00200000) +#define DBGAFR_NUMBITS_MASK ((uint32_t)0x00100000) + +/********************************************************************* + * @fn GPIO_DeInit + * + * @brief Deinitializes the GPIOx peripheral registers to their default + * reset values. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * + * @return none + */ +void GPIO_DeInit(GPIO_TypeDef *GPIOx) +{ + if(GPIOx == GPIOA) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOA, DISABLE); + } + else if(GPIOx == GPIOB) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOB, DISABLE); + } + else if(GPIOx == GPIOC) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOC, DISABLE); + } + else if(GPIOx == GPIOD) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOD, DISABLE); + } + else if(GPIOx == GPIOE) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOE, DISABLE); + } + else if(GPIOx == GPIOF) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOF, DISABLE); + } + else + { + if(GPIOx == GPIOG) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_GPIOG, DISABLE); + } + } +} + +/********************************************************************* + * @fn GPIO_AFIODeInit + * + * @brief Deinitializes the Alternate Functions (remap, event control + * and EXTI configuration) registers to their default reset values. + * + * @return none + */ +void GPIO_AFIODeInit(void) +{ + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_AFIO, DISABLE); +} + +/********************************************************************* + * @fn GPIO_Init + * + * @brief GPIOx - where x can be (A..G) to select the GPIO peripheral. + * + * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure that + * contains the configuration information for the specified GPIO peripheral. + * + * @return none + */ +void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct) +{ + uint32_t currentmode = 0x00, currentpin = 0x00, pinpos = 0x00, pos = 0x00; + uint32_t tmpreg = 0x00, pinmask = 0x00; + + currentmode = ((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x0F); + + if((((uint32_t)GPIO_InitStruct->GPIO_Mode) & ((uint32_t)0x10)) != 0x00) + { + currentmode |= (uint32_t)GPIO_InitStruct->GPIO_Speed; + } + + if(((uint32_t)GPIO_InitStruct->GPIO_Pin & ((uint32_t)0x00FF)) != 0x00) + { + tmpreg = GPIOx->CFGLR; + + for(pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = ((uint32_t)0x01) << pinpos; + currentpin = (GPIO_InitStruct->GPIO_Pin) & pos; + + if(currentpin == pos) + { + pos = pinpos << 2; + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + tmpreg |= (currentmode << pos); + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BCR = (((uint32_t)0x01) << pinpos); + } + else + { + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSHR = (((uint32_t)0x01) << pinpos); + } + } + } + } + GPIOx->CFGLR = tmpreg; + } + + if(GPIO_InitStruct->GPIO_Pin > 0x00FF) + { + tmpreg = GPIOx->CFGHR; + + for(pinpos = 0x00; pinpos < 0x08; pinpos++) + { + pos = (((uint32_t)0x01) << (pinpos + 0x08)); + currentpin = ((GPIO_InitStruct->GPIO_Pin) & pos); + + if(currentpin == pos) + { + pos = pinpos << 2; + pinmask = ((uint32_t)0x0F) << pos; + tmpreg &= ~pinmask; + tmpreg |= (currentmode << pos); + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPD) + { + GPIOx->BCR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + + if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_IPU) + { + GPIOx->BSHR = (((uint32_t)0x01) << (pinpos + 0x08)); + } + } + } + GPIOx->CFGHR = tmpreg; + } +} + +/********************************************************************* + * @fn GPIO_StructInit + * + * @brief Fills each GPIO_InitStruct member with its default + * + * @param GPIO_InitStruct - pointer to a GPIO_InitTypeDef structure + * which will be initialized. + * + * @return none + */ +void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct) +{ + GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All; + GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN_FLOATING; +} + +/********************************************************************* + * @fn GPIO_ReadInputDataBit + * + * @brief GPIOx - where x can be (A..G) to select the GPIO peripheral. + * + * @param GPIO_Pin - specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * + * @return The input port pin value. + */ +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + if((GPIOx->INDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn GPIO_ReadInputData + * + * @brief Reads the specified GPIO input data port. + * + * @param GPIOx: where x can be (A..G) to select the GPIO peripheral. + * + * @return The input port pin value. + */ +uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx) +{ + return ((uint16_t)GPIOx->INDR); +} + +/********************************************************************* + * @fn GPIO_ReadOutputDataBit + * + * @brief Reads the specified output data port bit. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bit to read. + * This parameter can be GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint8_t bitstatus = 0x00; + + if((GPIOx->OUTDR & GPIO_Pin) != (uint32_t)Bit_RESET) + { + bitstatus = (uint8_t)Bit_SET; + } + else + { + bitstatus = (uint8_t)Bit_RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn GPIO_ReadOutputData + * + * @brief Reads the specified GPIO output data port. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * + * @return GPIO output port pin value. + */ +uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx) +{ + return ((uint16_t)GPIOx->OUTDR); +} + +/********************************************************************* + * @fn GPIO_SetBits + * + * @brief Sets the selected data port bits. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIOx->BSHR = GPIO_Pin; +} + +/********************************************************************* + * @fn GPIO_ResetBits + * + * @brief Clears the selected data port bits. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bits to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + GPIOx->BCR = GPIO_Pin; +} + +/********************************************************************* + * @fn GPIO_WriteBit + * + * @brief Sets or clears the selected data port bit. + * + * @param GPIO_Pin - specifies the port bit to be written. + * This parameter can be one of GPIO_Pin_x where x can be (0..15). + * BitVal - specifies the value to be written to the selected bit. + * Bit_RESET - to clear the port pin. + * Bit_SET - to set the port pin. + * + * @return none + */ +void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal) +{ + if(BitVal != Bit_RESET) + { + GPIOx->BSHR = GPIO_Pin; + } + else + { + GPIOx->BCR = GPIO_Pin; + } +} + +/********************************************************************* + * @fn GPIO_Write + * + * @brief Writes data to the specified GPIO data port. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * PortVal - specifies the value to be written to the port output data register. + * + * @return none + */ +void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal) +{ + GPIOx->OUTDR = PortVal; +} + +/********************************************************************* + * @fn GPIO_PinLockConfig + * + * @brief Locks GPIO Pins configuration registers. + * + * @param GPIOx - where x can be (A..G) to select the GPIO peripheral. + * GPIO_Pin - specifies the port bit to be written. + * This parameter can be any combination of GPIO_Pin_x where x can be (0..15). + * + * @return none + */ +void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +{ + uint32_t tmp = 0x00010000; + + tmp |= GPIO_Pin; + GPIOx->LCKR = tmp; + GPIOx->LCKR = GPIO_Pin; + GPIOx->LCKR = tmp; + tmp = GPIOx->LCKR; + tmp = GPIOx->LCKR; +} + +/********************************************************************* + * @fn GPIO_EventOutputConfig + * + * @brief Selects the GPIO pin used as Event output. + * + * @param GPIO_PortSource - selects the GPIO port to be used as source + * for Event output. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..E). + * GPIO_PinSource - specifies the pin for the Event output. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * + * @return none + */ +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmpreg = 0x00; + + tmpreg = AFIO->ECR; + tmpreg &= ECR_PORTPINCONFIG_MASK; + tmpreg |= (uint32_t)GPIO_PortSource << 0x04; + tmpreg |= GPIO_PinSource; + AFIO->ECR = tmpreg; +} + +/********************************************************************* + * @fn GPIO_EventOutputCmd + * + * @brief Enables or disables the Event Output. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void GPIO_EventOutputCmd(FunctionalState NewState) +{ + if(NewState) + { + AFIO->ECR |= (1 << 7); + } + else + { + AFIO->ECR &= ~(1 << 7); + } +} + +/********************************************************************* + * @fn GPIO_PinRemapConfig + * + * @brief Changes the mapping of the specified pin. + * + * @param GPIO_Remap - selects the pin to remap. + * GPIO_Remap_SPI1 - SPI1 Alternate Function mapping + * GPIO_Remap_I2C1 - I2C1 Alternate Function mapping + * GPIO_Remap_USART1 - USART1 Alternate Function mapping + * GPIO_Remap_USART2 - USART2 Alternate Function mapping + * GPIO_PartialRemap_USART3 - USART3 Partial Alternate Function mapping + * GPIO_FullRemap_USART3 - USART3 Full Alternate Function mapping + * GPIO_PartialRemap_TIM1 - TIM1 Partial Alternate Function mapping + * GPIO_FullRemap_TIM1 - TIM1 Full Alternate Function mapping + * GPIO_PartialRemap1_TIM2 - TIM2 Partial1 Alternate Function mapping + * GPIO_PartialRemap2_TIM2 - TIM2 Partial2 Alternate Function mapping + * GPIO_FullRemap_TIM2 - TIM2 Full Alternate Function mapping + * GPIO_PartialRemap_TIM3 - TIM3 Partial Alternate Function mapping + * GPIO_FullRemap_TIM3 - TIM3 Full Alternate Function mapping + * GPIO_Remap_TIM4 - TIM4 Alternate Function mapping + * GPIO_Remap1_CAN1 - CAN1 Alternate Function mapping + * GPIO_Remap2_CAN1 - CAN1 Alternate Function mapping + * GPIO_Remap_PD0PD1 - PD0 and PD1 Alternate Function mapping + * GPIO_Remap_ADC1_ETRGINJ - ADC1 External Trigger Injected Conversion remapping + * GPIO_Remap_ADC1_ETRGREG - ADC1 External Trigger Regular Conversion remapping + * GPIO_Remap_ADC2_ETRGINJ - ADC2 External Trigger Injected Conversion remapping + * GPIO_Remap_ADC2_ETRGREG - ADC2 External Trigger Regular Conversion remapping + * GPIO_Remap_ETH - Ethernet remapping + * GPIO_Remap_CAN2 - CAN2 remapping + * GPIO_Remap_MII_RMII_SEL - MII or RMII selection + * GPIO_Remap_SWJ_Disable - Full SWJ Disabled + * GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame) connected + * to TIM2 Internal Trigger 1 for calibration + * GPIO_Remap_TIM2ITR1_PTP_SOF - Ethernet PTP output or USB OTG SOF (Start of Frame) + * GPIO_Remap_TIM8 - TIM8 Alternate Function mapping + * GPIO_PartialRemap_TIM9 - TIM9 Partial Alternate Function mapping + * GPIO_FullRemap_TIM9 - TIM9 Full Alternate Function mapping + * GPIO_PartialRemap_TIM10 - TIM10 Partial Alternate Function mapping + * GPIO_FullRemap_TIM10 - TIM10 Full Alternate Function mapping + * GPIO_Remap_FSMC_NADV - FSMC_NADV Alternate Function mapping + * GPIO_PartialRemap_USART4 - USART4 Partial Alternate Function mapping + * GPIO_FullRemap_USART4 - USART4 Full Alternate Function mapping + * GPIO_PartialRemap_USART5 - USART5 Partial Alternate Function mapping + * GPIO_FullRemap_USART5 - USART5 Full Alternate Function mapping + * GPIO_PartialRemap_USART6 - USART6 Partial Alternate Function mapping + * GPIO_FullRemap_USART6 - USART6 Full Alternate Function mapping + * GPIO_PartialRemap_USART7 - USART7 Partial Alternate Function mapping + * GPIO_FullRemap_USART7 - USART7 Full Alternate Function mapping + * GPIO_PartialRemap_USART8 - USART8 Partial Alternate Function mapping + * GPIO_FullRemap_USART8 - USART8 Full Alternate Function mapping + * GPIO_Remap_USART1_HighBit - USART1 Alternate Function mapping high bit + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState) +{ + uint32_t tmp = 0x00, tmp1 = 0x00, tmpreg = 0x00, tmpmask = 0x00; + + if((GPIO_Remap & 0x80000000) == 0x80000000) + { + tmpreg = AFIO->PCFR2; + } + else + { + tmpreg = AFIO->PCFR1; + } + + tmpmask = (GPIO_Remap & DBGAFR_POSITION_MASK) >> 0x10; + tmp = GPIO_Remap & LSB_MASK; + + if((GPIO_Remap & (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) == (DBGAFR_LOCATION_MASK | DBGAFR_NUMBITS_MASK)) + { + tmpreg &= DBGAFR_SWJCFG_MASK; + AFIO->PCFR1 &= DBGAFR_SWJCFG_MASK; + } + else if((GPIO_Remap & DBGAFR_NUMBITS_MASK) == DBGAFR_NUMBITS_MASK) + { + tmp1 = ((uint32_t)0x03) << tmpmask; + tmpreg &= ~tmp1; + tmpreg |= ~DBGAFR_SWJCFG_MASK; + } + else + { + tmpreg &= ~(tmp << (((GPIO_Remap & 0x7FFFFFFF)>> 0x15) * 0x10)); + tmpreg |= ~DBGAFR_SWJCFG_MASK; + } + + if(NewState != DISABLE) + { + tmpreg |= (tmp << (((GPIO_Remap & 0x7FFFFFFF)>> 0x15) * 0x10)); + } + + if((GPIO_Remap & 0x80000000) == 0x80000000) + { + AFIO->PCFR2 = tmpreg; + } + else + { + AFIO->PCFR1 = tmpreg; + } +} + +/********************************************************************* + * @fn GPIO_EXTILineConfig + * + * @brief Selects the GPIO pin used as EXTI Line. + * + * @param GPIO_PortSource - selects the GPIO port to be used as source for EXTI lines. + * This parameter can be GPIO_PortSourceGPIOx where x can be (A..G). + * GPIO_PinSource - specifies the EXTI line to be configured. + * This parameter can be GPIO_PinSourcex where x can be (0..15). + * + * @return none + */ +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource) +{ + uint32_t tmp = 0x00; + + tmp = ((uint32_t)0x0F) << (0x04 * (GPIO_PinSource & (uint8_t)0x03)); + AFIO->EXTICR[GPIO_PinSource >> 0x02] &= ~tmp; + AFIO->EXTICR[GPIO_PinSource >> 0x02] |= (((uint32_t)GPIO_PortSource) << (0x04 * (GPIO_PinSource & (uint8_t)0x03))); +} + + +/********************************************************************* + * @fn GPIO_IPD_Unused + * + * @brief Configure unused GPIO as input pull-up. + * + * @param none + * + * @return none + */ +void GPIO_IPD_Unused(void) +{ + GPIO_InitTypeDef GPIO_InitStructure = {0}; + uint32_t chip = 0; + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC | RCC_APB2Periph_GPIOD, ENABLE); + chip = *( uint32_t * )0x1FFFF884 & (~0x000000F0); + switch(chip) + { + case 0x25004102: //CH32V103C8T6 + { + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1\ + |GPIO_Pin_2|GPIO_Pin_3\ + |GPIO_Pin_4|GPIO_Pin_5\ + |GPIO_Pin_6|GPIO_Pin_7\ + |GPIO_Pin_8|GPIO_Pin_9\ + |GPIO_Pin_10|GPIO_Pin_11|GPIO_Pin_12; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOC, &GPIO_InitStructure); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_2; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOD, &GPIO_InitStructure); + break; + } + default: + { + break; + } + } + +} + + + diff --git a/ch32v103_hallarray_controller/src/periph/ch32v10x_gpio.h b/ch32v103_hallarray_controller/src/periph/ch32v10x_gpio.h new file mode 100644 index 0000000..d3ff46e --- /dev/null +++ b/ch32v103_hallarray_controller/src/periph/ch32v10x_gpio.h @@ -0,0 +1,161 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_gpio.h + * Author : WCH + * Version : V1.0.1 + * Date : 2025/01/02 + * Description : This file contains all the functions prototypes for the + * GPIO firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V10x_GPIO_H +#define __CH32V10x_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v10x.h" + +/* Output Maximum frequency selection */ +typedef enum +{ + GPIO_Speed_10MHz = 1, + GPIO_Speed_2MHz, + GPIO_Speed_50MHz +} GPIOSpeed_TypeDef; + +/* Configuration Mode enumeration */ +typedef enum +{ + GPIO_Mode_AIN = 0x0, + GPIO_Mode_IN_FLOATING = 0x04, + GPIO_Mode_IPD = 0x28, + GPIO_Mode_IPU = 0x48, + GPIO_Mode_Out_OD = 0x14, + GPIO_Mode_Out_PP = 0x10, + GPIO_Mode_AF_OD = 0x1C, + GPIO_Mode_AF_PP = 0x18 +} GPIOMode_TypeDef; + +/* GPIO Init structure definition */ +typedef struct +{ + uint16_t GPIO_Pin; /* Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_pins_define */ + + GPIOSpeed_TypeDef GPIO_Speed; /* Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIOSpeed_TypeDef */ + + GPIOMode_TypeDef GPIO_Mode; /* Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIOMode_TypeDef */ +} GPIO_InitTypeDef; + +/* Bit_SET and Bit_RESET enumeration */ +typedef enum +{ + Bit_RESET = 0, + Bit_SET +} BitAction; + +/* GPIO_pins_define */ +#define GPIO_Pin_0 ((uint16_t)0x0001) /* Pin 0 selected */ +#define GPIO_Pin_1 ((uint16_t)0x0002) /* Pin 1 selected */ +#define GPIO_Pin_2 ((uint16_t)0x0004) /* Pin 2 selected */ +#define GPIO_Pin_3 ((uint16_t)0x0008) /* Pin 3 selected */ +#define GPIO_Pin_4 ((uint16_t)0x0010) /* Pin 4 selected */ +#define GPIO_Pin_5 ((uint16_t)0x0020) /* Pin 5 selected */ +#define GPIO_Pin_6 ((uint16_t)0x0040) /* Pin 6 selected */ +#define GPIO_Pin_7 ((uint16_t)0x0080) /* Pin 7 selected */ +#define GPIO_Pin_8 ((uint16_t)0x0100) /* Pin 8 selected */ +#define GPIO_Pin_9 ((uint16_t)0x0200) /* Pin 9 selected */ +#define GPIO_Pin_10 ((uint16_t)0x0400) /* Pin 10 selected */ +#define GPIO_Pin_11 ((uint16_t)0x0800) /* Pin 11 selected */ +#define GPIO_Pin_12 ((uint16_t)0x1000) /* Pin 12 selected */ +#define GPIO_Pin_13 ((uint16_t)0x2000) /* Pin 13 selected */ +#define GPIO_Pin_14 ((uint16_t)0x4000) /* Pin 14 selected */ +#define GPIO_Pin_15 ((uint16_t)0x8000) /* Pin 15 selected */ +#define GPIO_Pin_All ((uint16_t)0xFFFF) /* All pins selected */ + +/* GPIO_Remap_define */ +#define GPIO_Remap_SPI1 ((uint32_t)0x00000001) /* SPI1 Alternate Function mapping */ +#define GPIO_Remap_I2C1 ((uint32_t)0x00000002) /* I2C1 Alternate Function mapping */ +#define GPIO_Remap_USART1 ((uint32_t)0x00000004) /* USART1 Alternate Function mapping */ +#define GPIO_Remap_USART2 ((uint32_t)0x00000008) /* USART2 Alternate Function mapping */ +#define GPIO_PartialRemap_USART3 ((uint32_t)0x00140010) /* USART3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_USART3 ((uint32_t)0x00140030) /* USART3 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM1 ((uint32_t)0x00160040) /* TIM1 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM1 ((uint32_t)0x001600C0) /* TIM1 Full Alternate Function mapping */ +#define GPIO_PartialRemap1_TIM2 ((uint32_t)0x00180100) /* TIM2 Partial1 Alternate Function mapping */ +#define GPIO_PartialRemap2_TIM2 ((uint32_t)0x00180200) /* TIM2 Partial2 Alternate Function mapping */ +#define GPIO_FullRemap_TIM2 ((uint32_t)0x00180300) /* TIM2 Full Alternate Function mapping */ +#define GPIO_PartialRemap_TIM3 ((uint32_t)0x001A0800) /* TIM3 Partial Alternate Function mapping */ +#define GPIO_FullRemap_TIM3 ((uint32_t)0x001A0C00) /* TIM3 Full Alternate Function mapping */ +#define GPIO_Remap_TIM4 ((uint32_t)0x00001000) /* TIM4 Alternate Function mapping */ +#define GPIO_Remap1_CAN1 ((uint32_t)0x001D4000) /* CAN1 Alternate Function mapping */ +#define GPIO_Remap2_CAN1 ((uint32_t)0x001D6000) /* CAN1 Alternate Function mapping */ +#define GPIO_Remap_PD0PD1 ((uint32_t)0x00008000) /* PD0 and PD1 Alternate Function mapping */ +#define GPIO_Remap_ADC1_ETRGINJ ((uint32_t)0x00200002) /* ADC1 External Trigger Injected Conversion remapping */ +#define GPIO_Remap_ADC1_ETRGREG ((uint32_t)0x00200004) /* ADC1 External Trigger Regular Conversion remapping */ +#define GPIO_Remap_SWJ_Disable ((uint32_t)0x00300400) /* Full SWJ Disabled */ +#define GPIO_Remap_TIM2ITR1_PTP_SOF ((uint32_t)0x00202000) /* Ethernet PTP output or USB OTG SOF (Start of Frame) connected \ + to TIM2 Internal Trigger 1 for calibration \ + (only for Connectivity line devices) */ +#define GPIO_Remap_TIM1_DMA ((uint32_t)0x80000010) /* TIM1 DMA requests mapping (only for Value line devices) */ +#define GPIO_Remap_TIM67_DAC_DMA ((uint32_t)0x80000800) /* TIM6/TIM7 and DAC DMA requests remapping (only for High density Value line devices) */ +#define GPIO_Remap_MISC ((uint32_t)0x80002000) /* Miscellaneous Remap (DMA2 Channel5 Position and DAC Trigger remapping, \ + only for High density Value line devices) */ +#define GPIO_Remap_PD01 GPIO_Remap_PD0PD1 + +/* GPIO_Port_Sources */ +#define GPIO_PortSourceGPIOA ((uint8_t)0x00) +#define GPIO_PortSourceGPIOB ((uint8_t)0x01) +#define GPIO_PortSourceGPIOC ((uint8_t)0x02) +#define GPIO_PortSourceGPIOD ((uint8_t)0x03) +#define GPIO_PortSourceGPIOE ((uint8_t)0x04) +#define GPIO_PortSourceGPIOF ((uint8_t)0x05) +#define GPIO_PortSourceGPIOG ((uint8_t)0x06) + +/* GPIO_Pin_sources */ +#define GPIO_PinSource0 ((uint8_t)0x00) +#define GPIO_PinSource1 ((uint8_t)0x01) +#define GPIO_PinSource2 ((uint8_t)0x02) +#define GPIO_PinSource3 ((uint8_t)0x03) +#define GPIO_PinSource4 ((uint8_t)0x04) +#define GPIO_PinSource5 ((uint8_t)0x05) +#define GPIO_PinSource6 ((uint8_t)0x06) +#define GPIO_PinSource7 ((uint8_t)0x07) +#define GPIO_PinSource8 ((uint8_t)0x08) +#define GPIO_PinSource9 ((uint8_t)0x09) +#define GPIO_PinSource10 ((uint8_t)0x0A) +#define GPIO_PinSource11 ((uint8_t)0x0B) +#define GPIO_PinSource12 ((uint8_t)0x0C) +#define GPIO_PinSource13 ((uint8_t)0x0D) +#define GPIO_PinSource14 ((uint8_t)0x0E) +#define GPIO_PinSource15 ((uint8_t)0x0F) + +void GPIO_DeInit(GPIO_TypeDef *GPIOx); +void GPIO_AFIODeInit(void); +void GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_InitStruct); +void GPIO_StructInit(GPIO_InitTypeDef *GPIO_InitStruct); +uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadInputData(GPIO_TypeDef *GPIOx); +uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +uint16_t GPIO_ReadOutputData(GPIO_TypeDef *GPIOx); +void GPIO_SetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void GPIO_ResetBits(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void GPIO_WriteBit(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, BitAction BitVal); +void GPIO_Write(GPIO_TypeDef *GPIOx, uint16_t PortVal); +void GPIO_PinLockConfig(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +void GPIO_EventOutputConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); +void GPIO_EventOutputCmd(FunctionalState NewState); +void GPIO_PinRemapConfig(uint32_t GPIO_Remap, FunctionalState NewState); +void GPIO_EXTILineConfig(uint8_t GPIO_PortSource, uint8_t GPIO_PinSource); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V10x_GPIO_H */ diff --git a/ch32v103_hallarray_controller/src/periph/ch32v10x_misc.c b/ch32v103_hallarray_controller/src/periph/ch32v10x_misc.c new file mode 100644 index 0000000..542193d --- /dev/null +++ b/ch32v103_hallarray_controller/src/periph/ch32v10x_misc.c @@ -0,0 +1,87 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_misc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/05 + * Description : This file provides all the miscellaneous firmware functions . +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v10x_misc.h" + +__IO uint32_t NVIC_Priority_Group = 0; + +/********************************************************************* + * @fn NVIC_PriorityGroupConfig + * + * @brief Configures the priority grouping - pre-emption priority and subpriority. + * + * @param NVIC_PriorityGroup - specifies the priority grouping bits length. + * NVIC_PriorityGroup_0 - 0 bits for pre-emption priority + * 4 bits for subpriority + * NVIC_PriorityGroup_1 - 1 bits for pre-emption priority + * 3 bits for subpriority + * + * @return none + */ +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup) +{ +#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN) + NVIC_INTNestCfg(DISABLE); +#else + NVIC_INTNestCfg(ENABLE); +#endif + + NVIC_Priority_Group = NVIC_PriorityGroup; +} + +/********************************************************************* + * @fn NVIC_Init + * + * @brief Initializes the NVIC peripheral according to the specified parameters in + * the NVIC_InitStruct. + * + * @param NVIC_InitStruct - pointer to a NVIC_InitTypeDef structure that contains the + * configuration information for the specified NVIC peripheral. + * interrupt nesting enable(PFIC->CFGR bit1 = 0) + * NVIC_IRQChannelPreemptionPriority - range from 0 to 1. + * NVIC_IRQChannelSubPriority - range from 0 to 7. + * + * interrupt nesting disable(PFIC->CFGR bit1 = 1) + * NVIC_IRQChannelPreemptionPriority - range is 0. + * NVIC_IRQChannelSubPriority - range from 0 to 0xF. + * + * @return none + */ +void NVIC_Init(NVIC_InitTypeDef *NVIC_InitStruct) +{ +#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN) + if(NVIC_Priority_Group == NVIC_PriorityGroup_0) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4); + } +#else + if(NVIC_Priority_Group == NVIC_PriorityGroup_1) + { + if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 1) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (1 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4)); + } + else if(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority == 0) + { + NVIC_SetPriority(NVIC_InitStruct->NVIC_IRQChannel, (0 << 7) | (NVIC_InitStruct->NVIC_IRQChannelSubPriority << 4)); + } + } +#endif + + if(NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE) + { + NVIC_EnableIRQ(NVIC_InitStruct->NVIC_IRQChannel); + } + else + { + NVIC_DisableIRQ(NVIC_InitStruct->NVIC_IRQChannel); + } +} diff --git a/ch32v103_hallarray_controller/src/periph/ch32v10x_misc.h b/ch32v103_hallarray_controller/src/periph/ch32v10x_misc.h new file mode 100644 index 0000000..5db551c --- /dev/null +++ b/ch32v103_hallarray_controller/src/periph/ch32v10x_misc.h @@ -0,0 +1,70 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_misc.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/05 + * Description : This file contains all the functions prototypes for the + * miscellaneous firmware library functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V10X_MISC_H +#define __CH32V10X_MISC_H + +#ifdef __cplusplus + extern "C" { +#endif + +#include "ch32v10x.h" + +/* CSR_INTSYSCR_INEST_definition */ +#define INTSYSCR_INEST_NoEN 0x00 /* interrupt nesting disable(PFIC->CFGR bit1 = 1) */ +#define INTSYSCR_INEST_EN 0x01 /* interrupt nesting enable(PFIC->CFGR bit1 = 0) */ + +/* Check the configuration of PFIC->CFGR + * interrupt nesting enable(PFIC->CFGR bit1 = 0) + * priority - bit[7] - Preemption Priority + * bit[6:4] - Sub priority + * bit[3:0] - Reserve + * interrupt nesting disable(PFIC->CFGR bit1 = 1) + * priority - bit[7:4] - Sub priority + * bit[3:0] - Reserve + */ + +#ifndef INTSYSCR_INEST +#define INTSYSCR_INEST INTSYSCR_INEST_EN +#endif + +/* NVIC Init Structure definition + * interrupt nesting enable(PFIC->CFGR bit1 = 0) + * NVIC_IRQChannelPreemptionPriority - range from 0 to 1. + * NVIC_IRQChannelSubPriority - range from 0 to 7. + * + * interrupt nesting disable(PFIC->CFGR bit1 = 1) + * NVIC_IRQChannelPreemptionPriority - range is 0. + * NVIC_IRQChannelSubPriority - range from 0 to 0xF. + * + */ +typedef struct +{ + uint8_t NVIC_IRQChannel; + uint8_t NVIC_IRQChannelPreemptionPriority; + uint8_t NVIC_IRQChannelSubPriority; + FunctionalState NVIC_IRQChannelCmd; +} NVIC_InitTypeDef; + +/* Preemption_Priority_Group */ +#if (INTSYSCR_INEST == INTSYSCR_INEST_NoEN) +#define NVIC_PriorityGroup_0 ((uint32_t)0x00) /* interrupt nesting disable(PFIC->CFGR bit1 = 1) */ +#else +#define NVIC_PriorityGroup_1 ((uint32_t)0x01) /* interrupt nesting enable(PFIC->CFGR bit1 = 0) */ +#endif + + +void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup); +void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct); + +#endif /* __CH32V10x_MISC_H */ + diff --git a/ch32v103_hallarray_controller/src/periph/ch32v10x_rcc.c b/ch32v103_hallarray_controller/src/periph/ch32v10x_rcc.c new file mode 100644 index 0000000..66b93ea --- /dev/null +++ b/ch32v103_hallarray_controller/src/periph/ch32v10x_rcc.c @@ -0,0 +1,950 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_rcc.c + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : This file provides all the RCC firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v10x_rcc.h" + +/* RCC registers bit address in the alias region */ +#define RCC_OFFSET (RCC_BASE - PERIPH_BASE) + +/* BDCTLR Register */ +#define BDCTLR_OFFSET (RCC_OFFSET + 0x20) + +/* RCC registers bit mask */ + +/* CTLR register bit mask */ +#define CTLR_HSEBYP_Reset ((uint32_t)0xFFFBFFFF) +#define CTLR_HSEBYP_Set ((uint32_t)0x00040000) +#define CTLR_HSEON_Reset ((uint32_t)0xFFFEFFFF) +#define CTLR_HSEON_Set ((uint32_t)0x00010000) +#define CTLR_HSITRIM_Mask ((uint32_t)0xFFFFFF07) + +#define CFGR0_PLL_Mask ((uint32_t)0xFFC0FFFF) +#define CFGR0_PLLMull_Mask ((uint32_t)0x003C0000) +#define CFGR0_PLLSRC_Mask ((uint32_t)0x00010000) +#define CFGR0_PLLXTPRE_Mask ((uint32_t)0x00020000) +#define CFGR0_SWS_Mask ((uint32_t)0x0000000C) +#define CFGR0_SW_Mask ((uint32_t)0xFFFFFFFC) +#define CFGR0_HPRE_Reset_Mask ((uint32_t)0xFFFFFF0F) +#define CFGR0_HPRE_Set_Mask ((uint32_t)0x000000F0) +#define CFGR0_PPRE1_Reset_Mask ((uint32_t)0xFFFFF8FF) +#define CFGR0_PPRE1_Set_Mask ((uint32_t)0x00000700) +#define CFGR0_PPRE2_Reset_Mask ((uint32_t)0xFFFFC7FF) +#define CFGR0_PPRE2_Set_Mask ((uint32_t)0x00003800) +#define CFGR0_ADCPRE_Reset_Mask ((uint32_t)0xFFFF3FFF) +#define CFGR0_ADCPRE_Set_Mask ((uint32_t)0x0000C000) + +/* RSTSCKR register bit mask */ +#define RSTSCKR_RMVF_Set ((uint32_t)0x01000000) + +/* RCC Flag Mask */ +#define FLAG_Mask ((uint8_t)0x1F) + +/* INTR register byte 2 (Bits[15:8]) base address */ +#define INTR_BYTE2_ADDRESS ((uint32_t)0x40021009) + +/* INTR register byte 3 (Bits[23:16]) base address */ +#define INTR_BYTE3_ADDRESS ((uint32_t)0x4002100A) + +/* CFGR0 register byte 4 (Bits[31:24]) base address */ +#define CFGR0_BYTE4_ADDRESS ((uint32_t)0x40021007) + +/* BDCTLR register base address */ +#define BDCTLR_ADDRESS (PERIPH_BASE + BDCTLR_OFFSET) + +static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; +static __I uint8_t ADCPrescTable[4] = {2, 4, 6, 8}; + +/********************************************************************* + * @fn RCC_DeInit + * + * @brief Resets the RCC clock configuration to the default reset state. + * Note- + * HSE can not be stopped if it is used directly or through the PLL as system clock. + * @return none + */ +void RCC_DeInit(void) +{ + RCC->CTLR |= (uint32_t)0x00000001; + RCC->CFGR0 &= (uint32_t)0xF8FF0000; + RCC->CTLR &= (uint32_t)0xFEF6FFFF; + RCC->CTLR &= (uint32_t)0xFFFBFFFF; + RCC->CFGR0 &= (uint32_t)0xFF80FFFF; + RCC->INTR = 0x009F0000; +} + +/********************************************************************* + * @fn RCC_HSEConfig + * + * @brief Configures the External High Speed oscillator (HSE). + * + * @param RCC_HSE - + * RCC_HSE_OFF - HSE oscillator OFF. + * RCC_HSE_ON - HSE oscillator ON. + * RCC_HSE_Bypass - HSE oscillator bypassed with external clock. + * Note- + * HSE can not be stopped if it is used directly or through the PLL as system clock. + * @return none + */ +void RCC_HSEConfig(uint32_t RCC_HSE) +{ + RCC->CTLR &= CTLR_HSEON_Reset; + RCC->CTLR &= CTLR_HSEBYP_Reset; + + switch(RCC_HSE) + { + case RCC_HSE_ON: + RCC->CTLR |= CTLR_HSEON_Set; + break; + + case RCC_HSE_Bypass: + RCC->CTLR |= CTLR_HSEBYP_Set | CTLR_HSEON_Set; + break; + + default: + break; + } +} + +/********************************************************************* + * @fn RCC_WaitForHSEStartUp + * + * @brief Waits for HSE start-up. + * + * @return READY - HSE oscillator is stable and ready to use. + * NoREADY - HSE oscillator not yet ready. + */ +ErrorStatus RCC_WaitForHSEStartUp(void) +{ + __IO uint32_t StartUpCounter = 0; + + ErrorStatus status = NoREADY; + FlagStatus HSEStatus = RESET; + + do + { + HSEStatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY); + StartUpCounter++; + } while((StartUpCounter != HSE_STARTUP_TIMEOUT) && (HSEStatus == RESET)); + + if(RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET) + { + status = READY; + } + else + { + status = NoREADY; + } + + return (status); +} + +/********************************************************************* + * @fn RCC_AdjustHSICalibrationValue + * + * @brief Adjusts the Internal High Speed oscillator (HSI) calibration value. + * + * @param HSICalibrationValue - specifies the calibration trimming value. + * This parameter must be a number between 0 and 0x1F. + * + * @return none + */ +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CTLR; + tmpreg &= CTLR_HSITRIM_Mask; + tmpreg |= (uint32_t)HSICalibrationValue << 3; + RCC->CTLR = tmpreg; +} + +/********************************************************************* + * @fn RCC_HSICmd + * + * @brief Enables or disables the Internal High Speed oscillator (HSI). + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_HSICmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1 << 0); + } + else + { + RCC->CTLR &= ~(1 << 0); + } +} + +/********************************************************************* + * @fn RCC_PLLConfig + * + * @brief Configures the PLL clock source and multiplication factor. + * + * @param RCC_PLLSource - specifies the PLL entry clock source. + * RCC_PLLSource_HSI_Div2 - HSI oscillator clock divided by 2 + * selected as PLL clock entry. + * RCC_PLLSource_HSE_Div1 - HSE oscillator clock selected as PLL + * clock entry. + * RCC_PLLSource_HSE_Div2 - HSE oscillator clock divided by 2 + * selected as PLL clock entry. + * RCC_PLLMul - specifies the PLL multiplication factor. + * This parameter can be RCC_PLLMul_x where x:[2,16]. + * + * @return none + */ +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_PLL_Mask; + tmpreg |= RCC_PLLSource | RCC_PLLMul; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PLLCmd + * + * @brief Enables or disables the PLL. + * Note-The PLL can not be disabled if it is used as system clock. + * + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_PLLCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1 << 24); + } + else + { + RCC->CTLR &= ~(1 << 24); + } +} + +/********************************************************************* + * @fn RCC_SYSCLKConfig + * + * @brief Configures the system clock (SYSCLK). + * + * @param RCC_SYSCLKSource - specifies the clock source used as system clock. + * RCC_SYSCLKSource_HSI - HSI selected as system clock. + * RCC_SYSCLKSource_HSE - HSE selected as system clock. + * RCC_SYSCLKSource_PLLCLK - PLL selected as system clock. + * + * @return none + */ +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_SW_Mask; + tmpreg |= RCC_SYSCLKSource; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_GetSYSCLKSource + * + * @brief Returns the clock source used as system clock. + * + * @return 0x00 - HSI used as system clock. + * 0x04 - HSE used as system clock. + * 0x08 - PLL used as system clock. + */ +uint8_t RCC_GetSYSCLKSource(void) +{ + return ((uint8_t)(RCC->CFGR0 & CFGR0_SWS_Mask)); +} + +/********************************************************************* + * @fn RCC_HCLKConfig + * + * @brief Configures the AHB clock (HCLK). + * + * @param RCC_SYSCLK - defines the AHB clock divider. This clock is derived from + * the system clock (SYSCLK). + * RCC_SYSCLK_Div1 - AHB clock = SYSCLK. + * RCC_SYSCLK_Div2 - AHB clock = SYSCLK/2. + * RCC_SYSCLK_Div4 - AHB clock = SYSCLK/4. + * RCC_SYSCLK_Div8 - AHB clock = SYSCLK/8. + * RCC_SYSCLK_Div16 - AHB clock = SYSCLK/16. + * RCC_SYSCLK_Div64 - AHB clock = SYSCLK/64. + * RCC_SYSCLK_Div128 - AHB clock = SYSCLK/128. + * RCC_SYSCLK_Div256 - AHB clock = SYSCLK/256. + * RCC_SYSCLK_Div512 - AHB clock = SYSCLK/512. + * + * @return none + */ +void RCC_HCLKConfig(uint32_t RCC_SYSCLK) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_HPRE_Reset_Mask; + tmpreg |= RCC_SYSCLK; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PCLK1Config + * + * @brief Configures the Low Speed APB clock (PCLK1). + * + * @param RCC_HCLK - defines the APB1 clock divider. This clock is derived from + * the AHB clock (HCLK). + * RCC_HCLK_Div1 - APB1 clock = HCLK. + * RCC_HCLK_Div2 - APB1 clock = HCLK/2. + * RCC_HCLK_Div4 - APB1 clock = HCLK/4. + * RCC_HCLK_Div8 - APB1 clock = HCLK/8. + * RCC_HCLK_Div16 - APB1 clock = HCLK/16. + * + * @return none + */ +void RCC_PCLK1Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_PPRE1_Reset_Mask; + tmpreg |= RCC_HCLK; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_PCLK2Config + * + * @brief Configures the High Speed APB clock (PCLK2). + * + * @param RCC_HCLK - defines the APB2 clock divider. This clock is derived from + * the AHB clock (HCLK). + * RCC_HCLK_Div1 - APB2 clock = HCLK. + * RCC_HCLK_Div2 - APB2 clock = HCLK/2. + * RCC_HCLK_Div4 - APB2 clock = HCLK/4. + * RCC_HCLK_Div8 - APB2 clock = HCLK/8. + * RCC_HCLK_Div16 - APB2 clock = HCLK/16. + * @return none + */ +void RCC_PCLK2Config(uint32_t RCC_HCLK) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_PPRE2_Reset_Mask; + tmpreg |= RCC_HCLK << 3; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_ITConfig + * + * @brief Enables or disables the specified RCC interrupts. + * + * @param RCC_IT - specifies the RCC interrupt sources to be enabled or disabled. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_LSERDY - LSE ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + *(__IO uint8_t *)INTR_BYTE2_ADDRESS |= RCC_IT; + } + else + { + *(__IO uint8_t *)INTR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT; + } +} + +/********************************************************************* + * @fn RCC_USBCLKConfig + * + * @brief Configures the USB clock (USBCLK). + * + * @param RCC_USBCLKSource: specifies the USB clock source. This clock is + * derived from the PLL output. + * RCC_USBCLKSource_PLLCLK_1Div5: PLL clock divided by 1,5 selected as USB + * clock source. + * RCC_USBCLKSource_PLLCLK_Div1: PLL clock selected as USB clock source. + * + * @return none + */ +void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource) +{ + if(RCC_USBCLKSource) + { + RCC->CFGR0 |= (1 << 22); + } + else + { + RCC->CFGR0 &= ~(1 << 22); + } +} + +/********************************************************************* + * @fn RCC_ADCCLKConfig + * + * @brief Configures the ADC clock (ADCCLK). + * + * @param RCC_PCLK2 - defines the ADC clock divider. This clock is derived from + * the APB2 clock (PCLK2). + * RCC_PCLK2_Div2 - ADC clock = PCLK2/2. + * RCC_PCLK2_Div4 - ADC clock = PCLK2/4. + * RCC_PCLK2_Div6 - ADC clock = PCLK2/6. + * RCC_PCLK2_Div8 - ADC clock = PCLK2/8. + * + * @return none + */ +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2) +{ + uint32_t tmpreg = 0; + + tmpreg = RCC->CFGR0; + tmpreg &= CFGR0_ADCPRE_Reset_Mask; + tmpreg |= RCC_PCLK2; + RCC->CFGR0 = tmpreg; +} + +/********************************************************************* + * @fn RCC_LSEConfig + * + * @brief Configures the External Low Speed oscillator (LSE). + * + * @param RCC_LSE - specifies the new state of the LSE. + * RCC_LSE_OFF - LSE oscillator OFF. + * RCC_LSE_ON - LSE oscillator ON. + * RCC_LSE_Bypass - LSE oscillator bypassed with external clock. + * + * @return none + */ +void RCC_LSEConfig(uint8_t RCC_LSE) +{ + *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_OFF; + *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_OFF; + + switch(RCC_LSE) + { + case RCC_LSE_ON: + *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_ON; + break; + + case RCC_LSE_Bypass: + *(__IO uint8_t *)BDCTLR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON; + break; + + default: + break; + } +} + +/********************************************************************* + * @fn RCC_LSICmd + * + * @brief Enables or disables the Internal Low Speed oscillator (LSI). + * Note- + * LSI can not be disabled if the IWDG is running. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_LSICmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->RSTSCKR |= (1 << 0); + } + else + { + RCC->RSTSCKR &= ~(1 << 0); + } +} + +/********************************************************************* + * @fn RCC_RTCCLKConfig + * + * @brief Once the RTC clock is selected it can't be changed unless the Backup domain is reset. + * + * @param RCC_RTCCLKSource - specifies the RTC clock source. + * RCC_RTCCLKSource_LSE - LSE selected as RTC clock. + * RCC_RTCCLKSource_LSI - LSI selected as RTC clock. + * RCC_RTCCLKSource_HSE_Div128 - HSE clock divided by 128 selected as RTC clock. + * Note- + * Once the RTC clock is selected it can't be changed unless the Backup domain is reset. + * @return none + */ +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource) +{ + RCC->BDCTLR |= RCC_RTCCLKSource; +} + +/********************************************************************* + * @fn RCC_RTCCLKCmd + * + * @brief This function must be used only after the RTC clock was selected + * using the RCC_RTCCLKConfig function. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_RTCCLKCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->BDCTLR |= (1 << 15); + } + else + { + RCC->BDCTLR &= ~(1 << 15); + } +} + +/********************************************************************* + * @fn RCC_GetClocksFreq + * + * @brief The result of this function could be not correct when using + * fractional value for HSE crystal. + * + * @param RCC_Clocks - pointer to a RCC_ClocksTypeDef structure which will hold + * the clocks frequencies. + * + * @return none + */ +void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0, presc = 0; + + tmp = RCC->CFGR0 & CFGR0_SWS_Mask; + + switch(tmp) + { + case 0x00: + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + + case 0x04: + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE; + break; + + case 0x08: + pllmull = RCC->CFGR0 & CFGR0_PLLMull_Mask; + pllsource = RCC->CFGR0 & CFGR0_PLLSRC_Mask; + pllmull = (pllmull >> 18) + 2; + + if(pllsource == 0x00) + { + if(EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE) + { + RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE)*pllmull; + } + else + { + RCC_Clocks->SYSCLK_Frequency = (HSI_VALUE >> 1) * pllmull; + } + } + else + { + if((RCC->CFGR0 & CFGR0_PLLXTPRE_Mask) != (uint32_t)RESET) + { + RCC_Clocks->SYSCLK_Frequency = (HSE_VALUE >> 1) * pllmull; + } + else + { + RCC_Clocks->SYSCLK_Frequency = HSE_VALUE * pllmull; + } + } + break; + + default: + RCC_Clocks->SYSCLK_Frequency = HSI_VALUE; + break; + } + + tmp = RCC->CFGR0 & CFGR0_HPRE_Set_Mask; + tmp = tmp >> 4; + presc = APBAHBPrescTable[tmp]; + RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc; + tmp = RCC->CFGR0 & CFGR0_PPRE1_Set_Mask; + tmp = tmp >> 8; + presc = APBAHBPrescTable[tmp]; + RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + tmp = RCC->CFGR0 & CFGR0_PPRE2_Set_Mask; + tmp = tmp >> 11; + presc = APBAHBPrescTable[tmp]; + RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc; + tmp = RCC->CFGR0 & CFGR0_ADCPRE_Set_Mask; + tmp = tmp >> 14; + presc = ADCPrescTable[tmp]; + RCC_Clocks->ADCCLK_Frequency = RCC_Clocks->PCLK2_Frequency / presc; +} + +/********************************************************************* + * @fn RCC_AHBPeriphClockCmd + * + * @brief Enables or disables the AHB peripheral clock. + * + * @param RCC_AHBPeriph - specifies the AHB peripheral to gates its clock. + * RCC_AHBPeriph_DMA1. + * RCC_AHBPeriph_DMA2. + * RCC_AHBPeriph_SRAM. + * Note- + * SRAM clock can be disabled only during sleep mode. + * NewState: ENABLE or DISABLE. + * + * @return none + */ +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->AHBPCENR |= RCC_AHBPeriph; + } + else + { + RCC->AHBPCENR &= ~RCC_AHBPeriph; + } +} + +/********************************************************************* + * @fn RCC_APB2PeriphClockCmd + * + * @brief Enables or disables the High Speed APB (APB2) peripheral clock. + * + * @param RCC_APB2Periph - specifies the APB2 peripheral to gates its clock. + * RCC_APB2Periph_AFIO. + * RCC_APB2Periph_GPIOA. + * RCC_APB2Periph_GPIOB. + * RCC_APB2Periph_GPIOC. + * RCC_APB2Periph_GPIOD. + * RCC_APB2Periph_GPIOE + * RCC_APB2Periph_ADC1. + * RCC_APB2Periph_ADC2 + * RCC_APB2Periph_TIM1. + * RCC_APB2Periph_SPI1. + * RCC_APB2Periph_TIM8 + * RCC_APB2Periph_USART1. + * NewState - ENABLE or DISABLE + * + * @return none + */ +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->APB2PCENR |= RCC_APB2Periph; + } + else + { + RCC->APB2PCENR &= ~RCC_APB2Periph; + } +} + +/********************************************************************* + * @fn RCC_APB1PeriphClockCmd + * + * @brief Enables or disables the Low Speed APB (APB1) peripheral clock. + * + * @param RCC_APB1Periph - specifies the APB1 peripheral to gates its clock. + * RCC_APB1Periph_TIM2. + * RCC_APB1Periph_TIM3. + * RCC_APB1Periph_TIM4. + * RCC_APB1Periph_WWDG. + * RCC_APB1Periph_SPI2. + * RCC_APB1Periph_USART2. + * RCC_APB1Periph_I2C1. + * RCC_APB1Periph_I2C2. + * RCC_APB1Periph_USB. + * RCC_APB1Periph_CAN1. + * RCC_APB1Periph_BKP. + * RCC_APB1Periph_PWR. + * RCC_APB1Periph_DAC. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->APB1PCENR |= RCC_APB1Periph; + } + else + { + RCC->APB1PCENR &= ~RCC_APB1Periph; + } +} + +/********************************************************************* + * @fn RCC_APB2PeriphResetCmd + * + * @brief Forces or releases High Speed APB (APB2) peripheral reset. + * + * @param RCC_APB2Periph - specifies the APB2 peripheral to reset. + * RCC_APB2Periph_AFIO. + * RCC_APB2Periph_GPIOA. + * RCC_APB2Periph_GPIOB. + * RCC_APB2Periph_GPIOC. + * RCC_APB2Periph_GPIOD. + * RCC_APB2Periph_GPIOE + * RCC_APB2Periph_ADC1. + * RCC_APB2Periph_TIM1. + * RCC_APB2Periph_SPI1. + * RCC_APB2Periph_USART1. + * NewState - ENABLE or DISABLE + * + * @return none + */ +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->APB2PRSTR |= RCC_APB2Periph; + } + else + { + RCC->APB2PRSTR &= ~RCC_APB2Periph; + } +} + +/********************************************************************* + * @fn RCC_APB1PeriphResetCmd + * + * @brief Forces or releases Low Speed APB (APB1) peripheral reset. + * + * @param RCC_APB1Periph - specifies the APB1 peripheral to reset. + * RCC_APB1Periph_TIM2. + * RCC_APB1Periph_TIM3. + * RCC_APB1Periph_TIM4. + * RCC_APB1Periph_WWDG. + * RCC_APB1Periph_SPI2. + * RCC_APB1Periph_USART2. + * RCC_APB1Periph_USART3. + * RCC_APB1Periph_I2C1. + * RCC_APB1Periph_I2C2. + * RCC_APB1Periph_USB. + * RCC_APB1Periph_CAN1. + * RCC_APB1Periph_BKP. + * RCC_APB1Periph_PWR. + * RCC_APB1Periph_DAC. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + RCC->APB1PRSTR |= RCC_APB1Periph; + } + else + { + RCC->APB1PRSTR &= ~RCC_APB1Periph; + } +} + +/********************************************************************* + * @fn RCC_BackupResetCmd + * + * @brief Forces or releases the Backup domain reset. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_BackupResetCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->BDCTLR |= (1 << 16); + } + else + { + RCC->BDCTLR &= ~(1 << 16); + } +} + +/********************************************************************* + * @fn RCC_ClockSecuritySystemCmd + * + * @brief Enables or disables the Clock Security System. + * + * @param NewState - ENABLE or DISABLE. + * + * @return none + */ +void RCC_ClockSecuritySystemCmd(FunctionalState NewState) +{ + if(NewState) + { + RCC->CTLR |= (1 << 19); + } + else + { + RCC->CTLR &= ~(1 << 19); + } +} + +/********************************************************************* + * @fn RCC_MCOConfig + * + * @brief Selects the clock source to output on MCO pin. + * + * @param RCC_MCO - specifies the clock source to output. + * RCC_MCO_NoClock - No clock selected. + * RCC_MCO_SYSCLK - System clock selected. + * RCC_MCO_HSI - HSI oscillator clock selected. + * RCC_MCO_HSE - HSE oscillator clock selected. + * RCC_MCO_PLLCLK_Div2 - PLL clock divided by 2 selected. + * + * @return none + */ +void RCC_MCOConfig(uint8_t RCC_MCO) +{ + *(__IO uint8_t *)CFGR0_BYTE4_ADDRESS = RCC_MCO; +} + +/********************************************************************* + * @fn RCC_GetFlagStatus + * + * @brief Checks whether the specified RCC flag is set or not. + * + * @param RCC_FLAG - specifies the flag to check. + * RCC_FLAG_HSIRDY - HSI oscillator clock ready. + * RCC_FLAG_HSERDY - HSE oscillator clock ready. + * RCC_FLAG_PLLRDY - PLL clock ready. + * RCC_FLAG_LSERDY - LSE oscillator clock ready. + * RCC_FLAG_LSIRDY - LSI oscillator clock ready. + * RCC_FLAG_PINRST - Pin reset. + * RCC_FLAG_PORRST - POR/PDR reset. + * RCC_FLAG_SFTRST - Software reset. + * RCC_FLAG_IWDGRST - Independent Watchdog reset. + * RCC_FLAG_WWDGRST - Window Watchdog reset. + * RCC_FLAG_LPWRRST - Low Power reset. + * + * @return FlagStatus - SET or RESET. + */ +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG) +{ + uint32_t tmp = 0; + uint32_t statusreg = 0; + + FlagStatus bitstatus = RESET; + tmp = RCC_FLAG >> 5; + + if(tmp == 1) + { + statusreg = RCC->CTLR; + } + else if(tmp == 2) + { + statusreg = RCC->BDCTLR; + } + else + { + statusreg = RCC->RSTSCKR; + } + + tmp = RCC_FLAG & FLAG_Mask; + + if((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn RCC_ClearFlag + * + * @brief Clears the RCC reset flags. + * Note- + * The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST, + * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST + * @return none + */ +void RCC_ClearFlag(void) +{ + RCC->RSTSCKR |= RSTSCKR_RMVF_Set; +} + +/********************************************************************* + * @fn RCC_GetITStatus + * + * @brief Checks whether the specified RCC interrupt has occurred or not. + * + * @param RCC_IT - specifies the RCC interrupt source to check. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_LSERDY - LSE ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * RCC_IT_CSS - Clock Security System interrupt. + * + * @return ITStatus - SET or RESET. + */ +ITStatus RCC_GetITStatus(uint8_t RCC_IT) +{ + ITStatus bitstatus = RESET; + + if((RCC->INTR & RCC_IT) != (uint32_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn RCC_ClearITPendingBit + * + * @brief Clears the RCC's interrupt pending bits. + * + * @param RCC_IT - specifies the interrupt pending bit to clear. + * RCC_IT_LSIRDY - LSI ready interrupt. + * RCC_IT_LSERDY - LSE ready interrupt. + * RCC_IT_HSIRDY - HSI ready interrupt. + * RCC_IT_HSERDY - HSE ready interrupt. + * RCC_IT_PLLRDY - PLL ready interrupt. + * RCC_IT_CSS - Clock Security System interrupt. + * + * @return none + */ +void RCC_ClearITPendingBit(uint8_t RCC_IT) +{ + *(__IO uint8_t *)INTR_BYTE3_ADDRESS = RCC_IT; +} + + + diff --git a/ch32v103_hallarray_controller/src/periph/ch32v10x_rcc.h b/ch32v103_hallarray_controller/src/periph/ch32v10x_rcc.h new file mode 100644 index 0000000..0efbf16 --- /dev/null +++ b/ch32v103_hallarray_controller/src/periph/ch32v10x_rcc.h @@ -0,0 +1,230 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_rcc.h + * Author : WCH + * Version : V1.0.1 + * Date : 2025/01/02 + * Description : This file provides all the RCC firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V10x_RCC_H +#define __CH32V10x_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v10x.h" + +/* RCC_Exported_Types */ +typedef struct +{ + uint32_t SYSCLK_Frequency; /* returns SYSCLK clock frequency expressed in Hz */ + uint32_t HCLK_Frequency; /* returns HCLK clock frequency expressed in Hz */ + uint32_t PCLK1_Frequency; /* returns PCLK1 clock frequency expressed in Hz */ + uint32_t PCLK2_Frequency; /* returns PCLK2 clock frequency expressed in Hz */ + uint32_t ADCCLK_Frequency; /* returns ADCCLK clock frequency expressed in Hz */ +} RCC_ClocksTypeDef; + +/* HSE_configuration */ +#define RCC_HSE_OFF ((uint32_t)0x00000000) +#define RCC_HSE_ON ((uint32_t)0x00010000) +#define RCC_HSE_Bypass ((uint32_t)0x00040000) + +/* PLL_entry_clock_source */ +#define RCC_PLLSource_HSI_Div2 ((uint32_t)0x00000000) +#define RCC_PLLSource_HSE_Div1 ((uint32_t)0x00010000) +#define RCC_PLLSource_HSE_Div2 ((uint32_t)0x00030000) + +/* PLL_multiplication_factor */ +#define RCC_PLLMul_2 ((uint32_t)0x00000000) +#define RCC_PLLMul_3 ((uint32_t)0x00040000) +#define RCC_PLLMul_4 ((uint32_t)0x00080000) +#define RCC_PLLMul_5 ((uint32_t)0x000C0000) +#define RCC_PLLMul_6 ((uint32_t)0x00100000) +#define RCC_PLLMul_7 ((uint32_t)0x00140000) +#define RCC_PLLMul_8 ((uint32_t)0x00180000) +#define RCC_PLLMul_9 ((uint32_t)0x001C0000) +#define RCC_PLLMul_10 ((uint32_t)0x00200000) +#define RCC_PLLMul_11 ((uint32_t)0x00240000) +#define RCC_PLLMul_12 ((uint32_t)0x00280000) +#define RCC_PLLMul_13 ((uint32_t)0x002C0000) +#define RCC_PLLMul_14 ((uint32_t)0x00300000) +#define RCC_PLLMul_15 ((uint32_t)0x00340000) +#define RCC_PLLMul_16 ((uint32_t)0x00380000) + +/* System_clock_source */ +#define RCC_SYSCLKSource_HSI ((uint32_t)0x00000000) +#define RCC_SYSCLKSource_HSE ((uint32_t)0x00000001) +#define RCC_SYSCLKSource_PLLCLK ((uint32_t)0x00000002) + +/* AHB_clock_source */ +#define RCC_SYSCLK_Div1 ((uint32_t)0x00000000) +#define RCC_SYSCLK_Div2 ((uint32_t)0x00000080) +#define RCC_SYSCLK_Div4 ((uint32_t)0x00000090) +#define RCC_SYSCLK_Div8 ((uint32_t)0x000000A0) +#define RCC_SYSCLK_Div16 ((uint32_t)0x000000B0) +#define RCC_SYSCLK_Div64 ((uint32_t)0x000000C0) +#define RCC_SYSCLK_Div128 ((uint32_t)0x000000D0) +#define RCC_SYSCLK_Div256 ((uint32_t)0x000000E0) +#define RCC_SYSCLK_Div512 ((uint32_t)0x000000F0) + +/* APB1_APB2_clock_source */ +#define RCC_HCLK_Div1 ((uint32_t)0x00000000) +#define RCC_HCLK_Div2 ((uint32_t)0x00000400) +#define RCC_HCLK_Div4 ((uint32_t)0x00000500) +#define RCC_HCLK_Div8 ((uint32_t)0x00000600) +#define RCC_HCLK_Div16 ((uint32_t)0x00000700) + +/* RCC_Interrupt_source */ +#define RCC_IT_LSIRDY ((uint8_t)0x01) +#define RCC_IT_LSERDY ((uint8_t)0x02) +#define RCC_IT_HSIRDY ((uint8_t)0x04) +#define RCC_IT_HSERDY ((uint8_t)0x08) +#define RCC_IT_PLLRDY ((uint8_t)0x10) +#define RCC_IT_CSS ((uint8_t)0x80) + +/* USB_Device_clock_source */ +#define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00) +#define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01) + +/* ADC_clock_source */ +#define RCC_PCLK2_Div2 ((uint32_t)0x00000000) +#define RCC_PCLK2_Div4 ((uint32_t)0x00004000) +#define RCC_PCLK2_Div6 ((uint32_t)0x00008000) +#define RCC_PCLK2_Div8 ((uint32_t)0x0000C000) + +/* LSE_configuration */ +#define RCC_LSE_OFF ((uint8_t)0x00) +#define RCC_LSE_ON ((uint8_t)0x01) +#define RCC_LSE_Bypass ((uint8_t)0x04) + +/* RTC_clock_source */ +#define RCC_RTCCLKSource_LSE ((uint32_t)0x00000100) +#define RCC_RTCCLKSource_LSI ((uint32_t)0x00000200) +#define RCC_RTCCLKSource_HSE_Div128 ((uint32_t)0x00000300) + +/* AHB_peripheral */ +#define RCC_AHBPeriph_DMA1 ((uint32_t)0x00000001) +#define RCC_AHBPeriph_DMA2 ((uint32_t)0x00000002) +#define RCC_AHBPeriph_SRAM ((uint32_t)0x00000004) +#define RCC_AHBPeriph_FLITF ((uint32_t)0x00000010) +#define RCC_AHBPeriph_CRC ((uint32_t)0x00000040) +#define RCC_AHBPeriph_FSMC ((uint32_t)0x00000100) +#define RCC_AHBPeriph_SDIO ((uint32_t)0x00000400) +#define RCC_AHBPeriph_USBFS ((uint32_t)0x00001000) +#define RCC_AHBPeriph_USBHD RCC_AHBPeriph_USBFS + +/* APB2_peripheral */ +#define RCC_APB2Periph_AFIO ((uint32_t)0x00000001) +#define RCC_APB2Periph_GPIOA ((uint32_t)0x00000004) +#define RCC_APB2Periph_GPIOB ((uint32_t)0x00000008) +#define RCC_APB2Periph_GPIOC ((uint32_t)0x00000010) +#define RCC_APB2Periph_GPIOD ((uint32_t)0x00000020) +#define RCC_APB2Periph_GPIOE ((uint32_t)0x00000040) +#define RCC_APB2Periph_GPIOF ((uint32_t)0x00000080) +#define RCC_APB2Periph_GPIOG ((uint32_t)0x00000100) +#define RCC_APB2Periph_ADC1 ((uint32_t)0x00000200) +#define RCC_APB2Periph_ADC2 ((uint32_t)0x00000400) +#define RCC_APB2Periph_TIM1 ((uint32_t)0x00000800) +#define RCC_APB2Periph_SPI1 ((uint32_t)0x00001000) +#define RCC_APB2Periph_TIM8 ((uint32_t)0x00002000) +#define RCC_APB2Periph_USART1 ((uint32_t)0x00004000) +#define RCC_APB2Periph_ADC3 ((uint32_t)0x00008000) +#define RCC_APB2Periph_TIM15 ((uint32_t)0x00010000) +#define RCC_APB2Periph_TIM16 ((uint32_t)0x00020000) +#define RCC_APB2Periph_TIM17 ((uint32_t)0x00040000) +#define RCC_APB2Periph_TIM9 ((uint32_t)0x00080000) +#define RCC_APB2Periph_TIM10 ((uint32_t)0x00100000) +#define RCC_APB2Periph_TIM11 ((uint32_t)0x00200000) + +/* APB1_peripheral */ +#define RCC_APB1Periph_TIM2 ((uint32_t)0x00000001) +#define RCC_APB1Periph_TIM3 ((uint32_t)0x00000002) +#define RCC_APB1Periph_TIM4 ((uint32_t)0x00000004) +#define RCC_APB1Periph_TIM5 ((uint32_t)0x00000008) +#define RCC_APB1Periph_TIM6 ((uint32_t)0x00000010) +#define RCC_APB1Periph_TIM7 ((uint32_t)0x00000020) +#define RCC_APB1Periph_TIM12 ((uint32_t)0x00000040) +#define RCC_APB1Periph_TIM13 ((uint32_t)0x00000080) +#define RCC_APB1Periph_TIM14 ((uint32_t)0x00000100) +#define RCC_APB1Periph_WWDG ((uint32_t)0x00000800) +#define RCC_APB1Periph_SPI2 ((uint32_t)0x00004000) +#define RCC_APB1Periph_USART2 ((uint32_t)0x00020000) +#define RCC_APB1Periph_USART3 ((uint32_t)0x00040000) +#define RCC_APB1Periph_UART4 ((uint32_t)0x00080000) +#define RCC_APB1Periph_UART5 ((uint32_t)0x00100000) +#define RCC_APB1Periph_I2C1 ((uint32_t)0x00200000) +#define RCC_APB1Periph_I2C2 ((uint32_t)0x00400000) +#define RCC_APB1Periph_USB ((uint32_t)0x00800000) +#define RCC_APB1Periph_CAN1 ((uint32_t)0x02000000) +#define RCC_APB1Periph_CAN2 ((uint32_t)0x04000000) +#define RCC_APB1Periph_BKP ((uint32_t)0x08000000) +#define RCC_APB1Periph_PWR ((uint32_t)0x10000000) +#define RCC_APB1Periph_DAC ((uint32_t)0x20000000) +#define RCC_APB1Periph_CEC ((uint32_t)0x40000000) + +/* Clock_source_to_output_on_MCO_pin */ +#define RCC_MCO_NoClock ((uint8_t)0x00) +#define RCC_MCO_SYSCLK ((uint8_t)0x04) +#define RCC_MCO_HSI ((uint8_t)0x05) +#define RCC_MCO_HSE ((uint8_t)0x06) +#define RCC_MCO_PLLCLK_Div2 ((uint8_t)0x07) + +/* RCC_Flag */ +#define RCC_FLAG_HSIRDY ((uint8_t)0x21) +#define RCC_FLAG_HSERDY ((uint8_t)0x31) +#define RCC_FLAG_PLLRDY ((uint8_t)0x39) +#define RCC_FLAG_LSERDY ((uint8_t)0x41) +#define RCC_FLAG_LSIRDY ((uint8_t)0x61) +#define RCC_FLAG_PINRST ((uint8_t)0x7A) +#define RCC_FLAG_PORRST ((uint8_t)0x7B) +#define RCC_FLAG_SFTRST ((uint8_t)0x7C) +#define RCC_FLAG_IWDGRST ((uint8_t)0x7D) +#define RCC_FLAG_WWDGRST ((uint8_t)0x7E) +#define RCC_FLAG_LPWRRST ((uint8_t)0x7F) + +/* SysTick_clock_source */ +#define SysTick_CLKSource_HCLK_Div8 ((uint32_t)0xFFFFFFFB) +#define SysTick_CLKSource_HCLK ((uint32_t)0x00000004) + +void RCC_DeInit(void); +void RCC_HSEConfig(uint32_t RCC_HSE); +ErrorStatus RCC_WaitForHSEStartUp(void); +void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue); +void RCC_HSICmd(FunctionalState NewState); +void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul); +void RCC_PLLCmd(FunctionalState NewState); +void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource); +uint8_t RCC_GetSYSCLKSource(void); +void RCC_HCLKConfig(uint32_t RCC_SYSCLK); +void RCC_PCLK1Config(uint32_t RCC_HCLK); +void RCC_PCLK2Config(uint32_t RCC_HCLK); +void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState); +void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource); +void RCC_ADCCLKConfig(uint32_t RCC_PCLK2); +void RCC_LSEConfig(uint8_t RCC_LSE); +void RCC_LSICmd(FunctionalState NewState); +void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource); +void RCC_RTCCLKCmd(FunctionalState NewState); +void RCC_GetClocksFreq(RCC_ClocksTypeDef *RCC_Clocks); +void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState); +void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState); +void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState); +void RCC_BackupResetCmd(FunctionalState NewState); +void RCC_ClockSecuritySystemCmd(FunctionalState NewState); +void RCC_MCOConfig(uint8_t RCC_MCO); +FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG); +void RCC_ClearFlag(void); +ITStatus RCC_GetITStatus(uint8_t RCC_IT); +void RCC_ClearITPendingBit(uint8_t RCC_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V10x_RCC_H */ diff --git a/ch32v103_hallarray_controller/src/periph/ch32v10x_tim.c b/ch32v103_hallarray_controller/src/periph/ch32v10x_tim.c new file mode 100644 index 0000000..7a772b6 --- /dev/null +++ b/ch32v103_hallarray_controller/src/periph/ch32v10x_tim.c @@ -0,0 +1,2355 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_tim.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/06 + * Description : This file provides all the TIM firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v10x_tim.h" +#include "ch32v10x_rcc.h" + +/* TIM registers bit mask */ +#define SMCFGR_ETR_Mask ((uint16_t)0x00FF) +#define CHCTLR_Offset ((uint16_t)0x0018) +#define CCER_CCE_Set ((uint16_t)0x0001) +#define CCER_CCNE_Set ((uint16_t)0x0004) + +static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); +static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter); + +/********************************************************************* + * @fn TIM_DeInit + * + * @brief Deinitializes the TIMx peripheral registers to their default + * reset values. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * + * @return none + */ +void TIM_DeInit(TIM_TypeDef *TIMx) +{ + if(TIMx == TIM1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE); + } + else if(TIMx == TIM2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE); + } + else if(TIMx == TIM3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE); + } + else if(TIMx == TIM4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE); + } +} + +/********************************************************************* + * @fn TIM_TimeBaseInit + * + * @brief Initializes the TIMx Time Base Unit peripheral according to + * the specified parameters in the TIM_TimeBaseInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef + * structure. + * + * @return none + */ +void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) +{ + uint16_t tmpcr1 = 0; + + tmpcr1 = TIMx->CTLR1; + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4)) + { + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode; + } + + tmpcr1 &= (uint16_t)(~((uint16_t)TIM_CTLR1_CKD)); + tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision; + + TIMx->CTLR1 = tmpcr1; + TIMx->ATRLR = TIM_TimeBaseInitStruct->TIM_Period; + TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler; + + if(TIMx == TIM1) + { + TIMx->RPTCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter; + } + + TIMx->SWEVGR = TIM_PSCReloadMode_Immediate; +} + +/********************************************************************* + * @fn TIM_OC1Init + * + * @brief Initializes the TIMx Channel1 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~(uint16_t)TIM_CC1E); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR1; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC1M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC1S)); + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1P)); + tmpccer |= TIM_OCInitStruct->TIM_OCPolarity; + tmpccer |= TIM_OCInitStruct->TIM_OutputState; + + if(TIMx == TIM1) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NP)); + tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity; + + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC1NE)); + tmpccer |= TIM_OCInitStruct->TIM_OutputNState; + + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS1N)); + + tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState; + tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState; + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR1 = tmpccmrx; + TIMx->CH1CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2Init + * + * @brief Initializes the TIMx Channel2 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC2E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR1; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC2M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC2S)); + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4); + + if(TIMx == TIM1) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NP)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC2NE)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4); + + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS2N)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR1 = tmpccmrx; + TIMx->CH2CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3Init + * + * @brief Initializes the TIMx Channel3 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC3E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR2; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC3M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC3S)); + tmpccmrx |= TIM_OCInitStruct->TIM_OCMode; + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8); + + if(TIMx == TIM1) + { + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NP)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC3NE)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3)); + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS3N)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR2 = tmpccmrx; + TIMx->CH3CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC4Init + * + * @brief Initializes the TIMx Channel4 according to the specified + * parameters in the TIM_OCInitStruct. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0; + + TIMx->CCER &= (uint16_t)(~((uint16_t)TIM_CC4E)); + tmpccer = TIMx->CCER; + tmpcr2 = TIMx->CTLR2; + tmpccmrx = TIMx->CHCTLR2; + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_OC4M)); + tmpccmrx &= (uint16_t)(~((uint16_t)TIM_CC4S)); + tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8); + tmpccer &= (uint16_t)(~((uint16_t)TIM_CC4P)); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12); + tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12); + + if(TIMx == TIM1) + { + tmpcr2 &= (uint16_t)(~((uint16_t)TIM_OIS4)); + tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6); + } + + TIMx->CTLR2 = tmpcr2; + TIMx->CHCTLR2 = tmpccmrx; + TIMx->CH4CVR = TIM_OCInitStruct->TIM_Pulse; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_ICInit + * + * @brief IInitializes the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct. + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_2) + { + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_3) + { + TI3_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, + TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/********************************************************************* + * @fn TIM_PWMIConfig + * + * @brief Configures the TIM peripheral according to the specified + * parameters in the TIM_ICInitStruct to measure an external + * PWM signal. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + uint16_t icoppositepolarity = TIM_ICPolarity_Rising; + uint16_t icoppositeselection = TIM_ICSelection_DirectTI; + + if(TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising) + { + icoppositepolarity = TIM_ICPolarity_Falling; + } + else + { + icoppositepolarity = TIM_ICPolarity_Rising; + } + + if(TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI) + { + icoppositeselection = TIM_ICSelection_IndirectTI; + } + else + { + icoppositeselection = TIM_ICSelection_DirectTI; + } + + if(TIM_ICInitStruct->TIM_Channel == TIM_Channel_1) + { + TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } + else + { + TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection, + TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter); + TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler); + } +} + +/********************************************************************* + * @fn TIM_BDTRConfig + * + * @brief Configures the: Break feature, dead time, Lock level, the OSSI, + * the OSSR State and the AOE(automatic output enable). + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. + * + * @return none + */ +void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState | + TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime | + TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity | + TIM_BDTRInitStruct->TIM_AutomaticOutput; +} + +/********************************************************************* + * @fn TIM_TimeBaseStructInit + * + * @brief Fills each TIM_TimeBaseInitStruct member with its default value. + * + * @param TIM_TimeBaseInitStruct - pointer to a TIM_TimeBaseInitTypeDef structure. + * + * @return none + */ +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct) +{ + TIM_TimeBaseInitStruct->TIM_Period = 0xFFFF; + TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000; + TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000; +} + +/********************************************************************* + * @fn TIM_OCStructInit + * + * @brief Fills each TIM_OCInitStruct member with its default value. + * + * @param TIM_OCInitStruct - pointer to a TIM_OCInitTypeDef structure. + * + * @return none + */ +void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct) +{ + TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing; + TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable; + TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable; + TIM_OCInitStruct->TIM_Pulse = 0x0000; + TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High; + TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset; + TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset; +} + +/********************************************************************* + * @fn TIM_ICStructInit + * + * @brief Fills each TIM_ICInitStruct member with its default value. + * + * @param TIM_ICInitStruct - pointer to a TIM_ICInitTypeDef structure. + * + * @return none + */ +void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct) +{ + TIM_ICInitStruct->TIM_Channel = TIM_Channel_1; + TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising; + TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI; + TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1; + TIM_ICInitStruct->TIM_ICFilter = 0x00; +} + +/********************************************************************* + * @fn TIM_BDTRStructInit + * + * @brief Fills each TIM_BDTRInitStruct member with its default value. + * + * @param TIM_BDTRInitStruct - pointer to a TIM_BDTRInitTypeDef structure. + * + * @return none + */ +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct) +{ + TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable; + TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable; + TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF; + TIM_BDTRInitStruct->TIM_DeadTime = 0x00; + TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable; + TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low; + TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable; +} + +/********************************************************************* + * @fn TIM_Cmd + * + * @brief Enables or disables the specified TIM peripheral. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_CEN; + } + else + { + TIMx->CTLR1 &= (uint16_t)(~((uint16_t)TIM_CEN)); + } +} + +/********************************************************************* + * @fn TIM_CtrlPWMOutputs + * + * @brief Enables or disables the TIM peripheral Main Outputs. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->BDTR |= TIM_MOE; + } + else + { + TIMx->BDTR &= (uint16_t)(~((uint16_t)TIM_MOE)); + } +} + +/********************************************************************* + * @fn TIM_ITConfig + * + * @brief Enables or disables the specified TIM interrupts. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_IT - specifies the TIM interrupts sources to be enabled or disabled. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->DMAINTENR |= TIM_IT; + } + else + { + TIMx->DMAINTENR &= (uint16_t)~TIM_IT; + } +} + +/********************************************************************* + * @fn TIM_GenerateEvent + * + * @brief Configures the TIMx event to be generate by software. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_IT - specifies the TIM interrupts sources to be enabled or disabled. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource) +{ + TIMx->SWEVGR = TIM_EventSource; +} + +/********************************************************************* + * @fn TIM_DMAConfig + * + * @brief Configures the TIMx's DMA interface. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_DMABase: DMA Base address. + * TIM_DMABase_CR. + * TIM_DMABase_CR2. + * TIM_DMABase_SMCR. + * TIM_DMABase_DIER. + * TIM1_DMABase_SR. + * TIM_DMABase_EGR. + * TIM_DMABase_CCMR1. + * TIM_DMABase_CCMR2. + * TIM_DMABase_CCER. + * TIM_DMABase_CNT. + * TIM_DMABase_PSC. + * TIM_DMABase_CCR1. + * TIM_DMABase_CCR2. + * TIM_DMABase_CCR3. + * TIM_DMABase_CCR4. + * TIM_DMABase_BDTR. + * TIM_DMABase_DCR. + * TIM_DMABurstLength - DMA Burst length. + * TIM_DMABurstLength_1Transfer. + * TIM_DMABurstLength_18Transfers. + * + * @return none + */ +void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength) +{ + TIMx->DMACFGR = TIM_DMABase | TIM_DMABurstLength; +} + +/********************************************************************* + * @fn TIM_DMACmd + * + * @brief Enables or disables the TIMx's DMA Requests. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_DMASource - specifies the DMA Request sources. + * TIM_DMA_Update - TIM update Interrupt source. + * TIM_DMA_CC1 - TIM Capture Compare 1 DMA source. + * TIM_DMA_CC2 - TIM Capture Compare 2 DMA source. + * TIM_DMA_CC3 - TIM Capture Compare 3 DMA source. + * TIM_DMA_CC4 - TIM Capture Compare 4 DMA source. + * TIM_DMA_COM - TIM Commutation DMA source. + * TIM_DMA_Trigger - TIM Trigger DMA source. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->DMAINTENR |= TIM_DMASource; + } + else + { + TIMx->DMAINTENR &= (uint16_t)~TIM_DMASource; + } +} + +/********************************************************************* + * @fn TIM_InternalClockConfig + * + * @brief Configures the TIMx internal Clock. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * + * @return none + */ +void TIM_InternalClockConfig(TIM_TypeDef *TIMx) +{ + TIMx->SMCFGR &= (uint16_t)(~((uint16_t)TIM_SMS)); +} + +/********************************************************************* + * @fn TIM_ITRxExternalClockConfig + * + * @brief Configures the TIMx Internal Trigger as External Clock. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_InputTriggerSource: Trigger source. + * TIM_TS_ITR0 - Internal Trigger 0. + * TIM_TS_ITR1 - Internal Trigger 1. + * TIM_TS_ITR2 - Internal Trigger 2. + * TIM_TS_ITR3 - Internal Trigger 3. + * + * @return none + */ +void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) +{ + TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource); + TIMx->SMCFGR |= TIM_SlaveMode_External1; +} + +/********************************************************************* + * @fn TIM_TIxExternalClockConfig + * + * @brief Configures the TIMx Trigger as External Clock. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_TIxExternalCLKSource - Trigger source. + * TIM_TIxExternalCLK1Source_TI1ED - TI1 Edge Detector. + * TIM_TIxExternalCLK1Source_TI1 - Filtered Timer Input 1. + * TIM_TIxExternalCLK1Source_TI2 - Filtered Timer Input 2. + * TIM_ICPolarity - specifies the TIx Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_DMA_COM - TIM Commutation DMA source. + * TIM_DMA_Trigger - TIM Trigger DMA source. + * ICFilter - specifies the filter value. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter) +{ + if(TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2) + { + TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + else + { + TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter); + } + + TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource); + TIMx->SMCFGR |= TIM_SlaveMode_External1; +} + +/********************************************************************* + * @fn TIM_ETRClockMode1Config + * + * @brief Configures the External clock Mode1. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); + tmpsmcr |= TIM_SlaveMode_External1; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); + tmpsmcr |= TIM_TS_ETRF; + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_ETRClockMode2Config + * + * @brief Configures the External clock Mode2. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter) +{ + TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter); + TIMx->SMCFGR |= TIM_ECE; +} + +/********************************************************************* + * @fn TIM_ETRConfig + * + * @brief Configures the TIMx External Trigger (ETR). + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ExtTRGPrescaler - The external Trigger Prescaler. + * TIM_ExtTRGPSC_OFF - ETRP Prescaler OFF. + * TIM_ExtTRGPSC_DIV2 - ETRP frequency divided by 2. + * TIM_ExtTRGPSC_DIV4 - ETRP frequency divided by 4. + * TIM_ExtTRGPSC_DIV8 - ETRP frequency divided by 8. + * TIM_ExtTRGPolarity - The external Trigger Polarity. + * TIM_ExtTRGPolarity_Inverted - active low or falling edge active. + * TIM_ExtTRGPolarity_NonInverted - active high or rising edge active. + * ExtTRGFilter - External Trigger Filter. + * This parameter must be a value between 0x0 and 0xF. + * + * @return none + */ +void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter) +{ + uint16_t tmpsmcr = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= SMCFGR_ETR_Mask; + tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8))); + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_PrescalerConfig + * + * @brief Configures the TIMx Prescaler. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * Prescaler - specifies the Prescaler Register value. + * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. + * TIM_PSCReloadMode - specifies the TIM Prescaler Reload mode. + * TIM_PSCReloadMode_Update - The Prescaler is loaded at the update event. + * TIM_PSCReloadMode_Immediate - The Prescaler is loaded immediately. + * + * @return none + */ +void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode) +{ + TIMx->PSC = Prescaler; + TIMx->SWEVGR = TIM_PSCReloadMode; +} + +/********************************************************************* + * @fn TIM_CounterModeConfig + * + * @brief Specifies the TIMx Counter Mode to be used. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_CounterMode - specifies the Counter Mode to be used. + * TIM_CounterMode_Up - TIM Up Counting Mode. + * TIM_CounterMode_Down - TIM Down Counting Mode. + * TIM_CounterMode_CenterAligned1 - TIM Center Aligned Mode1. + * TIM_CounterMode_CenterAligned2 - TIM Center Aligned Mode2. + * TIM_CounterMode_CenterAligned3 - TIM Center Aligned Mode3. + * + * @return none + */ +void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode) +{ + uint16_t tmpcr1 = 0; + + tmpcr1 = TIMx->CTLR1; + tmpcr1 &= (uint16_t)(~((uint16_t)(TIM_DIR | TIM_CMS))); + tmpcr1 |= TIM_CounterMode; + TIMx->CTLR1 = tmpcr1; +} + +/********************************************************************* + * @fn TIM_SelectInputTrigger + * + * @brief Selects the Input Trigger source. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_InputTriggerSource - The Input Trigger source. + * TIM_TS_ITR0 - Internal Trigger 0. + * TIM_TS_ITR1 - Internal Trigger 1. + * TIM_TS_ITR2 - Internal Trigger 2. + * TIM_TS_ITR3 - Internal Trigger 3. + * TIM_TS_TI1F_ED - TI1 Edge Detector. + * TIM_TS_TI1FP1 - Filtered Timer Input 1. + * TIM_TS_TI2FP2 - Filtered Timer Input 2. + * TIM_TS_ETRF - External Trigger input. + * + * @return none + */ +void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource) +{ + uint16_t tmpsmcr = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_TS)); + tmpsmcr |= TIM_InputTriggerSource; + TIMx->SMCFGR = tmpsmcr; +} + +/********************************************************************* + * @fn TIM_EncoderInterfaceConfig + * + * @brief Configures the TIMx Encoder Interface. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_EncoderMode - specifies the TIMx Encoder Mode. + * TIM_EncoderMode_TI1 - Counter counts on TI1FP1 edge depending + * on TI2FP2 level. + * TIM_EncoderMode_TI2 - Counter counts on TI2FP2 edge depending + * on TI1FP1 level. + * TIM_EncoderMode_TI12 - Counter counts on both TI1FP1 and + * TI2FP2 edges depending. + * TIM_IC1Polarity - specifies the IC1 Polarity. + * TIM_ICPolarity_Falling - IC Falling edge. + * TTIM_ICPolarity_Rising - IC Rising edge. + * TIM_IC2Polarity - specifies the IC2 Polarity. + * TIM_ICPolarity_Falling - IC Falling edge. + * TIM_ICPolarity_Rising - IC Rising edge. + * + * @return none + */ +void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity) +{ + uint16_t tmpsmcr = 0; + uint16_t tmpccmr1 = 0; + uint16_t tmpccer = 0; + + tmpsmcr = TIMx->SMCFGR; + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmpsmcr &= (uint16_t)(~((uint16_t)TIM_SMS)); + tmpsmcr |= TIM_EncoderMode; + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & (uint16_t)(~((uint16_t)TIM_CC2S))); + tmpccmr1 |= TIM_CC1S_0 | TIM_CC2S_0; + tmpccer &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1P)) & ((uint16_t) ~((uint16_t)TIM_CC2P))); + tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4)); + TIMx->SMCFGR = tmpsmcr; + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_ForcedOC1Config + * + * @brief Forces the TIMx output 1 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC1REF. + * TIM_ForcedAction_InActive - Force inactive level on OC1REF. + * + * @return none + */ +void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1M); + tmpccmr1 |= TIM_ForcedAction; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ForcedOC2Config + * + * @brief Forces the TIMx output 2 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC2REF. + * TIM_ForcedAction_InActive - Force inactive level on OC2REF. + * + * @return none + */ +void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2M); + tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ForcedOC3Config + * + * @brief Forces the TIMx output 3 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC3REF. + * TIM_ForcedAction_InActive - Force inactive level on OC3REF. + * + * @return none + */ +void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3M); + tmpccmr2 |= TIM_ForcedAction; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ForcedOC4Config + * + * @brief Forces the TIMx output 4 waveform to active or inactive level. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_ForcedAction - specifies the forced Action to be set to the + * output waveform. + * TIM_ForcedAction_Active - Force active level on OC4REF. + * TIM_ForcedAction_InActive - Force inactive level on OC4REF. + * + * @return none + */ +void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4M); + tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ARRPreloadConfig + * + * @brief Enables or disables TIMx peripheral Preload register on ARR. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_ARPE; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_ARPE); + } +} + +/********************************************************************* + * @fn TIM_SelectCOM + * + * @brief Selects the TIM peripheral Commutation event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCUS; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCUS); + } +} + +/********************************************************************* + * @fn TIM_SelectCCDMA + * + * @brief Selects the TIMx peripheral Capture Compare DMA source. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCDS; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCDS); + } +} + +/********************************************************************* + * @fn TIM_CCPreloadControl + * + * @brief DSets or Resets the TIM peripheral Capture Compare Preload Control bit. + * reset values (Affects also the I2Ss). + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_CCPC; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_CCPC); + } +} + +/********************************************************************* + * @fn TIM_OC1PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR1. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1PE); + tmpccmr1 |= TIM_OCPreload; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC2PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR2. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2PE); + tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC3PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR3. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3PE); + tmpccmr2 |= TIM_OCPreload; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC4PreloadConfig + * + * @brief Enables or disables the TIMx peripheral Preload register on CCR4. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPreload - new state of the TIMx peripheral Preload register. + * TIM_OCPreload_Enable. + * TIM_OCPreload_Disable. + * + * @return none + */ +void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4PE); + tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC1FastConfig + * + * @brief Configures the TIMx Output Compare 1 Fast feature. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1FE); + tmpccmr1 |= TIM_OCFast; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC2FastConfig + * + * @brief Configures the TIMx Output Compare 2 Fast feature. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2FE); + tmpccmr1 |= (uint16_t)(TIM_OCFast << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_OC3FastConfig + * + * @brief Configures the TIMx Output Compare 3 Fast feature. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3FE); + tmpccmr2 |= TIM_OCFast; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC4FastConfig + * + * @brief Configures the TIMx Output Compare 4 Fast feature. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCFast - new state of the Output Compare Fast Enable Bit. + * TIM_OCFast_Enable - TIM output compare fast enable. + * TIM_OCFast_Disable - TIM output compare fast disable. + * + * @return none + */ +void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4FE); + tmpccmr2 |= (uint16_t)(TIM_OCFast << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ClearOC1Ref + * + * @brief Clears or safeguards the OCREF1 signal on an external event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC1CE); + tmpccmr1 |= TIM_OCClear; + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ClearOC2Ref + * + * @brief Clears or safeguards the OCREF2 signal on an external event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr1 = 0; + + tmpccmr1 = TIMx->CHCTLR1; + tmpccmr1 &= (uint16_t) ~((uint16_t)TIM_OC2CE); + tmpccmr1 |= (uint16_t)(TIM_OCClear << 8); + TIMx->CHCTLR1 = tmpccmr1; +} + +/********************************************************************* + * @fn TIM_ClearOC3Ref + * + * @brief Clears or safeguards the OCREF3 signal on an external event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC3CE); + tmpccmr2 |= TIM_OCClear; + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_ClearOC4Ref + * + * @brief Clears or safeguards the OCREF4 signal on an external event. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCClear - new state of the Output Compare Clear Enable Bit. + * TIM_OCClear_Enable - TIM Output clear enable. + * TIM_OCClear_Disable - TIM Output clear disable. + * + * @return none + */ +void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear) +{ + uint16_t tmpccmr2 = 0; + + tmpccmr2 = TIMx->CHCTLR2; + tmpccmr2 &= (uint16_t) ~((uint16_t)TIM_OC4CE); + tmpccmr2 |= (uint16_t)(TIM_OCClear << 8); + TIMx->CHCTLR2 = tmpccmr2; +} + +/********************************************************************* + * @fn TIM_OC1PolarityConfig + * + * @brief Configures the TIMx channel 1 polarity. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPolarity - specifies the OC1 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1P); + tmpccer |= TIM_OCPolarity; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC1NPolarityConfig + * + * @brief Configures the TIMx channel 1 polarity. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC1N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC1NP); + tmpccer |= TIM_OCNPolarity; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2PolarityConfig + * + * @brief Configures the TIMx channel 2 polarity. + * + * @param TIMx - where x can be 1 to 4 to select the TIM peripheral. + * TIM_OCPolarity - specifies the OC2 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 4); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC2NPolarityConfig + * + * @brief Configures the TIMx channel 2 polarity. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC1N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC2NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 4); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3PolarityConfig + * + * @brief Configures the TIMx Channel 3 polarity. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_OCPolarit - specifies the OC3 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 8); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC3NPolarityConfig + * + * @brief Configures the TIMx Channel 3N polarity. + * + * @param TIMx - where x can be 1 to select the TIM peripheral. + * TIM_OCNPolarity - specifies the OC2N Polarity. + * TIM_OCNPolarity_High - Output Compare active high. + * TIM_OCNPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC3NP); + tmpccer |= (uint16_t)(TIM_OCNPolarity << 8); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_OC4PolarityConfig + * + * @brief Configures the TIMx Channel 4 polarity. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_OCPolarit - specifies the OC3 Polarity. + * TIM_OCPolarity_High - Output Compare active high. + * TIM_OCPolarity_Low - Output Compare active low. + * + * @return none + */ +void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity) +{ + uint16_t tmpccer = 0; + + tmpccer = TIMx->CCER; + tmpccer &= (uint16_t) ~((uint16_t)TIM_CC4P); + tmpccer |= (uint16_t)(TIM_OCPolarity << 12); + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TIM_CCxCmd + * + * @brief Enables or disables the TIM Capture Compare Channel x. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_Channel_4 - TIM Channel 4. + * TIM_CCx - specifies the TIM Channel CCxE bit new state. + * TIM_CCx_Enable. + * TIM_CCx_Disable. + * + * @return none + */ +void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx) +{ + uint16_t tmp = 0; + + tmp = CCER_CCE_Set << TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp; + TIMx->CCER |= (uint16_t)(TIM_CCx << TIM_Channel); +} + +/********************************************************************* + * @fn TIM_CCxNCmd + * + * @brief Enables or disables the TIM Capture Compare Channel xN. + * + * @param TIMx - where x can be 1 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_CCxN - specifies the TIM Channel CCxNE bit new state. + * TIM_CCxN_Enable. + * TIM_CCxN_Disable. + * + * @return none + */ +void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN) +{ + uint16_t tmp = 0; + + tmp = CCER_CCNE_Set << TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp; + TIMx->CCER |= (uint16_t)(TIM_CCxN << TIM_Channel); +} + +/********************************************************************* + * @fn TIM_SelectOCxM + * + * @brief Selects the TIM Output Compare Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_Channel - specifies the TIM Channel. + * TIM_Channel_1 - TIM Channel 1. + * TIM_Channel_2 - TIM Channel 2. + * TIM_Channel_3 - TIM Channel 3. + * TIM_Channel_4 - TIM Channel 4. + * TIM_OCMode - specifies the TIM Output Compare Mode. + * TIM_OCMode_Timing. + * TIM_OCMode_Active. + * TIM_OCMode_Toggle. + * TIM_OCMode_PWM1. + * TIM_OCMode_PWM2. + * TIM_ForcedAction_Active. + * TIM_ForcedAction_InActive. + * + * @return none + */ +void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode) +{ + uint32_t tmp = 0; + uint16_t tmp1 = 0; + + tmp = (uint32_t)TIMx; + tmp += CHCTLR_Offset; + tmp1 = CCER_CCE_Set << (uint16_t)TIM_Channel; + TIMx->CCER &= (uint16_t)~tmp1; + + if((TIM_Channel == TIM_Channel_1) || (TIM_Channel == TIM_Channel_3)) + { + tmp += (TIM_Channel >> 1); + *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC1M); + *(__IO uint32_t *)tmp |= TIM_OCMode; + } + else + { + tmp += (uint16_t)(TIM_Channel - (uint16_t)4) >> (uint16_t)1; + *(__IO uint32_t *)tmp &= (uint32_t) ~((uint32_t)TIM_OC2M); + *(__IO uint32_t *)tmp |= (uint16_t)(TIM_OCMode << 8); + } +} + +/********************************************************************* + * @fn TIM_UpdateDisableConfig + * + * @brief Enables or Disables the TIMx Update event. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR1 |= TIM_UDIS; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_UDIS); + } +} + +/********************************************************************* + * @fn TIM_UpdateRequestConfig + * + * @brief Configures the TIMx Update Request Interrupt source. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_UpdateSource - specifies the Update source. + * TIM_UpdateSource_Regular. + * TIM_UpdateSource_Global. + * + * @return none + */ +void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource) +{ + if(TIM_UpdateSource != TIM_UpdateSource_Global) + { + TIMx->CTLR1 |= TIM_URS; + } + else + { + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_URS); + } +} + +/********************************************************************* + * @fn TIM_SelectHallSensor + * + * @brief Enables or disables the TIMx's Hall sensor interface. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + TIMx->CTLR2 |= TIM_TI1S; + } + else + { + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_TI1S); + } +} + +/********************************************************************* + * @fn TIM_SelectOnePulseMode + * + * @brief Selects the TIMx's One Pulse Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_OPMode - specifies the OPM Mode to be used. + * TIM_OPMode_Single. + * TIM_OPMode_Repetitive. + * + * @return none + */ +void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode) +{ + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_OPM); + TIMx->CTLR1 |= TIM_OPMode; +} + +/********************************************************************* + * @fn TIM_SelectOutputTrigger + * + * @brief Selects the TIMx Trigger Output Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_TRGOSource - specifies the Trigger Output source. + * TIM_TRGOSource_Reset - The UG bit in the TIM_EGR register is + * used as the trigger output (TRGO). + * TIM_TRGOSource_Enable - The Counter Enable CEN is used as the + * trigger output (TRGO). + * TIM_TRGOSource_Update - The update event is selected as the + * trigger output (TRGO). + * TIM_TRGOSource_OC1 - The trigger output sends a positive pulse + * when the CC1IF flag is to be set, as soon as a capture or compare match occurs (TRGO). + * TIM_TRGOSource_OC1Ref - OC1REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC2Ref - OC2REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC3Ref - OC3REF signal is used as the trigger output (TRGO). + * TIM_TRGOSource_OC4Ref - OC4REF signal is used as the trigger output (TRGO). + * + * @return none + */ +void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource) +{ + TIMx->CTLR2 &= (uint16_t) ~((uint16_t)TIM_MMS); + TIMx->CTLR2 |= TIM_TRGOSource; +} + +/********************************************************************* + * @fn TIM_SelectSlaveMode + * + * @brief Selects the TIMx Slave Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_SlaveMode - specifies the Timer Slave Mode. + * TIM_SlaveMode_Reset - Rising edge of the selected trigger + * signal (TRGI) re-initializes. + * TIM_SlaveMode_Gated - The counter clock is enabled when the + * trigger signal (TRGI) is high. + * TIM_SlaveMode_Trigger - The counter starts at a rising edge + * of the trigger TRGI. + * TIM_SlaveMode_External1 - Rising edges of the selected trigger + * (TRGI) clock the counter. + * + * @return none + */ +void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode) +{ + TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_SMS); + TIMx->SMCFGR |= TIM_SlaveMode; +} + +/********************************************************************* + * @fn TIM_SelectMasterSlaveMode + * + * @brief Sets or Resets the TIMx Master/Slave Mode. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_MasterSlaveMode - specifies the Timer Master Slave Mode. + * TIM_MasterSlaveMode_Enable - synchronization between the current + * timer and its slaves (through TRGO). + * TIM_MasterSlaveMode_Disable - No action. + * + * @return none + */ +void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode) +{ + TIMx->SMCFGR &= (uint16_t) ~((uint16_t)TIM_MSM); + TIMx->SMCFGR |= TIM_MasterSlaveMode; +} + +/********************************************************************* + * @fn TIM_SetCounter + * + * @brief Sets the TIMx Counter Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Counter - specifies the Counter register new value. + * + * @return none + */ +void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter) +{ + TIMx->CNT = Counter; +} + +/********************************************************************* + * @fn TIM_SetAutoreload + * + * @brief Sets the TIMx Autoreload Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Autoreload - specifies the Autoreload register new value. + * + * @return none + */ +void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload) +{ + TIMx->ATRLR = Autoreload; +} + +/********************************************************************* + * @fn TIM_SetCompare1 + * + * @brief Sets the TIMx Capture Compare1 Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1) +{ + TIMx->CH1CVR = Compare1; +} + +/********************************************************************* + * @fn TIM_SetCompare2 + * + * @brief Sets the TIMx Capture Compare2 Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2) +{ + TIMx->CH2CVR = Compare2; +} + +/********************************************************************* + * @fn TIM_SetCompare3 + * + * @brief Sets the TIMx Capture Compare3 Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3) +{ + TIMx->CH3CVR = Compare3; +} + +/********************************************************************* + * @fn TIM_SetCompare4 + * + * @brief Sets the TIMx Capture Compare4 Register value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * Compare1 - specifies the Capture Compare1 register new value. + * + * @return none + */ +void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4) +{ + TIMx->CH4CVR = Compare4; +} + +/********************************************************************* + * @fn TIM_SetIC1Prescaler + * + * @brief Sets the TIMx Input Capture 1 prescaler. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC1PSC); + TIMx->CHCTLR1 |= TIM_ICPSC; +} + +/********************************************************************* + * @fn TIM_SetIC2Prescaler + * + * @brief Sets the TIMx Input Capture 2 prescaler. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR1 &= (uint16_t) ~((uint16_t)TIM_IC2PSC); + TIMx->CHCTLR1 |= (uint16_t)(TIM_ICPSC << 8); +} + +/********************************************************************* + * @fn TIM_SetIC3Prescaler + * + * @brief Sets the TIMx Input Capture 3 prescaler. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC3PSC); + TIMx->CHCTLR2 |= TIM_ICPSC; +} + +/********************************************************************* + * @fn TIM_SetIC4Prescaler + * + * @brief Sets the TIMx Input Capture 4 prescaler. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_ICPSC - specifies the Input Capture1 prescaler new value. + * TIM_ICPSC_DIV1 - no prescaler. + * TIM_ICPSC_DIV2 - capture is done once every 2 events. + * TIM_ICPSC_DIV4 - capture is done once every 4 events. + * TIM_ICPSC_DIV8 - capture is done once every 8 events. + * + * @return none + */ +void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC) +{ + TIMx->CHCTLR2 &= (uint16_t) ~((uint16_t)TIM_IC4PSC); + TIMx->CHCTLR2 |= (uint16_t)(TIM_ICPSC << 8); +} + +/********************************************************************* + * @fn TIM_SetClockDivision + * + * @brief Sets the TIMx Clock Division value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_CKD - specifies the clock division value. + * TIM_CKD_DIV1 - TDTS = Tck_tim. + * TIM_CKD_DIV2 - TDTS = 2*Tck_tim. + * TIM_CKD_DIV4 - TDTS = 4*Tck_tim. + * + * @return none + */ +void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD) +{ + TIMx->CTLR1 &= (uint16_t) ~((uint16_t)TIM_CTLR1_CKD); + TIMx->CTLR1 |= TIM_CKD; +} + +/********************************************************************* + * @fn TIM_GetCapture1 + * + * @brief Gets the TIMx Input Capture 1 value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CH1CVR - Capture Compare 1 Register value. + */ +uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx) +{ + return TIMx->CH1CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture2 + * + * @brief Gets the TIMx Input Capture 2 value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CH2CVR - Capture Compare 2 Register value. + */ +uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx) +{ + return TIMx->CH2CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture2 + * + * @brief Gets the TIMx Input Capture 2 value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CH2CVR - Capture Compare 2 Register value. + */ +uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx) +{ + return TIMx->CH3CVR; +} + +/********************************************************************* + * @fn TIM_GetCapture4 + * + * @brief Gets the TIMx Input Capture 4 value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CH4CVR - Capture Compare 4 Register value. + */ +uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx) +{ + return TIMx->CH4CVR; +} + +/********************************************************************* + * @fn TIM_GetCounter + * + * @brief Gets the TIMx Counter value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->CNT - Counter Register value. + */ +uint16_t TIM_GetCounter(TIM_TypeDef *TIMx) +{ + return TIMx->CNT; +} + +/********************************************************************* + * @fn TIM_GetPrescaler + * + * @brief Gets the TIMx Prescaler value. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * + * @return TIMx->PSC - Prescaler Register value. + */ +uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx) +{ + return TIMx->PSC; +} + +/********************************************************************* + * @fn TIM_GetFlagStatus + * + * @brief Checks whether the specified TIM flag is set or not. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_FLAG - specifies the flag to check. + * TIM_FLAG_Update - TIM update Flag. + * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. + * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. + * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. + * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. + * TIM_FLAG_COM - TIM Commutation Flag. + * TIM_FLAG_Trigger - TIM Trigger Flag. + * TIM_FLAG_Break - TIM Break Flag. + * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. + * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. + * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. + * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. + * + * @return SET or RESET. + */ +FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) +{ + ITStatus bitstatus = RESET; + + if((TIMx->INTFR & TIM_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn TIM_ClearFlag + * + * @brief Clears the TIMx's pending flags. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_FLAG - specifies the flag to check. + * TIM_FLAG_Update - TIM update Flag. + * TIM_FLAG_CC1 - TIM Capture Compare 1 Flag. + * TIM_FLAG_CC2 - TIM Capture Compare 2 Flag. + * TIM_FLAG_CC3 - TIM Capture Compare 3 Flag. + * TIM_FLAG_CC4 - TIM Capture Compare 4 Flag. + * TIM_FLAG_COM - TIM Commutation Flag. + * TIM_FLAG_Trigger - TIM Trigger Flag. + * TIM_FLAG_Break - TIM Break Flag. + * TIM_FLAG_CC1OF - TIM Capture Compare 1 overcapture Flag. + * TIM_FLAG_CC2OF - TIM Capture Compare 2 overcapture Flag. + * TIM_FLAG_CC3OF - TIM Capture Compare 3 overcapture Flag. + * TIM_FLAG_CC4OF - TIM Capture Compare 4 overcapture Flag. + * + * @return none + */ +void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG) +{ + TIMx->INTFR = (uint16_t)~TIM_FLAG; +} + +/********************************************************************* + * @fn TIM_GetITStatus + * + * @brief Checks whether the TIM interrupt has occurred or not. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_IT - specifies the TIM interrupt source to check. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * + * @return none + */ +ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT) +{ + ITStatus bitstatus = RESET; + uint16_t itstatus = 0x0, itenable = 0x0; + + itstatus = TIMx->INTFR & TIM_IT; + + itenable = TIMx->DMAINTENR & TIM_IT; + if((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn TIM_ClearITPendingBit + * + * @brief Clears the TIMx's interrupt pending bits. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * TIM_IT - specifies the TIM interrupt source to check. + * TIM_IT_Update - TIM update Interrupt source. + * TIM_IT_CC1 - TIM Capture Compare 1 Interrupt source. + * TIM_IT_CC2 - TIM Capture Compare 2 Interrupt source. + * TIM_IT_CC3 - TIM Capture Compare 3 Interrupt source. + * TIM_IT_CC4 - TIM Capture Compare 4 Interrupt source. + * TIM_IT_COM - TIM Commutation Interrupt source. + * TIM_IT_Trigger - TIM Trigger Interrupt source. + * TIM_IT_Break - TIM Break Interrupt source. + * + * @return none + */ +void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT) +{ + TIMx->INTFR = (uint16_t)~TIM_IT; +} + +/********************************************************************* + * @fn TI1_Config + * + * @brief Configure the TI1 as Input. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 1 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 1 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 1 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI1_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC1E); + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC1S)) & ((uint16_t) ~((uint16_t)TIM_IC1F))); + + TIMx->CHCTLR1 |= (uint16_t)(TIM_ICSelection); + tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC1P | TIM_CC1NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC1E); + } + + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI2_Config + * + * @brief Configure the TI2 as Input. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 2 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 2 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 2 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI2_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC2E); + tmpccmr1 = TIMx->CHCTLR1; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 4); + tmpccmr1 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC2S)) & ((uint16_t) ~((uint16_t)TIM_IC2F))); + + TIMx->CHCTLR1 |= (uint16_t)(TIM_ICSelection << 8); + tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8) | (uint16_t)(TIM_ICFilter << 12); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC2E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC2P | TIM_CC2NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC2E); + } + + TIMx->CHCTLR1 = tmpccmr1; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI3_Config + * + * @brief Configure the TI3 as Input. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 3 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 3 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 3 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI3_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC3E); + tmpccmr2 = TIMx->CHCTLR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 8); + tmpccmr2 &= (uint16_t)(((uint16_t) ~((uint16_t)TIM_CC3S)) & ((uint16_t) ~((uint16_t)TIM_IC3F))); + + TIMx->CHCTLR2 |= (uint16_t)(TIM_ICSelection); + tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4)); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC3E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P | TIM_CC3NP)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC3E); + } + + TIMx->CHCTLR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} + +/********************************************************************* + * @fn TI4_Config + * + * @brief Configure the TI4 as Input. + * + * @param TIMx - where x can be 1 to 4 select the TIM peripheral. + * IM_ICPolarity - The Input Polarity. + * TIM_ICPolarity_Rising. + * TIM_ICPolarity_Falling. + * TIM_ICSelection - specifies the input to be used. + * TIM_ICSelection_DirectTI - TIM Input 4 is selected to be + * connected to IC1. + * TIM_ICSelection_IndirectTI - TIM Input 4 is selected to be + * connected to IC2. + * TIM_ICSelection_TRC - TIM Input 4 is selected to be connected + * to TRC. + * TIM_ICFilter - Specifies the Input Capture Filter. + * This parameter must be a value between 0x00 and 0x0F. + * + * @return none + */ +static void TI4_Config(TIM_TypeDef *TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection, + uint16_t TIM_ICFilter) +{ + uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0; + + TIMx->CCER &= (uint16_t) ~((uint16_t)TIM_CC4E); + tmpccmr2 = TIMx->CHCTLR2; + tmpccer = TIMx->CCER; + tmp = (uint16_t)(TIM_ICPolarity << 12); + tmpccmr2 &= (uint16_t)((uint16_t)(~(uint16_t)TIM_CC4S) & ((uint16_t) ~((uint16_t)TIM_IC4F))); + + TIMx->CHCTLR2 |= (uint16_t)(TIM_ICSelection << 8); + tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8) | (uint16_t)(TIM_ICFilter << 12); + + if((TIMx == TIM1) || (TIMx == TIM2) || (TIMx == TIM3) || (TIMx == TIM4)) + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC4P)); + tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CC4E); + } + else + { + tmpccer &= (uint16_t) ~((uint16_t)(TIM_CC3P)); + tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CC4E); + } + + TIMx->CHCTLR2 = tmpccmr2; + TIMx->CCER = tmpccer; +} diff --git a/ch32v103_hallarray_controller/src/periph/ch32v10x_tim.h b/ch32v103_hallarray_controller/src/periph/ch32v10x_tim.h new file mode 100644 index 0000000..17d254d --- /dev/null +++ b/ch32v103_hallarray_controller/src/periph/ch32v10x_tim.h @@ -0,0 +1,508 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_tim.h + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : This file contains all the functions prototypes for the + * TIM firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V10x_TIM_H +#define __CH32V10x_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v10x.h" + +/* TIM Time Base Init structure definition */ +typedef struct +{ + uint16_t TIM_Prescaler; /* Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_CounterMode; /* Specifies the counter mode. + This parameter can be a value of @ref TIM_Counter_Mode */ + + uint16_t TIM_Period; /* Specifies the period value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between 0x0000 and 0xFFFF. */ + + uint16_t TIM_ClockDivision; /* Specifies the clock division. + This parameter can be a value of @ref TIM_Clock_Division_CKD */ + + uint8_t TIM_RepetitionCounter; /* Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_TimeBaseInitTypeDef; + +/* TIM Output Compare Init structure definition */ +typedef struct +{ + uint16_t TIM_OCMode; /* Specifies the TIM mode. + This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ + + uint16_t TIM_OutputState; /* Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_state */ + + uint16_t TIM_OutputNState; /* Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_Output_Compare_N_state + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_Pulse; /* Specifies the pulse value to be loaded into the Capture Compare Register. + This parameter can be a number between 0x0000 and 0xFFFF */ + + uint16_t TIM_OCPolarity; /* Specifies the output polarity. + This parameter can be a value of @ref TIM_Output_Compare_Polarity */ + + uint16_t TIM_OCNPolarity; /* Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_Output_Compare_N_Polarity + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCIdleState; /* Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ + + uint16_t TIM_OCNIdleState; /* Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State + @note This parameter is valid only for TIM1 and TIM8. */ +} TIM_OCInitTypeDef; + +/* TIM Input Capture Init structure definition */ +typedef struct +{ + uint16_t TIM_Channel; /* Specifies the TIM channel. + This parameter can be a value of @ref TIM_Channel */ + + uint16_t TIM_ICPolarity; /* Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_Input_Capture_Polarity */ + + uint16_t TIM_ICSelection; /* Specifies the input. + This parameter can be a value of @ref TIM_Input_Capture_Selection */ + + uint16_t TIM_ICPrescaler; /* Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ + + uint16_t TIM_ICFilter; /* Specifies the input capture filter. + This parameter can be a number between 0x0 and 0xF */ +} TIM_ICInitTypeDef; + +/* BDTR structure definition */ +typedef struct +{ + uint16_t TIM_OSSRState; /* Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref OSSR_Off_State_Selection_for_Run_mode_state */ + + uint16_t TIM_OSSIState; /* Specifies the Off-State used in Idle state. + This parameter can be a value of @ref OSSI_Off_State_Selection_for_Idle_mode_state */ + + uint16_t TIM_LOCKLevel; /* Specifies the LOCK level parameters. + This parameter can be a value of @ref Lock_level */ + + uint16_t TIM_DeadTime; /* Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between 0x00 and 0xFF */ + + uint16_t TIM_Break; /* Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref Break_Input_enable_disable */ + + uint16_t TIM_BreakPolarity; /* Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref Break_Polarity */ + + uint16_t TIM_AutomaticOutput; /* Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */ +} TIM_BDTRInitTypeDef; + +/* TIM_Output_Compare_and_PWM_modes */ +#define TIM_OCMode_Timing ((uint16_t)0x0000) +#define TIM_OCMode_Active ((uint16_t)0x0010) +#define TIM_OCMode_Inactive ((uint16_t)0x0020) +#define TIM_OCMode_Toggle ((uint16_t)0x0030) +#define TIM_OCMode_PWM1 ((uint16_t)0x0060) +#define TIM_OCMode_PWM2 ((uint16_t)0x0070) + +/* TIM_One_Pulse_Mode */ +#define TIM_OPMode_Single ((uint16_t)0x0008) +#define TIM_OPMode_Repetitive ((uint16_t)0x0000) + +/* TIM_Channel */ +#define TIM_Channel_1 ((uint16_t)0x0000) +#define TIM_Channel_2 ((uint16_t)0x0004) +#define TIM_Channel_3 ((uint16_t)0x0008) +#define TIM_Channel_4 ((uint16_t)0x000C) + +/* TIM_Clock_Division_CKD */ +#define TIM_CKD_DIV1 ((uint16_t)0x0000) +#define TIM_CKD_DIV2 ((uint16_t)0x0100) +#define TIM_CKD_DIV4 ((uint16_t)0x0200) + +/* TIM_Counter_Mode */ +#define TIM_CounterMode_Up ((uint16_t)0x0000) +#define TIM_CounterMode_Down ((uint16_t)0x0010) +#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020) +#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040) +#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060) + +/* TIM_Output_Compare_Polarity */ +#define TIM_OCPolarity_High ((uint16_t)0x0000) +#define TIM_OCPolarity_Low ((uint16_t)0x0002) + +/* TIM_Output_Compare_N_Polarity */ +#define TIM_OCNPolarity_High ((uint16_t)0x0000) +#define TIM_OCNPolarity_Low ((uint16_t)0x0008) + +/* TIM_Output_Compare_state */ +#define TIM_OutputState_Disable ((uint16_t)0x0000) +#define TIM_OutputState_Enable ((uint16_t)0x0001) + +/* TIM_Output_Compare_N_state */ +#define TIM_OutputNState_Disable ((uint16_t)0x0000) +#define TIM_OutputNState_Enable ((uint16_t)0x0004) + +/* TIM_Capture_Compare_state */ +#define TIM_CCx_Enable ((uint16_t)0x0001) +#define TIM_CCx_Disable ((uint16_t)0x0000) + +/* TIM_Capture_Compare_N_state */ +#define TIM_CCxN_Enable ((uint16_t)0x0004) +#define TIM_CCxN_Disable ((uint16_t)0x0000) + +/* Break_Input_enable_disable */ +#define TIM_Break_Enable ((uint16_t)0x1000) +#define TIM_Break_Disable ((uint16_t)0x0000) + +/* Break_Polarity */ +#define TIM_BreakPolarity_Low ((uint16_t)0x0000) +#define TIM_BreakPolarity_High ((uint16_t)0x2000) + +/* TIM_AOE_Bit_Set_Reset */ +#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000) +#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000) + +/* Lock_level */ +#define TIM_LOCKLevel_OFF ((uint16_t)0x0000) +#define TIM_LOCKLevel_1 ((uint16_t)0x0100) +#define TIM_LOCKLevel_2 ((uint16_t)0x0200) +#define TIM_LOCKLevel_3 ((uint16_t)0x0300) + +/* OSSI_Off_State_Selection_for_Idle_mode_state */ +#define TIM_OSSIState_Enable ((uint16_t)0x0400) +#define TIM_OSSIState_Disable ((uint16_t)0x0000) + +/* OSSR_Off_State_Selection_for_Run_mode_state */ +#define TIM_OSSRState_Enable ((uint16_t)0x0800) +#define TIM_OSSRState_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Idle_State */ +#define TIM_OCIdleState_Set ((uint16_t)0x0100) +#define TIM_OCIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Output_Compare_N_Idle_State */ +#define TIM_OCNIdleState_Set ((uint16_t)0x0200) +#define TIM_OCNIdleState_Reset ((uint16_t)0x0000) + +/* TIM_Input_Capture_Polarity */ +#define TIM_ICPolarity_Rising ((uint16_t)0x0000) +#define TIM_ICPolarity_Falling ((uint16_t)0x0002) +#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A) + +/* TIM_Input_Capture_Selection */ +#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /* TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC1, IC2, IC3 or IC4, respectively */ +#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /* TIM Input 1, 2, 3 or 4 is selected to be \ + connected to IC2, IC1, IC4 or IC3, respectively. */ +#define TIM_ICSelection_TRC ((uint16_t)0x0003) /* TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */ + +/* TIM_Input_Capture_Prescaler */ +#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /* Capture performed each time an edge is detected on the capture input. */ +#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /* Capture performed once every 2 events. */ +#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /* Capture performed once every 4 events. */ +#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /* Capture performed once every 8 events. */ + +/* TIM_interrupt_sources */ +#define TIM_IT_Update ((uint16_t)0x0001) +#define TIM_IT_CC1 ((uint16_t)0x0002) +#define TIM_IT_CC2 ((uint16_t)0x0004) +#define TIM_IT_CC3 ((uint16_t)0x0008) +#define TIM_IT_CC4 ((uint16_t)0x0010) +#define TIM_IT_COM ((uint16_t)0x0020) +#define TIM_IT_Trigger ((uint16_t)0x0040) +#define TIM_IT_Break ((uint16_t)0x0080) + +/* TIM_DMA_Base_address */ +#define TIM_DMABase_CR1 ((uint16_t)0x0000) +#define TIM_DMABase_CR2 ((uint16_t)0x0001) +#define TIM_DMABase_SMCR ((uint16_t)0x0002) +#define TIM_DMABase_DIER ((uint16_t)0x0003) +#define TIM_DMABase_SR ((uint16_t)0x0004) +#define TIM_DMABase_EGR ((uint16_t)0x0005) +#define TIM_DMABase_CCMR1 ((uint16_t)0x0006) +#define TIM_DMABase_CCMR2 ((uint16_t)0x0007) +#define TIM_DMABase_CCER ((uint16_t)0x0008) +#define TIM_DMABase_CNT ((uint16_t)0x0009) +#define TIM_DMABase_PSC ((uint16_t)0x000A) +#define TIM_DMABase_ARR ((uint16_t)0x000B) +#define TIM_DMABase_RCR ((uint16_t)0x000C) +#define TIM_DMABase_CCR1 ((uint16_t)0x000D) +#define TIM_DMABase_CCR2 ((uint16_t)0x000E) +#define TIM_DMABase_CCR3 ((uint16_t)0x000F) +#define TIM_DMABase_CCR4 ((uint16_t)0x0010) +#define TIM_DMABase_BDTR ((uint16_t)0x0011) +#define TIM_DMABase_DCR ((uint16_t)0x0012) + +/* TIM_DMA_Burst_Length */ +#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000) +#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100) +#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200) +#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300) +#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400) +#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500) +#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600) +#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700) +#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800) +#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900) +#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00) +#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00) +#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00) +#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00) +#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00) +#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00) +#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000) +#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100) + +/* TIM_DMA_sources */ +#define TIM_DMA_Update ((uint16_t)0x0100) +#define TIM_DMA_CC1 ((uint16_t)0x0200) +#define TIM_DMA_CC2 ((uint16_t)0x0400) +#define TIM_DMA_CC3 ((uint16_t)0x0800) +#define TIM_DMA_CC4 ((uint16_t)0x1000) +#define TIM_DMA_COM ((uint16_t)0x2000) +#define TIM_DMA_Trigger ((uint16_t)0x4000) + +/* TIM_External_Trigger_Prescaler */ +#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000) +#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000) +#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000) +#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000) + +/* TIM_Internal_Trigger_Selection */ +#define TIM_TS_ITR0 ((uint16_t)0x0000) +#define TIM_TS_ITR1 ((uint16_t)0x0010) +#define TIM_TS_ITR2 ((uint16_t)0x0020) +#define TIM_TS_ITR3 ((uint16_t)0x0030) +#define TIM_TS_TI1F_ED ((uint16_t)0x0040) +#define TIM_TS_TI1FP1 ((uint16_t)0x0050) +#define TIM_TS_TI2FP2 ((uint16_t)0x0060) +#define TIM_TS_ETRF ((uint16_t)0x0070) + +/* TIM_TIx_External_Clock_Source */ +#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050) +#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060) +#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040) + +/* TIM_External_Trigger_Polarity */ +#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000) +#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000) + +/* TIM_Prescaler_Reload_Mode */ +#define TIM_PSCReloadMode_Update ((uint16_t)0x0000) +#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001) + +/* TIM_Forced_Action */ +#define TIM_ForcedAction_Active ((uint16_t)0x0050) +#define TIM_ForcedAction_InActive ((uint16_t)0x0040) + +/* TIM_Encoder_Mode */ +#define TIM_EncoderMode_TI1 ((uint16_t)0x0001) +#define TIM_EncoderMode_TI2 ((uint16_t)0x0002) +#define TIM_EncoderMode_TI12 ((uint16_t)0x0003) + +/* TIM_Event_Source */ +#define TIM_EventSource_Update ((uint16_t)0x0001) +#define TIM_EventSource_CC1 ((uint16_t)0x0002) +#define TIM_EventSource_CC2 ((uint16_t)0x0004) +#define TIM_EventSource_CC3 ((uint16_t)0x0008) +#define TIM_EventSource_CC4 ((uint16_t)0x0010) +#define TIM_EventSource_COM ((uint16_t)0x0020) +#define TIM_EventSource_Trigger ((uint16_t)0x0040) +#define TIM_EventSource_Break ((uint16_t)0x0080) + +/* TIM_Update_Source */ +#define TIM_UpdateSource_Global ((uint16_t)0x0000) /* Source of update is the counter overflow/underflow \ + or the setting of UG bit, or an update generation \ + through the slave mode controller. */ +#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /* Source of update is counter overflow/underflow. */ + +/* TIM_Output_Compare_Preload_State */ +#define TIM_OCPreload_Enable ((uint16_t)0x0008) +#define TIM_OCPreload_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Fast_State */ +#define TIM_OCFast_Enable ((uint16_t)0x0004) +#define TIM_OCFast_Disable ((uint16_t)0x0000) + +/* TIM_Output_Compare_Clear_State */ +#define TIM_OCClear_Enable ((uint16_t)0x0080) +#define TIM_OCClear_Disable ((uint16_t)0x0000) + +/* TIM_Trigger_Output_Source */ +#define TIM_TRGOSource_Reset ((uint16_t)0x0000) +#define TIM_TRGOSource_Enable ((uint16_t)0x0010) +#define TIM_TRGOSource_Update ((uint16_t)0x0020) +#define TIM_TRGOSource_OC1 ((uint16_t)0x0030) +#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040) +#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050) +#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060) +#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070) + +/* TIM_Slave_Mode */ +#define TIM_SlaveMode_Reset ((uint16_t)0x0004) +#define TIM_SlaveMode_Gated ((uint16_t)0x0005) +#define TIM_SlaveMode_Trigger ((uint16_t)0x0006) +#define TIM_SlaveMode_External1 ((uint16_t)0x0007) + +/* TIM_Master_Slave_Mode */ +#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080) +#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000) + +/* TIM_Flags */ +#define TIM_FLAG_Update ((uint16_t)0x0001) +#define TIM_FLAG_CC1 ((uint16_t)0x0002) +#define TIM_FLAG_CC2 ((uint16_t)0x0004) +#define TIM_FLAG_CC3 ((uint16_t)0x0008) +#define TIM_FLAG_CC4 ((uint16_t)0x0010) +#define TIM_FLAG_COM ((uint16_t)0x0020) +#define TIM_FLAG_Trigger ((uint16_t)0x0040) +#define TIM_FLAG_Break ((uint16_t)0x0080) +#define TIM_FLAG_CC1OF ((uint16_t)0x0200) +#define TIM_FLAG_CC2OF ((uint16_t)0x0400) +#define TIM_FLAG_CC3OF ((uint16_t)0x0800) +#define TIM_FLAG_CC4OF ((uint16_t)0x1000) + +/* TIM_Legacy */ +#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer +#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers +#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers +#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers +#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers +#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers +#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers +#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers +#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers +#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers +#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers +#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers +#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers +#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers +#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers +#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers +#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers +#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers + +void TIM_DeInit(TIM_TypeDef *TIMx); +void TIM_TimeBaseInit(TIM_TypeDef *TIMx, TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct); +void TIM_OC1Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_OC2Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_OC3Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_OC4Init(TIM_TypeDef *TIMx, TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_ICInit(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct); +void TIM_PWMIConfig(TIM_TypeDef *TIMx, TIM_ICInitTypeDef *TIM_ICInitStruct); +void TIM_BDTRConfig(TIM_TypeDef *TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef *TIM_TimeBaseInitStruct); +void TIM_OCStructInit(TIM_OCInitTypeDef *TIM_OCInitStruct); +void TIM_ICStructInit(TIM_ICInitTypeDef *TIM_ICInitStruct); +void TIM_BDTRStructInit(TIM_BDTRInitTypeDef *TIM_BDTRInitStruct); +void TIM_Cmd(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_CtrlPWMOutputs(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_ITConfig(TIM_TypeDef *TIMx, uint16_t TIM_IT, FunctionalState NewState); +void TIM_GenerateEvent(TIM_TypeDef *TIMx, uint16_t TIM_EventSource); +void TIM_DMAConfig(TIM_TypeDef *TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength); +void TIM_DMACmd(TIM_TypeDef *TIMx, uint16_t TIM_DMASource, FunctionalState NewState); +void TIM_InternalClockConfig(TIM_TypeDef *TIMx); +void TIM_ITRxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource); +void TIM_TIxExternalClockConfig(TIM_TypeDef *TIMx, uint16_t TIM_TIxExternalCLKSource, + uint16_t TIM_ICPolarity, uint16_t ICFilter); +void TIM_ETRClockMode1Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_ETRClockMode2Config(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, + uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter); +void TIM_ETRConfig(TIM_TypeDef *TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity, + uint16_t ExtTRGFilter); +void TIM_PrescalerConfig(TIM_TypeDef *TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode); +void TIM_CounterModeConfig(TIM_TypeDef *TIMx, uint16_t TIM_CounterMode); +void TIM_SelectInputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_InputTriggerSource); +void TIM_EncoderInterfaceConfig(TIM_TypeDef *TIMx, uint16_t TIM_EncoderMode, + uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity); +void TIM_ForcedOC1Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC2Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC3Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ForcedOC4Config(TIM_TypeDef *TIMx, uint16_t TIM_ForcedAction); +void TIM_ARRPreloadConfig(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_SelectCOM(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_SelectCCDMA(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_CCPreloadControl(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_OC1PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC2PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC3PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC4PreloadConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPreload); +void TIM_OC1FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_OC2FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_OC3FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_OC4FastConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCFast); +void TIM_ClearOC1Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC2Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC3Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_ClearOC4Ref(TIM_TypeDef *TIMx, uint16_t TIM_OCClear); +void TIM_OC1PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_OC1NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC2PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_OC2NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC3PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_OC3NPolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCNPolarity); +void TIM_OC4PolarityConfig(TIM_TypeDef *TIMx, uint16_t TIM_OCPolarity); +void TIM_CCxCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx); +void TIM_CCxNCmd(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN); +void TIM_SelectOCxM(TIM_TypeDef *TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode); +void TIM_UpdateDisableConfig(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_UpdateRequestConfig(TIM_TypeDef *TIMx, uint16_t TIM_UpdateSource); +void TIM_SelectHallSensor(TIM_TypeDef *TIMx, FunctionalState NewState); +void TIM_SelectOnePulseMode(TIM_TypeDef *TIMx, uint16_t TIM_OPMode); +void TIM_SelectOutputTrigger(TIM_TypeDef *TIMx, uint16_t TIM_TRGOSource); +void TIM_SelectSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_SlaveMode); +void TIM_SelectMasterSlaveMode(TIM_TypeDef *TIMx, uint16_t TIM_MasterSlaveMode); +void TIM_SetCounter(TIM_TypeDef *TIMx, uint16_t Counter); +void TIM_SetAutoreload(TIM_TypeDef *TIMx, uint16_t Autoreload); +void TIM_SetCompare1(TIM_TypeDef *TIMx, uint16_t Compare1); +void TIM_SetCompare2(TIM_TypeDef *TIMx, uint16_t Compare2); +void TIM_SetCompare3(TIM_TypeDef *TIMx, uint16_t Compare3); +void TIM_SetCompare4(TIM_TypeDef *TIMx, uint16_t Compare4); +void TIM_SetIC1Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC2Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC3Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetIC4Prescaler(TIM_TypeDef *TIMx, uint16_t TIM_ICPSC); +void TIM_SetClockDivision(TIM_TypeDef *TIMx, uint16_t TIM_CKD); +uint16_t TIM_GetCapture1(TIM_TypeDef *TIMx); +uint16_t TIM_GetCapture2(TIM_TypeDef *TIMx); +uint16_t TIM_GetCapture3(TIM_TypeDef *TIMx); +uint16_t TIM_GetCapture4(TIM_TypeDef *TIMx); +uint16_t TIM_GetCounter(TIM_TypeDef *TIMx); +uint16_t TIM_GetPrescaler(TIM_TypeDef *TIMx); +FlagStatus TIM_GetFlagStatus(TIM_TypeDef *TIMx, uint16_t TIM_FLAG); +void TIM_ClearFlag(TIM_TypeDef *TIMx, uint16_t TIM_FLAG); +ITStatus TIM_GetITStatus(TIM_TypeDef *TIMx, uint16_t TIM_IT); +void TIM_ClearITPendingBit(TIM_TypeDef *TIMx, uint16_t TIM_IT); + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32V10x_TIM_H */ diff --git a/ch32v103_hallarray_controller/src/periph/ch32v10x_usart.c b/ch32v103_hallarray_controller/src/periph/ch32v10x_usart.c new file mode 100644 index 0000000..b9a4f89 --- /dev/null +++ b/ch32v103_hallarray_controller/src/periph/ch32v10x_usart.c @@ -0,0 +1,747 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_usart.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/06 + * Description : This file provides all the USART firmware functions. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v10x_usart.h" +#include "ch32v10x_rcc.h" + +/* USART_Private_Defines */ +#define CTLR1_UE_Set ((uint16_t)0x2000) /* USART Enable Mask */ +#define CTLR1_UE_Reset ((uint16_t)0xDFFF) /* USART Disable Mask */ + +#define CTLR1_WAKE_Mask ((uint16_t)0xF7FF) /* USART WakeUp Method Mask */ + +#define CTLR1_RWU_Set ((uint16_t)0x0002) /* USART mute mode Enable Mask */ +#define CTLR1_RWU_Reset ((uint16_t)0xFFFD) /* USART mute mode Enable Mask */ +#define CTLR1_SBK_Set ((uint16_t)0x0001) /* USART Break Character send Mask */ +#define CTLR1_CLEAR_Mask ((uint16_t)0xE9F3) /* USART CTLR1 Mask */ +#define CTLR2_Address_Mask ((uint16_t)0xFFF0) /* USART address Mask */ + +#define CTLR2_LINEN_Set ((uint16_t)0x4000) /* USART LIN Enable Mask */ +#define CTLR2_LINEN_Reset ((uint16_t)0xBFFF) /* USART LIN Disable Mask */ + +#define CTLR2_LBDL_Mask ((uint16_t)0xFFDF) /* USART LIN Break detection Mask */ +#define CTLR2_STOP_CLEAR_Mask ((uint16_t)0xCFFF) /* USART CTLR2 STOP Bits Mask */ +#define CTLR2_CLOCK_CLEAR_Mask ((uint16_t)0xF0FF) /* USART CTLR2 Clock Mask */ + +#define CTLR3_SCEN_Set ((uint16_t)0x0020) /* USART SC Enable Mask */ +#define CTLR3_SCEN_Reset ((uint16_t)0xFFDF) /* USART SC Disable Mask */ + +#define CTLR3_NACK_Set ((uint16_t)0x0010) /* USART SC NACK Enable Mask */ +#define CTLR3_NACK_Reset ((uint16_t)0xFFEF) /* USART SC NACK Disable Mask */ + +#define CTLR3_HDSEL_Set ((uint16_t)0x0008) /* USART Half-Duplex Enable Mask */ +#define CTLR3_HDSEL_Reset ((uint16_t)0xFFF7) /* USART Half-Duplex Disable Mask */ + +#define CTLR3_IRLP_Mask ((uint16_t)0xFFFB) /* USART IrDA LowPower mode Mask */ +#define CTLR3_CLEAR_Mask ((uint16_t)0xFCFF) /* USART CTLR3 Mask */ + +#define CTLR3_IREN_Set ((uint16_t)0x0002) /* USART IrDA Enable Mask */ +#define CTLR3_IREN_Reset ((uint16_t)0xFFFD) /* USART IrDA Disable Mask */ +#define GPR_LSB_Mask ((uint16_t)0x00FF) /* Guard Time Register LSB Mask */ +#define GPR_MSB_Mask ((uint16_t)0xFF00) /* Guard Time Register MSB Mask */ +#define IT_Mask ((uint16_t)0x001F) /* USART Interrupt Mask */ + +/********************************************************************* + * @fn USART_DeInit + * + * @brief Deinitializes the USARTx peripheral registers to their default + * reset values. + * + * @param USARTx - where x can be 1, 2 or 3 to select the UART peripheral. + * + * @return none + */ +void USART_DeInit(USART_TypeDef *USARTx) +{ + if(USARTx == USART1) + { + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE); + RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE); + } + else if(USARTx == USART2) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE); + } + else if(USARTx == USART3) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE); + } + else if(USARTx == UART4) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE); + } + else + { + if(USARTx == UART5) + { + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE); + RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE); + } + } +} + +/********************************************************************* + * @fn USART_Init + * + * @brief Initializes the USARTx peripheral according to the specified + * parameters in the USART_InitStruct. + * + * @param USARTx - where x can be 1, 2 or 3 to select the UART peripheral. + * USART_InitStruct - pointer to a USART_InitTypeDef structure + * that contains the configuration information for the specified + * USART peripheral. + * + * @return none + */ +void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct) +{ + uint32_t tmpreg = 0x00, apbclock = 0x00; + uint32_t integerdivider = 0x00; + uint32_t fractionaldivider = 0x00; + uint32_t usartxbase = 0; + RCC_ClocksTypeDef RCC_ClocksStatus; + + if(USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None) + { + } + + usartxbase = (uint32_t)USARTx; + tmpreg = USARTx->CTLR2; + tmpreg &= CTLR2_STOP_CLEAR_Mask; + tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits; + + USARTx->CTLR2 = (uint16_t)tmpreg; + tmpreg = USARTx->CTLR1; + tmpreg &= CTLR1_CLEAR_Mask; + tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity | + USART_InitStruct->USART_Mode; + USARTx->CTLR1 = (uint16_t)tmpreg; + + tmpreg = USARTx->CTLR3; + tmpreg &= CTLR3_CLEAR_Mask; + tmpreg |= USART_InitStruct->USART_HardwareFlowControl; + USARTx->CTLR3 = (uint16_t)tmpreg; + + RCC_GetClocksFreq(&RCC_ClocksStatus); + + if(usartxbase == USART1_BASE) + { + apbclock = RCC_ClocksStatus.PCLK2_Frequency; + } + else + { + apbclock = RCC_ClocksStatus.PCLK1_Frequency; + } + + integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate))); + tmpreg = (integerdivider / 100) << 4; + fractionaldivider = integerdivider - (100 * (tmpreg >> 4)); + tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F); + USARTx->BRR = (uint16_t)tmpreg; +} + +/********************************************************************* + * @fn USART_StructInit + * + * @brief Fills each USART_InitStruct member with its default value. + * + * @param USART_InitStruct: pointer to a USART_InitTypeDef structure + * which will be initialized. + * + * @return none + */ +void USART_StructInit(USART_InitTypeDef *USART_InitStruct) +{ + USART_InitStruct->USART_BaudRate = 9600; + USART_InitStruct->USART_WordLength = USART_WordLength_8b; + USART_InitStruct->USART_StopBits = USART_StopBits_1; + USART_InitStruct->USART_Parity = USART_Parity_No; + USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None; +} + +/********************************************************************* + * @fn USART_ClockInit + * + * @brief Initializes the USARTx peripheral Clock according to the + * specified parameters in the USART_ClockInitStruct . + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_ClockInitStruct - pointer to a USART_ClockInitTypeDef + * structure that contains the configuration information for the specified + * USART peripheral. + * + * @return none + */ +void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + uint32_t tmpreg = 0x00; + + tmpreg = USARTx->CTLR2; + tmpreg &= CTLR2_CLOCK_CLEAR_Mask; + tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | + USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit; + USARTx->CTLR2 = (uint16_t)tmpreg; +} + +/********************************************************************* + * @fn USART_ClockStructInit + * + * @brief Fills each USART_ClockStructInit member with its default value. + * + * @param USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef + * structure which will be initialized. + * + * @return none + */ +void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + USART_ClockInitStruct->USART_Clock = USART_Clock_Disable; + USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low; + USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge; + USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable; +} + +/********************************************************************* + * @fn USART_Cmd + * + * @brief Enables or disables the specified USART peripheral. + * reset values (Affects also the I2Ss). + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState: ENABLE or DISABLE. + * + * @return none + */ +void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR1 |= CTLR1_UE_Set; + } + else + { + USARTx->CTLR1 &= CTLR1_UE_Reset; + } +} + +/********************************************************************* + * @fn USART_ITConfig + * + * @brief Enables or disables the specified USART interrupts. + * reset values (Affects also the I2Ss). + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_IT - specifies the USART interrupt sources to be enabled or disabled. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TXE - Transmit Data Register empty interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * USART_IT_IDLE - Idle line detection interrupt. + * USART_IT_PE - Parity Error interrupt. + * USART_IT_ERR - Error interrupt. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState) +{ + uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00; + uint32_t usartxbase = 0x00; + + usartxbase = (uint32_t)USARTx; + usartreg = (((uint8_t)USART_IT) >> 0x05); + itpos = USART_IT & IT_Mask; + itmask = (((uint32_t)0x01) << itpos); + + if(usartreg == 0x01) + { + usartxbase += 0x0C; + } + else if(usartreg == 0x02) + { + usartxbase += 0x10; + } + else + { + usartxbase += 0x14; + } + + if(NewState != DISABLE) + { + *(__IO uint32_t *)usartxbase |= itmask; + } + else + { + *(__IO uint32_t *)usartxbase &= ~itmask; + } +} + +/********************************************************************* + * @fn USART_DMACmd + * + * @brief Enables or disables the USART DMA interface. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_DMAReq - specifies the DMA request. + * USART_DMAReq_Tx - USART DMA transmit request. + * USART_DMAReq_Rx - USART DMA receive request. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= USART_DMAReq; + } + else + { + USARTx->CTLR3 &= (uint16_t)~USART_DMAReq; + } +} + +/********************************************************************* + * @fn USART_SetAddress + * + * @brief Sets the address of the USART node. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_Address - Indicates the address of the USART node. + * + * @return none + */ +void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address) +{ + USARTx->CTLR2 &= CTLR2_Address_Mask; + USARTx->CTLR2 |= USART_Address; +} + +/********************************************************************* + * @fn USART_WakeUpConfig + * + * @brief Selects the USART WakeUp method. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_WakeUp - specifies the USART wakeup method. + * USART_WakeUp_IdleLine - WakeUp by an idle line detection. + * USART_WakeUp_AddressMark - WakeUp by an address mark. + * + * @return none + */ +void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp) +{ + USARTx->CTLR1 &= CTLR1_WAKE_Mask; + USARTx->CTLR1 |= USART_WakeUp; +} + +/********************************************************************* + * @fn USART_ReceiverWakeUpCmd + * + * @brief Determines if the USART is in mute mode or not. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR1 |= CTLR1_RWU_Set; + } + else + { + USARTx->CTLR1 &= CTLR1_RWU_Reset; + } +} + +/********************************************************************* + * @fn USART_LINBreakDetectLengthConfig + * + * @brief Sets the USART LIN Break detection length. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_LINBreakDetectLength - specifies the LIN break detection length. + * USART_LINBreakDetectLength_10b - 10-bit break detection. + * USART_LINBreakDetectLength_11b - 11-bit break detection. + * + * @return none + */ +void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength) +{ + USARTx->CTLR2 &= CTLR2_LBDL_Mask; + USARTx->CTLR2 |= USART_LINBreakDetectLength; +} + +/********************************************************************* + * @fn USART_LINCmd + * + * @brief Enables or disables the USART LIN mode. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR2 |= CTLR2_LINEN_Set; + } + else + { + USARTx->CTLR2 &= CTLR2_LINEN_Reset; + } +} + +/********************************************************************* + * @fn USART_SendData + * + * @brief Transmits single data through the USARTx peripheral. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * Data - the data to transmit. + * + * @return none + */ +void USART_SendData(USART_TypeDef *USARTx, uint16_t Data) +{ + USARTx->DATAR = (Data & (uint16_t)0x01FF); +} + +/********************************************************************* + * @fn USART_ReceiveData + * + * @brief Returns the most recent received data by the USARTx peripheral. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * + * @return The received data. + */ +uint16_t USART_ReceiveData(USART_TypeDef *USARTx) +{ + return (uint16_t)(USARTx->DATAR & (uint16_t)0x01FF); +} + +/********************************************************************* + * @fn USART_SendBreak + * + * @brief Transmits break characters. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * + * @return none + */ +void USART_SendBreak(USART_TypeDef *USARTx) +{ + USARTx->CTLR1 |= CTLR1_SBK_Set; +} + +/********************************************************************* + * @fn USART_SetGuardTime + * + * @brief Sets the specified USART guard time. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_GuardTime - specifies the guard time. + * + * @return none + */ +void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime) +{ + USARTx->GPR &= GPR_LSB_Mask; + USARTx->GPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08); +} + +/********************************************************************* + * @fn USART_SetPrescaler + * + * @brief Sets the system clock prescaler. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_Prescaler - specifies the prescaler clock. + * + * @return none + */ +void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler) +{ + USARTx->GPR &= GPR_MSB_Mask; + USARTx->GPR |= USART_Prescaler; +} + +/********************************************************************* + * @fn USART_SmartCardCmd + * + * @brief Enables or disables the USART Smart Card mode. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_SCEN_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_SCEN_Reset; + } +} + +/********************************************************************* + * @fn USART_SmartCardNACKCmd + * + * @brief Enables or disables NACK transmission. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_NACK_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_NACK_Reset; + } +} + +/********************************************************************* + * @fn USART_HalfDuplexCmd + * + * @brief Enables or disables the USART Half Duplex communication. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_HDSEL_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_HDSEL_Reset; + } +} + +/********************************************************************* + * @fn USART_IrDAConfig + * + * @brief Configures the USART's IrDA interface. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_IrDAMode - specifies the IrDA mode. + * USART_IrDAMode_LowPower. + * USART_IrDAMode_Normal. + * + * @return none + */ +void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode) +{ + USARTx->CTLR3 &= CTLR3_IRLP_Mask; + USARTx->CTLR3 |= USART_IrDAMode; +} + +/********************************************************************* + * @fn USART_IrDACmd + * + * @brief Enables or disables the USART's IrDA interface. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * NewState - ENABLE or DISABLE. + * + * @return none + */ +void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState) +{ + if(NewState != DISABLE) + { + USARTx->CTLR3 |= CTLR3_IREN_Set; + } + else + { + USARTx->CTLR3 &= CTLR3_IREN_Reset; + } +} + +/********************************************************************* + * @fn USART_GetFlagStatus + * + * @brief Checks whether the specified USART flag is set or not. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_FLAG - specifies the flag to check. + * USART_FLAG_LBD - LIN Break detection flag. + * USART_FLAG_TXE - Transmit data register empty flag. + * USART_FLAG_TC - Transmission Complete flag. + * USART_FLAG_RXNE - Receive data register not empty flag. + * USART_FLAG_IDLE - Idle Line detection flag. + * USART_FLAG_ORE - OverRun Error flag. + * USART_FLAG_NE - Noise Error flag. + * USART_FLAG_FE - Framing Error flag. + * USART_FLAG_PE - Parity Error flag. + * + * @return bitstatus: SET or RESET + */ +FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG) +{ + FlagStatus bitstatus = RESET; + + if((USARTx->STATR & USART_FLAG) != (uint16_t)RESET) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + return bitstatus; +} + +/********************************************************************* + * @fn USART_ClearFlag + * + * @brief Clears the USARTx's pending flags. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_FLAG - specifies the flag to clear. + * USART_FLAG_LBD - LIN Break detection flag. + * USART_FLAG_TC - Transmission Complete flag. + * USART_FLAG_RXNE - Receive data register not empty flag. + * Note- + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) flags are cleared by software + * sequence: a read operation to USART_STATR register (USART_GetFlagStatus()) + * followed by a read operation to USART_DATAR register (USART_ReceiveData()). + * - RXNE flag can be also cleared by a read to the USART_DATAR register + * (USART_ReceiveData()). + * - TC flag can be also cleared by software sequence: a read operation to + * USART_STATR register (USART_GetFlagStatus()) followed by a write operation + * to USART_DATAR register (USART_SendData()). + * - TXE flag is cleared only by a write to the USART_DATAR register + * (USART_SendData()). + * @return none + */ +void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG) +{ + + USARTx->STATR = (uint16_t)~USART_FLAG; +} + +/********************************************************************* + * @fn USART_GetITStatus + * + * @brief Checks whether the specified USART interrupt has occurred or not. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_IT - specifies the USART interrupt source to check. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TXE - Tansmit Data Register empty interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * USART_IT_IDLE - Idle line detection interrupt. + * USART_IT_ORE_RX - OverRun Error interrupt if the RXNEIE bit is set. + * USART_IT_ORE_ER - OverRun Error interrupt if the EIE bit is set. + * USART_IT_NE - Noise Error interrupt. + * USART_IT_FE - Framing Error interrupt. + * USART_IT_PE - Parity Error interrupt. + * + * @return bitstatus: SET or RESET. + */ +ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT) +{ + uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00; + ITStatus bitstatus = RESET; + + usartreg = (((uint8_t)USART_IT) >> 0x05); + itmask = USART_IT & IT_Mask; + itmask = (uint32_t)0x01 << itmask; + + if(usartreg == 0x01) + { + itmask &= USARTx->CTLR1; + } + else if(usartreg == 0x02) + { + itmask &= USARTx->CTLR2; + } + else + { + itmask &= USARTx->CTLR3; + } + + bitpos = USART_IT >> 0x08; + bitpos = (uint32_t)0x01 << bitpos; + bitpos &= USARTx->STATR; + + if((itmask != (uint16_t)RESET) && (bitpos != (uint16_t)RESET)) + { + bitstatus = SET; + } + else + { + bitstatus = RESET; + } + + return bitstatus; +} + +/********************************************************************* + * @fn USART_ClearITPendingBit + * + * @brief Clears the USARTx's interrupt pending bits. + * + * @param USARTx - where x can be 1, 2, 3 to select the USART peripheral. + * USART_IT - specifies the interrupt pending bit to clear. + * USART_IT_LBD - LIN Break detection interrupt. + * USART_IT_TC - Transmission complete interrupt. + * USART_IT_RXNE - Receive Data register not empty interrupt. + * Note- + * - PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun + * error) and IDLE (Idle line detected) pending bits are cleared by + * software sequence: a read operation to USART_STATR register + * (USART_GetITStatus()) followed by a read operation to USART_DATAR register + * (USART_ReceiveData()). + * - RXNE pending bit can be also cleared by a read to the USART_DATAR register + * (USART_ReceiveData()). + * - TC pending bit can be also cleared by software sequence: a read + * operation to USART_STATR register (USART_GetITStatus()) followed by a write + * operation to USART_DATAR register (USART_SendData()). + * - TXE pending bit is cleared only by a write to the USART_DATAR register + * (USART_SendData()). + * @return none + */ +void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT) +{ + uint16_t bitpos = 0x00, itmask = 0x00; + + bitpos = USART_IT >> 0x08; + itmask = ((uint16_t)0x01 << (uint16_t)bitpos); + USARTx->STATR = (uint16_t)~itmask; +} diff --git a/ch32v103_hallarray_controller/src/periph/ch32v10x_usart.h b/ch32v103_hallarray_controller/src/periph/ch32v10x_usart.h new file mode 100644 index 0000000..74d75cd --- /dev/null +++ b/ch32v103_hallarray_controller/src/periph/ch32v10x_usart.h @@ -0,0 +1,185 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : ch32v10x_usart.h + * Author : WCH + * Version : V1.0.0 + * Date : 2024/01/30 + * Description : This file contains all the functions prototypes for the + * USART firmware library. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __CH32V10x_USART_H +#define __CH32V10x_USART_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "ch32v10x.h" + +/* USART Init Structure definition */ +typedef struct +{ + uint32_t USART_BaudRate; /* This member configures the USART communication baud rate. + The baud rate is computed using the following formula: + - IntegerDivider = ((PCLKx) / (16 * (USART_InitStruct->USART_BaudRate))) + - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 16) + 0.5 */ + + uint16_t USART_WordLength; /* Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_Word_Length */ + + uint16_t USART_StopBits; /* Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint16_t USART_Parity; /* Specifies the parity mode. + This parameter can be a value of @ref USART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint16_t USART_Mode; /* Specifies wether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_Mode */ + + uint16_t USART_HardwareFlowControl; /* Specifies wether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} USART_InitTypeDef; + +/* USART Clock Init Structure definition */ +typedef struct +{ + uint16_t USART_Clock; /* Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_Clock */ + + uint16_t USART_CPOL; /* Specifies the steady state value of the serial clock. + This parameter can be a value of @ref USART_Clock_Polarity */ + + uint16_t USART_CPHA; /* Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_Clock_Phase */ + + uint16_t USART_LastBit; /* Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_Last_Bit */ +} USART_ClockInitTypeDef; + +/* USART_Word_Length */ +#define USART_WordLength_8b ((uint16_t)0x0000) +#define USART_WordLength_9b ((uint16_t)0x1000) + +/* USART_Stop_Bits */ +#define USART_StopBits_1 ((uint16_t)0x0000) +#define USART_StopBits_0_5 ((uint16_t)0x1000) +#define USART_StopBits_2 ((uint16_t)0x2000) +#define USART_StopBits_1_5 ((uint16_t)0x3000) + +/* USART_Parity */ +#define USART_Parity_No ((uint16_t)0x0000) +#define USART_Parity_Even ((uint16_t)0x0400) +#define USART_Parity_Odd ((uint16_t)0x0600) + +/* USART_Mode */ +#define USART_Mode_Rx ((uint16_t)0x0004) +#define USART_Mode_Tx ((uint16_t)0x0008) + +/* USART_Hardware_Flow_Control */ +#define USART_HardwareFlowControl_None ((uint16_t)0x0000) +#define USART_HardwareFlowControl_RTS ((uint16_t)0x0100) +#define USART_HardwareFlowControl_CTS ((uint16_t)0x0200) +#define USART_HardwareFlowControl_RTS_CTS ((uint16_t)0x0300) + +/* USART_Clock */ +#define USART_Clock_Disable ((uint16_t)0x0000) +#define USART_Clock_Enable ((uint16_t)0x0800) + +/* USART_Clock_Polarity */ +#define USART_CPOL_Low ((uint16_t)0x0000) +#define USART_CPOL_High ((uint16_t)0x0400) + +/* USART_Clock_Phase */ +#define USART_CPHA_1Edge ((uint16_t)0x0000) +#define USART_CPHA_2Edge ((uint16_t)0x0200) + +/* USART_Last_Bit */ +#define USART_LastBit_Disable ((uint16_t)0x0000) +#define USART_LastBit_Enable ((uint16_t)0x0100) + +/* USART_Interrupt_definition */ +#define USART_IT_PE ((uint16_t)0x0028) +#define USART_IT_TXE ((uint16_t)0x0727) +#define USART_IT_TC ((uint16_t)0x0626) +#define USART_IT_RXNE ((uint16_t)0x0525) +#define USART_IT_ORE_RX ((uint16_t)0x0325) +#define USART_IT_IDLE ((uint16_t)0x0424) +#define USART_IT_LBD ((uint16_t)0x0846) +#define USART_IT_CTS ((uint16_t)0x096A) +#define USART_IT_ERR ((uint16_t)0x0060) +#define USART_IT_ORE_ER ((uint16_t)0x0360) +#define USART_IT_NE ((uint16_t)0x0260) +#define USART_IT_FE ((uint16_t)0x0160) + +#define USART_IT_ORE USART_IT_ORE_ER + +/* USART_DMA_Requests */ +#define USART_DMAReq_Tx ((uint16_t)0x0080) +#define USART_DMAReq_Rx ((uint16_t)0x0040) + +/* USART_WakeUp_methods */ +#define USART_WakeUp_IdleLine ((uint16_t)0x0000) +#define USART_WakeUp_AddressMark ((uint16_t)0x0800) + +/* USART_LIN_Break_Detection_Length */ +#define USART_LINBreakDetectLength_10b ((uint16_t)0x0000) +#define USART_LINBreakDetectLength_11b ((uint16_t)0x0020) + +/* USART_IrDA_Low_Power */ +#define USART_IrDAMode_LowPower ((uint16_t)0x0004) +#define USART_IrDAMode_Normal ((uint16_t)0x0000) + +/* USART_Flags */ +#define USART_FLAG_CTS ((uint16_t)0x0200) +#define USART_FLAG_LBD ((uint16_t)0x0100) +#define USART_FLAG_TXE ((uint16_t)0x0080) +#define USART_FLAG_TC ((uint16_t)0x0040) +#define USART_FLAG_RXNE ((uint16_t)0x0020) +#define USART_FLAG_IDLE ((uint16_t)0x0010) +#define USART_FLAG_ORE ((uint16_t)0x0008) +#define USART_FLAG_NE ((uint16_t)0x0004) +#define USART_FLAG_FE ((uint16_t)0x0002) +#define USART_FLAG_PE ((uint16_t)0x0001) + +void USART_DeInit(USART_TypeDef *USARTx); +void USART_Init(USART_TypeDef *USARTx, USART_InitTypeDef *USART_InitStruct); +void USART_StructInit(USART_InitTypeDef *USART_InitStruct); +void USART_ClockInit(USART_TypeDef *USARTx, USART_ClockInitTypeDef *USART_ClockInitStruct); +void USART_ClockStructInit(USART_ClockInitTypeDef *USART_ClockInitStruct); +void USART_Cmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_ITConfig(USART_TypeDef *USARTx, uint16_t USART_IT, FunctionalState NewState); +void USART_DMACmd(USART_TypeDef *USARTx, uint16_t USART_DMAReq, FunctionalState NewState); +void USART_SetAddress(USART_TypeDef *USARTx, uint8_t USART_Address); +void USART_WakeUpConfig(USART_TypeDef *USARTx, uint16_t USART_WakeUp); +void USART_ReceiverWakeUpCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_LINBreakDetectLengthConfig(USART_TypeDef *USARTx, uint16_t USART_LINBreakDetectLength); +void USART_LINCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_SendData(USART_TypeDef *USARTx, uint16_t Data); +uint16_t USART_ReceiveData(USART_TypeDef *USARTx); +void USART_SendBreak(USART_TypeDef *USARTx); +void USART_SetGuardTime(USART_TypeDef *USARTx, uint8_t USART_GuardTime); +void USART_SetPrescaler(USART_TypeDef *USARTx, uint8_t USART_Prescaler); +void USART_SmartCardCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_SmartCardNACKCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_HalfDuplexCmd(USART_TypeDef *USARTx, FunctionalState NewState); +void USART_IrDAConfig(USART_TypeDef *USARTx, uint16_t USART_IrDAMode); +void USART_IrDACmd(USART_TypeDef *USARTx, FunctionalState NewState); +FlagStatus USART_GetFlagStatus(USART_TypeDef *USARTx, uint16_t USART_FLAG); +void USART_ClearFlag(USART_TypeDef *USARTx, uint16_t USART_FLAG); +ITStatus USART_GetITStatus(USART_TypeDef *USARTx, uint16_t USART_IT); +void USART_ClearITPendingBit(USART_TypeDef *USARTx, uint16_t USART_IT); + +#ifdef __cplusplus +} +#endif + +#endif /* __CH32V10x_USART_H */ diff --git a/ch32v103_hallarray_controller/src/user/app_main.c b/ch32v103_hallarray_controller/src/user/app_main.c new file mode 100644 index 0000000..655f140 --- /dev/null +++ b/ch32v103_hallarray_controller/src/user/app_main.c @@ -0,0 +1,151 @@ +#include "app_main.h" +#include "app_usb_cdc.h" +#include +#include "bsp_led_key.h" +#include "bsp_uart1.h" +#include "bsp_adc1.h" +#include "util_delay.h" + +#define BSP_ADC_CHANNEL_COUNT 15 +#define BSP_ADC_SAMPLE_RATE 2000 //ADC时钟为12M 采样时间12.5+71.5个ADC时钟 15个通道共15*(12.5+71.5)*(1/12MHz)=105us +#define BSP_ADC_AVERAGE_COUNT 20 +#define BSP_ADC_CALIBRATION_COUNT 200 + +uint16_t adc_buffer[BSP_ADC_CHANNEL_COUNT * BSP_ADC_AVERAGE_COUNT * 2]; //15个通道 每50次采样平均 双缓冲 +int32_t adc_offset[15] = { 2048, 2048, 2048, 2048, 2048, 2048, 2048, 2048, 2048, 2048, 2048, 2048, 2048, 2048, 2048 }; +volatile uint16_t calibration_count_left = 0; + +void adc_send_to_uart(int32_t *adc_result) +{ + static char uart_buffer1[64], uart_buffer2[64]; //双缓冲 + + for (uint16_t channel = 0; channel < BSP_ADC_CHANNEL_COUNT; channel ++) { + char *uart_string = channel % 2 ? uart_buffer1 : uart_buffer2; //切换双缓冲 + + const char *color_string = NULL; //根据数值范围更改文本颜色 + int32_t value = adc_result[channel] - adc_offset[channel]; + + if (value < - 5) { + color_string = "BLUE"; + } else if (value > 5) { + color_string = "RED"; + } else { + color_string = "BLACK"; + } + + uint16_t uart_length = snprintf(uart_string, sizeof(uart_buffer1), + "t%d_%d.txt=\"%d\"\xFF\xFF\xFFt%d_%d.pco=%s\xFF\xFF\xFF", + channel / 3 + 1, channel % 3 + 1, value, + channel / 3 + 1, channel % 3 + 1, color_string + ); + + bsp_uart1_send(uart_string, uart_length); + } +} + +void adc_send_to_cdc(int32_t *adc_result) +{ + if (cdc_dtr_flag == 0) { + return; + } + + static uint8_t count = 0; + + static char cdc_buffer1[128], cdc_buffer2[128]; //双缓冲 + char *cdc_string = count % 2 ? cdc_buffer1 : cdc_buffer2; //切换双缓冲 + + uint16_t cdc_length = snprintf(cdc_string, sizeof(cdc_buffer1), + "%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d,%d\r\n", + adc_result[0] - adc_offset[0], adc_result[1] - adc_offset[1], adc_result[2] - adc_offset[2], + adc_result[3] - adc_offset[3], adc_result[4] - adc_offset[4], adc_result[5] - adc_offset[5], + adc_result[6] - adc_offset[6], adc_result[7] - adc_offset[7], adc_result[8] - adc_offset[8], + adc_result[9] - adc_offset[9], adc_result[10] - adc_offset[10], adc_result[11] - adc_offset[11], + adc_result[12] - adc_offset[12], adc_result[13] - adc_offset[13], adc_result[14] - adc_offset[14] + ); + + usbd_ep_start_write(0, CDC_IN_EP, cdc_string, cdc_length); + + count ++; +} + +void adc_calibrate_start(void) +{ + memset(adc_offset, 0, sizeof(adc_offset)); + + calibration_count_left = BSP_ADC_CALIBRATION_COUNT; //进入校准模式 +} + +void adc_calibrate_routine(int32_t *adc_result) +{ + for (uint16_t channel = 0; channel < BSP_ADC_CHANNEL_COUNT; channel ++) { + adc_offset[channel] += adc_result[channel]; + } +} + +void adc_calibrate_finish(void) +{ + for (uint16_t channel = 0; channel < BSP_ADC_CHANNEL_COUNT; channel ++) { + adc_offset[channel] /= BSP_ADC_CALIBRATION_COUNT; + } +} + +void adc_dma_callback(uint16_t *buffer, uint16_t length) +{ + int32_t channel_avg[BSP_ADC_CHANNEL_COUNT] = { 0 }; + + for (uint16_t channel = 0; channel < BSP_ADC_CHANNEL_COUNT; channel ++) { + for (uint16_t count = 0; count < length / BSP_ADC_CHANNEL_COUNT; count ++) { + channel_avg[channel] += buffer[count * BSP_ADC_CHANNEL_COUNT + channel]; + } + channel_avg[channel] /= (length / BSP_ADC_CHANNEL_COUNT); //取平均 + } + + static uint32_t count = 0; + + if (calibration_count_left == 0) { //当前不处于校准模式 + adc_send_to_cdc(channel_avg); //100Hz + + if (count % 10 == 0) { //100Hz/20 = 10Hz + adc_send_to_uart(channel_avg); + } + + if (count % 50 == 0) { //100Hz/50 = 2Hz + bsp_led_green_toggle(); //LED慢闪 + } + } else { //当前处于校准模式 + if (count % 5 == 0) { //100Hz/50 = 20Hz + bsp_led_green_toggle(); //LED快闪 + } + + adc_calibrate_routine(channel_avg); + + calibration_count_left --; + if (calibration_count_left == 0) { + adc_calibrate_finish(); + } + } + + count ++; +} + +void app_main(void) +{ + delay_init(); + bsp_uart1_init(921600); + bsp_led_key_init(); + bsp_adc1_init(adc_buffer, BSP_ADC_CHANNEL_COUNT * BSP_ADC_AVERAGE_COUNT * 2, BSP_ADC_CHANNEL_COUNT); + bsp_adc1_irq_enable(adc_dma_callback); + bsp_adc1_start_dma(BSP_ADC_SAMPLE_RATE); + + cdc_acm_init(0, 0x40023400); + + while (1) { + if (bsp_key_read() && calibration_count_left == 0) { + adc_calibrate_start(); + + delay_ms(50); + while (bsp_key_read()); + delay_ms(5000); //防止重复进入 + } + } +} diff --git a/ch32v103_hallarray_controller/src/user/app_main.h b/ch32v103_hallarray_controller/src/user/app_main.h new file mode 100644 index 0000000..02108d1 --- /dev/null +++ b/ch32v103_hallarray_controller/src/user/app_main.h @@ -0,0 +1,8 @@ +#ifndef __APP_MAIN_H +#define __APP_MAIN_H + +#include "ch32v10x.h" + +void app_main(void); + +#endif diff --git a/ch32v103_hallarray_controller/src/user/app_usb_cdc.c b/ch32v103_hallarray_controller/src/user/app_usb_cdc.c new file mode 100644 index 0000000..9681c02 --- /dev/null +++ b/ch32v103_hallarray_controller/src/user/app_usb_cdc.c @@ -0,0 +1,208 @@ +#include "app_usb_cdc.h" +#include "bsp_led_key.h" + +#define USB_CONFIG_SIZE (9 + CDC_ACM_DESCRIPTOR_LEN) + +volatile bool cdc_tx_busy_flag = false; +volatile bool cdc_dtr_flag = false; + +USB_MEM_ALIGNX uint8_t read_buffer[CDC_MAX_MPS]; +USB_MEM_ALIGNX uint8_t write_buffer[CDC_MAX_MPS]; + +static uint8_t cdc_descriptor[] = { + /* 设备(Device)描述符 所有设备有且只有一个 */ + USB_DEVICE_DESCRIPTOR_INIT(USB_1_1, 0xEF, 0x02, 0x01, USBD_VID, USBD_PID, 0x0100, 0x01), + + /* 配置(Configuration)描述符 所有设备至少有一个 */ + USB_CONFIG_DESCRIPTOR_INIT(USB_CONFIG_SIZE, 0x02, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER_MA), + /* 截至此处的配置描述符长度: 9 */ + + /* 接口(Interface)描述符 USB-CDC设备 */ + CDC_ACM_DESCRIPTOR_INIT(0x00, CDC_INT_EP, CDC_OUT_EP, CDC_IN_EP, CDC_MAX_MPS, 0x02), + + /* 字符串(String)描述符 设备支持的语言描述符 */ + USB_LANGID_INIT(1033), + + /* 字符串(String)描述符 制造商字符串 */ + 0x10, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'P', 0x00, + 'M', 0x00, + 'S', 0x00, + '@', 0x00, + 'U', 0x00, + 'P', 0x00, + 'C', 0x00, /* 共7字符 */ + + /* 字符串(String)描述符 产品字符串 */ + 0x2C, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + 'H', 0x00, + 'a', 0x00, + 'l', 0x00, + 'l', 0x00, + ' ', 0x00, + 'A', 0x00, + 'r', 0x00, + 'r', 0x00, + 'a', 0x00, + 'y', 0x00, + ' ', 0x00, + 'C', 0x00, + 'o', 0x00, + 'n', 0x00, + 't', 0x00, + 'r', 0x00, + 'o', 0x00, + 'l', 0x00, + 'l', 0x00, + 'e', 0x00, + 'r', 0x00, /* 共21字符 */ + + /* 字符串(String)描述符 序列号字符串 */ + 0x32, /* bLength */ + USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ + '0', 0x00, + '0', 0x00, + '0', 0x00, + '0', 0x00, + '0', 0x00, + '0', 0x00, + '0', 0x00, + '0', 0x00, + '0', 0x00, + '0', 0x00, + '0', 0x00, + '0', 0x00, + '0', 0x00, + '0', 0x00, + '0', 0x00, + '0', 0x00, + '0', 0x00, + '0', 0x00, + '0', 0x00, + '0', 0x00, + '0', 0x00, + '0', 0x00, + '0', 0x00, + '0', 0x00, /* 共24字符 */ + 0x00 +}; + +static void usbd_event_handler(uint8_t busid, uint8_t event) +{ + switch (event) { + case USBD_EVENT_RESET: + printf("usb reset event\n"); + break; + case USBD_EVENT_CONNECTED: + printf("usb connected event\n"); + break; + case USBD_EVENT_DISCONNECTED: + printf("usb disconnect event\n"); + break; + case USBD_EVENT_RESUME: + printf("usb resume event\n"); + break; + case USBD_EVENT_SUSPEND: + printf("usb suspend event\n"); + break; + case USBD_EVENT_CONFIGURED: + printf("usb configured event\n"); + + cdc_tx_busy_flag = false; + usbd_ep_start_read(busid, CDC_OUT_EP, read_buffer, CDC_MAX_MPS); + break; + case USBD_EVENT_SET_REMOTE_WAKEUP: + break; + case USBD_EVENT_CLR_REMOTE_WAKEUP: + break; + + default: + break; + } +} + +void usbd_cdc_acm_bulk_out(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ + if (nbytes < sizeof(read_buffer)) { + read_buffer[nbytes] = '\0'; + } + +// printf("cdc received %d bytes of data, content: %s\n", nbytes, read_buffer); + + usbd_ep_start_read(busid, CDC_OUT_EP, read_buffer, CDC_MAX_MPS); +} + +void usbd_cdc_acm_bulk_in(uint8_t busid, uint8_t ep, uint32_t nbytes) +{ +// printf("cdc sent %d bytes of data\n", nbytes); + + if ((nbytes % usbd_get_ep_mps(busid, ep)) == 0 && nbytes) { //send zlp + usbd_ep_start_write(busid, CDC_IN_EP, NULL, 0); + } else { + cdc_tx_busy_flag = false; + } +} + +static void fill_usb_descriptor_serial_number(void) +{ + char uid_string[25]; + sprintf(uid_string, "%08X%08X%08X", *(volatile uint32_t *)0x1FFFF7E8, *(volatile uint32_t *)0x1FFFF7EC, *(volatile uint32_t *)0x1FFFF7F0); + + uint16_t serial_number_offset = 0; + + for (uint16_t i = 0; i < sizeof(cdc_descriptor) - 3; i ++) { //查找USB描述符中序列号字符描述符的偏移 + if (cdc_descriptor[i + 0] == '0' && cdc_descriptor[i + 1] == 0x00 && + cdc_descriptor[i + 2] == '0' && cdc_descriptor[i + 3] == 0x00) { + serial_number_offset = i; + break; + } + } + + if (serial_number_offset == 0) { //未找到 + return; + } + + for (uint8_t i = 0; i < 24; i ++) { //共24位 + cdc_descriptor[serial_number_offset + i * 2] = uid_string[i]; + } +} + +void cdc_acm_init(uint8_t busid, uintptr_t reg_base) +{ + fill_usb_descriptor_serial_number(); + + usbd_desc_register(busid, cdc_descriptor); + + static struct usbd_interface intf0; + static struct usbd_interface intf1; + usbd_add_interface(busid, usbd_cdc_acm_init_intf(busid, &intf0)); + usbd_add_interface(busid, usbd_cdc_acm_init_intf(busid, &intf1)); //USB CDC需要添加两个接口，否则CDC接口后面的接口会有问题 + + struct usbd_endpoint cdc_out_ep = { + .ep_addr = CDC_OUT_EP, + .ep_cb = usbd_cdc_acm_bulk_out + }; + + struct usbd_endpoint cdc_in_ep = { + .ep_addr = CDC_IN_EP, + .ep_cb = usbd_cdc_acm_bulk_in + }; + usbd_add_endpoint(busid, &cdc_out_ep); + usbd_add_endpoint(busid, &cdc_in_ep); + + usbd_initialize(busid, reg_base, usbd_event_handler); +} + +void usbd_cdc_acm_set_dtr(uint8_t busid, uint8_t intf, bool dtr) +{ + if (dtr) { + bsp_led_blue_on(); + } else { + bsp_led_blue_off(); + } + + cdc_dtr_flag = dtr; +// printf("dtr is set to %d\n", dtr); +} diff --git a/ch32v103_hallarray_controller/src/user/app_usb_cdc.h b/ch32v103_hallarray_controller/src/user/app_usb_cdc.h new file mode 100644 index 0000000..23be88e --- /dev/null +++ b/ch32v103_hallarray_controller/src/user/app_usb_cdc.h @@ -0,0 +1,22 @@ +#ifndef __APP_USB_CDC_H +#define __APP_USB_CDC_H + +#include "usbd_core.h" +#include "usbd_cdc_acm.h" + +#define USBD_VID 0x1A86 +#define USBD_PID 0xFE0C +#define USBD_MAX_POWER_MA 500 + +#define CDC_IN_EP 0x81 +#define CDC_OUT_EP 0x02 +#define CDC_INT_EP 0x83 + +#define CDC_MAX_MPS 64 + +extern volatile bool cdc_tx_busy_flag; +extern volatile bool cdc_dtr_flag; + +void cdc_acm_init(uint8_t busid, uintptr_t reg_base); + +#endif diff --git a/ch32v103_hallarray_controller/src/user/bsp_adc1.c b/ch32v103_hallarray_controller/src/user/bsp_adc1.c new file mode 100644 index 0000000..4dc47e9 --- /dev/null +++ b/ch32v103_hallarray_controller/src/user/bsp_adc1.c @@ -0,0 +1,172 @@ +#include "bsp_adc1.h" +#include + +static uint16_t *bsp_adc1_dma_buffer = NULL; +static uint16_t bsp_adc1_dma_buffer_size = 0; +static adc_dma_done_callback_t bsp_adc1_dma_done_callback = NULL; + +void bsp_adc1_init(uint16_t *dma_buffer, uint32_t dma_buffer_size, uint16_t adc_channel_count) //需要传入双倍大小的buffer 会产生HT和TC两个中断 +{ + if (dma_buffer == NULL) { + return; + } + + if (dma_buffer_size == 0 || dma_buffer_size % (adc_channel_count * 2)) { + return; + } + + bsp_adc1_dma_buffer = dma_buffer; + bsp_adc1_dma_buffer_size = dma_buffer_size; + + /* 使能各外设时钟 */ + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOA | RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC, ENABLE); + + RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADC1, ENABLE); + RCC_ADCCLKConfig(RCC_PCLK2_Div8); //72MHz/8=12MHz + + /* 初始化用于ADC输入的GPIO */ + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 | GPIO_Pin_6 | GPIO_Pin_7; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AIN; + GPIO_Init(GPIOA, &GPIO_InitStructure); //ADC1_IN0-IN7=PA0-PA7 + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0; + GPIO_Init(GPIOB, &GPIO_InitStructure); //ADC1_IN8=PB0 + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5; + GPIO_Init(GPIOC, &GPIO_InitStructure); //ADC1_IN10-IN15=PC0-PC5 + + /* 初始化ADC */ + ADC_DeInit(ADC1); + + ADC_InitTypeDef ADC_InitStructure; + ADC_InitStructure.ADC_Mode = ADC_Mode_Independent; + ADC_InitStructure.ADC_ScanConvMode = ENABLE; //使能扫描转换模式 + ADC_InitStructure.ADC_ContinuousConvMode = DISABLE; + ADC_InitStructure.ADC_ExternalTrigConv = ADC_ExternalTrigConv_T3_TRGO; //选择定时器3作为触发源 + ADC_InitStructure.ADC_DataAlign = ADC_DataAlign_Right; + ADC_InitStructure.ADC_NbrOfChannel = adc_channel_count; //启用15个通道 + ADC_Init(ADC1, &ADC_InitStructure); + ADC_Cmd(ADC1, ENABLE); //使能ADC + + /* 初始化用于传输ADC采样数据的DMA */ + DMA_DeInit(DMA1_Channel1); + + DMA_InitTypeDef DMA_InitStructure = { 0 }; + DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&ADC1->RDATAR; + DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)dma_buffer; + DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC; + DMA_InitStructure.DMA_BufferSize = dma_buffer_size; + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord; + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord; //uint16_t + DMA_InitStructure.DMA_Mode = DMA_Mode_Circular; + DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh; + DMA_InitStructure.DMA_M2M = DMA_M2M_Disable; + DMA_Init(DMA1_Channel1, &DMA_InitStructure); + + /* 设置ADC规则组通道 */ + ADC_RegularChannelConfig(ADC1, ADC_Channel_8, 1, ADC_SampleTime_71Cycles5); + ADC_RegularChannelConfig(ADC1, ADC_Channel_5, 2, ADC_SampleTime_71Cycles5); + ADC_RegularChannelConfig(ADC1, ADC_Channel_0, 3, ADC_SampleTime_71Cycles5); + ADC_RegularChannelConfig(ADC1, ADC_Channel_15, 4, ADC_SampleTime_71Cycles5); + ADC_RegularChannelConfig(ADC1, ADC_Channel_4, 5, ADC_SampleTime_71Cycles5); + ADC_RegularChannelConfig(ADC1, ADC_Channel_13, 6, ADC_SampleTime_71Cycles5); + ADC_RegularChannelConfig(ADC1, ADC_Channel_14, 7, ADC_SampleTime_71Cycles5); + ADC_RegularChannelConfig(ADC1, ADC_Channel_3, 8, ADC_SampleTime_71Cycles5); + ADC_RegularChannelConfig(ADC1, ADC_Channel_12, 9, ADC_SampleTime_71Cycles5); + ADC_RegularChannelConfig(ADC1, ADC_Channel_7, 10, ADC_SampleTime_71Cycles5); + ADC_RegularChannelConfig(ADC1, ADC_Channel_2, 11, ADC_SampleTime_71Cycles5); + ADC_RegularChannelConfig(ADC1, ADC_Channel_11, 12, ADC_SampleTime_71Cycles5); + ADC_RegularChannelConfig(ADC1, ADC_Channel_6, 13, ADC_SampleTime_71Cycles5); + ADC_RegularChannelConfig(ADC1, ADC_Channel_1, 14, ADC_SampleTime_71Cycles5); + ADC_RegularChannelConfig(ADC1, ADC_Channel_10, 15, ADC_SampleTime_71Cycles5); + ADC_RegularChannelConfig(ADC1, ADC_Channel_9, 16, ADC_SampleTime_71Cycles5); + + /* 校准ADC WCH的ADC校准并没有什么用 */ +// ADC_ResetCalibration(ADC1); +// while (ADC_GetResetCalibrationStatus(ADC1)); +// ADC_StartCalibration(ADC1); +// while (ADC_GetCalibrationStatus(ADC1)); +} + +void bsp_adc1_start_dma(uint32_t samples_per_second) //20-1000 +{ + RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE); + + /* 初始化用于触发ADC的定时器 */ + TIM_DeInit(TIM3); + + TIM_TimeBaseInitTypeDef TIM_TimeBaseInitStructure; + TIM_TimeBaseInitStructure.TIM_Period = 1000000 / samples_per_second - 1; //定时器触发频率 + TIM_TimeBaseInitStructure.TIM_Prescaler = SystemCoreClock / 1000000 - 1; //定时器时钟频率1MHz + TIM_TimeBaseInitStructure.TIM_ClockDivision = TIM_CKD_DIV1; + TIM_TimeBaseInitStructure.TIM_CounterMode = TIM_CounterMode_Up; + TIM_TimeBaseInit(TIM3, &TIM_TimeBaseInitStructure); + TIM_SelectOutputTrigger(TIM3, TIM_TRGOSource_Update); //选择定时器溢出事件作为ADC的触发源 + + /* 使能定时器与DMA 开始转换 */ + ADC_ExternalTrigConvCmd(ADC1, ENABLE); //使能外部触发 + ADC_DMACmd(ADC1, ENABLE); //使能ADC的DMA请求 + + DMA_Cmd(DMA1_Channel1, ENABLE); + TIM_Cmd(TIM3, ENABLE); +} + +void bsp_adc1_stop(void) +{ + TIM_Cmd(TIM3, DISABLE); + DMA_Cmd(DMA1_Channel1, DISABLE); + + ADC_DMACmd(ADC1, DISABLE); + ADC_ExternalTrigConvCmd(ADC1, DISABLE); + + DMA_ITConfig(DMA1_Channel1, DMA1_IT_HT1 | DMA1_IT_TC1, DISABLE); +} + +void bsp_adc1_irq_enable(adc_dma_done_callback_t adc_dma_done_callback) +{ + if (adc_dma_done_callback == NULL) { + return; + } + + bsp_adc1_dma_done_callback = adc_dma_done_callback; + + /* 初始化DMA中断 */ + NVIC_InitTypeDef NVIC_InitStructure; + NVIC_InitStructure.NVIC_IRQChannel = DMA1_Channel1_IRQn; + NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0; + NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&NVIC_InitStructure); + + DMA_ITConfig(DMA1_Channel1, DMA1_IT_HT1 | DMA1_IT_TC1, ENABLE); //使能DMA的半传输中断与传输完成中断 +} + +void bsp_adc1_irq_disable(void) +{ + DMA_ITConfig(DMA1_Channel1, DMA1_IT_HT1 | DMA1_IT_TC1, DISABLE); + + NVIC_DisableIRQ(DMA1_Channel1_IRQn); +} + +void DMA1_Channel1_IRQHandler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); + +void DMA1_Channel1_IRQHandler(void) +{ + if (DMA_GetITStatus(DMA1_IT_HT1)) { + if (bsp_adc1_dma_done_callback != NULL) { + bsp_adc1_dma_done_callback(&bsp_adc1_dma_buffer[0], bsp_adc1_dma_buffer_size / 2); + } + DMA_ClearFlag(DMA1_IT_HT1); + } + + if (DMA_GetITStatus(DMA1_IT_TC1)) { + if (bsp_adc1_dma_done_callback != NULL) { + bsp_adc1_dma_done_callback(&bsp_adc1_dma_buffer[bsp_adc1_dma_buffer_size / 2], bsp_adc1_dma_buffer_size / 2); + } + DMA_ClearFlag(DMA1_IT_TC1); + } +} diff --git a/ch32v103_hallarray_controller/src/user/bsp_adc1.h b/ch32v103_hallarray_controller/src/user/bsp_adc1.h new file mode 100644 index 0000000..5578522 --- /dev/null +++ b/ch32v103_hallarray_controller/src/user/bsp_adc1.h @@ -0,0 +1,15 @@ +#ifndef __BSP_ADC1_H +#define __BSP_ADC1_H + +#include "ch32v10x.h" + +typedef void(*adc_dma_done_callback_t)(uint16_t *buffer, uint16_t length); + +void bsp_adc1_init(uint16_t *buffer, uint32_t buffer_size, uint16_t adc_channel_count); +void bsp_adc1_start_dma(uint32_t samples_per_second); //20-1000 +void bsp_adc1_stop(void); + +void bsp_adc1_irq_enable(adc_dma_done_callback_t adc_dma_done_callback); +void bsp_adc1_irq_disable(void); + +#endif diff --git a/ch32v103_hallarray_controller/src/user/bsp_led_key.c b/ch32v103_hallarray_controller/src/user/bsp_led_key.c new file mode 100644 index 0000000..11f1b15 --- /dev/null +++ b/ch32v103_hallarray_controller/src/user/bsp_led_key.c @@ -0,0 +1,53 @@ +#include "bsp_led_key.h" + +void bsp_led_key_init(void) +{ + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB | RCC_APB2Periph_GPIOC, ENABLE); + + GPIO_WriteBit(GPIOC, GPIO_Pin_11 | GPIO_Pin_12, RESET); + + GPIO_InitTypeDef GPIO_InitStructure; + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_11 | GPIO_Pin_12; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_2MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_Init(GPIOC, &GPIO_InitStructure); //LED_G=PC11 LED_B=PC12 + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOB, &GPIO_InitStructure); //KEY=PB5 +} + +void bsp_led_green_on(void) +{ + GPIO_WriteBit(GPIOC, GPIO_Pin_11, SET); +} + +void bsp_led_green_off(void) +{ + GPIO_WriteBit(GPIOC, GPIO_Pin_11, RESET); +} + +void bsp_led_green_toggle(void) +{ + GPIO_WriteBit(GPIOC, GPIO_Pin_11, !GPIO_ReadOutputDataBit(GPIOC, GPIO_Pin_11)); +} + +void bsp_led_blue_on(void) +{ + GPIO_WriteBit(GPIOC, GPIO_Pin_12, SET); +} + +void bsp_led_blue_off(void) +{ + GPIO_WriteBit(GPIOC, GPIO_Pin_12, RESET); +} + +void bsp_led_blue_toggle(void) +{ + GPIO_WriteBit(GPIOC, GPIO_Pin_12, !GPIO_ReadOutputDataBit(GPIOC, GPIO_Pin_12)); +} + +uint8_t bsp_key_read(void) +{ + return GPIO_ReadInputDataBit(GPIOB, GPIO_Pin_5) == RESET; +} diff --git a/ch32v103_hallarray_controller/src/user/bsp_led_key.h b/ch32v103_hallarray_controller/src/user/bsp_led_key.h new file mode 100644 index 0000000..f9db7a7 --- /dev/null +++ b/ch32v103_hallarray_controller/src/user/bsp_led_key.h @@ -0,0 +1,15 @@ +#ifndef __BSP_LED_KEY_H +#define __BSP_LED_KEY_H + +#include "ch32v10x.h" + +void bsp_led_key_init(void); +void bsp_led_green_on(void); +void bsp_led_green_off(void); +void bsp_led_green_toggle(void); +void bsp_led_blue_on(void); +void bsp_led_blue_off(void); +void bsp_led_blue_toggle(void); +uint8_t bsp_key_read(void); + +#endif diff --git a/ch32v103_hallarray_controller/src/user/bsp_uart1.c b/ch32v103_hallarray_controller/src/user/bsp_uart1.c new file mode 100644 index 0000000..e07bbd4 --- /dev/null +++ b/ch32v103_hallarray_controller/src/user/bsp_uart1.c @@ -0,0 +1,65 @@ +#include "bsp_uart1.h" +#include + +void bsp_uart1_init(uint32_t baudrate) +{ + GPIO_InitTypeDef GPIO_InitStructure; + USART_InitTypeDef USART_InitStructure; + + RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1 | RCC_APB2Periph_GPIOA, ENABLE); + RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_9; //USART1_TX=PA9 + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF_PP; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_10; //USART1_TX=PA10 + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_IPU; + GPIO_Init(GPIOA, &GPIO_InitStructure); + + USART_InitStructure.USART_BaudRate = baudrate; + USART_InitStructure.USART_WordLength = USART_WordLength_8b; + USART_InitStructure.USART_StopBits = USART_StopBits_1; + USART_InitStructure.USART_Parity = USART_Parity_No; + USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + USART_InitStructure.USART_Mode = USART_Mode_Tx | USART_Mode_Rx; + + USART_Init(USART1, &USART_InitStructure); + USART_Cmd(USART1, ENABLE); + USART_DMACmd(USART1, USART_DMAReq_Tx, ENABLE); //使能UART1的DMA发送 + + DMA_InitTypeDef DMA_InitStructure; + DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)&USART1->DATAR; //USART1数据寄存器地址 + DMA_InitStructure.DMA_MemoryBaseAddr = 0; //数据缓冲区地址 + DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST; //外设->内存方向 + DMA_InitStructure.DMA_BufferSize = 0; //缓冲区大小 + DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; //外设地址不自增 + DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable; //内存地址自增 + DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte; //外设数据大小：字节 + DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte; //内存数据大小：字节 + DMA_InitStructure.DMA_Mode = DMA_Mode_Normal; //普通模式 + DMA_InitStructure.DMA_Priority = DMA_Priority_Medium; //中优先级 + DMA_InitStructure.DMA_M2M = DMA_M2M_Disable; //非内存到内存传输 + DMA_Init(DMA1_Channel4, &DMA_InitStructure); +} + +void bsp_uart1_send(uint8_t *buffer, uint16_t size) +{ + static uint8_t skip_first_wait = 1; + + while (DMA_GetFlagStatus(DMA1_FLAG_TC4) == RESET) { //等待传输完成 + if (skip_first_wait != 0) { + skip_first_wait = 0; + break; + } + } + + DMA_ClearFlag(DMA1_FLAG_TC4); //清除传输完成标志 + DMA_Cmd(DMA1_Channel4, DISABLE); //禁用DMA通道4 + + DMA1_Channel4->MADDR = (uint32_t)buffer; //设置DMA传输的内存地址 + DMA1_Channel4->CNTR = size; //设置DMA传输数据长度 + + DMA_Cmd(DMA1_Channel4, ENABLE); //使能DMA通道4，开始发送 +} diff --git a/ch32v103_hallarray_controller/src/user/bsp_uart1.h b/ch32v103_hallarray_controller/src/user/bsp_uart1.h new file mode 100644 index 0000000..1bbb99e --- /dev/null +++ b/ch32v103_hallarray_controller/src/user/bsp_uart1.h @@ -0,0 +1,9 @@ +#ifndef __BSP_UART1_H +#define __BSP_UART1_H + +#include "ch32v10x.h" + +void bsp_uart1_init(uint32_t baudrate); +void bsp_uart1_send(uint8_t *buffer, uint16_t size); + +#endif diff --git a/ch32v103_hallarray_controller/src/user/ch32v10x_conf.h b/ch32v103_hallarray_controller/src/user/ch32v10x_conf.h new file mode 100644 index 0000000..075257e --- /dev/null +++ b/ch32v103_hallarray_controller/src/user/ch32v10x_conf.h @@ -0,0 +1,12 @@ +#ifndef __CH32V10x_CONF_H +#define __CH32V10x_CONF_H + +#include "ch32v10x_adc.h" +#include "ch32v10x_dma.h" +#include "ch32v10x_gpio.h" +#include "ch32v10x_rcc.h" +#include "ch32v10x_tim.h" +#include "ch32v10x_usart.h" +#include "ch32v10x_misc.h" + +#endif diff --git a/ch32v103_hallarray_controller/src/user/ch32v10x_it.c b/ch32v103_hallarray_controller/src/user/ch32v10x_it.c new file mode 100644 index 0000000..dbe234a --- /dev/null +++ b/ch32v103_hallarray_controller/src/user/ch32v10x_it.c @@ -0,0 +1,8 @@ +#include "ch32v10x.h" + +void HardFault_Handler(void) __attribute__((interrupt("WCH-Interrupt-fast"))); + +void HardFault_Handler(void) +{ + while(1); +} diff --git a/ch32v103_hallarray_controller/src/user/main.c b/ch32v103_hallarray_controller/src/user/main.c new file mode 100644 index 0000000..e954285 --- /dev/null +++ b/ch32v103_hallarray_controller/src/user/main.c @@ -0,0 +1,9 @@ +#include "app_main.h" + +int main(void) +{ + NVIC_PriorityGroupConfig(NVIC_PriorityGroup_1); + SystemCoreClockUpdate(); + + app_main(); +} diff --git a/ch32v103_hallarray_controller/src/user/system_ch32v10x.c b/ch32v103_hallarray_controller/src/user/system_ch32v10x.c new file mode 100644 index 0000000..16ca8f9 --- /dev/null +++ b/ch32v103_hallarray_controller/src/user/system_ch32v10x.c @@ -0,0 +1,600 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : system_ch32v10x.c + * Author : WCH + * Version : V1.0.0 + * Date : 2024/06/23 + * Description : CH32V10x Device Peripheral Access Layer System Source File. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#include "ch32v10x.h" + +/* + * Uncomment the line corresponding to the desired System clock (SYSCLK) frequency (after + * reset the HSI is used as SYSCLK source). + * If none of the define below is enabled, the HSI is used as System clock source. + */ +//#define SYSCLK_FREQ_HSE HSE_VALUE +//#define SYSCLK_FREQ_48MHz_HSE 48000000 +//#define SYSCLK_FREQ_56MHz_HSE 56000000 +#define SYSCLK_FREQ_72MHz_HSE 72000000 +//#define SYSCLK_FREQ_HSI HSI_VALUE +//#define SYSCLK_FREQ_48MHz_HSI 48000000 +//#define SYSCLK_FREQ_56MHz_HSI 56000000 +//#define SYSCLK_FREQ_72MHz_HSI 72000000 + +/* Clock Definitions */ +#ifdef SYSCLK_FREQ_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz_HSE +uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSE; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_48MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_48MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_56MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_56MHz_HSI; /* System Clock Frequency (Core Clock) */ +#elif defined SYSCLK_FREQ_72MHz_HSI +uint32_t SystemCoreClock = SYSCLK_FREQ_72MHz_HSI; /* System Clock Frequency (Core Clock) */ +#else +uint32_t SystemCoreClock = HSI_VALUE; /* System Clock Frequency (Core Clock) */ + +#endif + +__I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + +/* ch32v10x_system_private_function_proto_types */ +static void SetSysClock(void); + +#ifdef SYSCLK_FREQ_HSE +static void SetSysClockToHSE( void ); +#elif defined SYSCLK_FREQ_48MHz_HSE +static void SetSysClockTo48_HSE( void ); +#elif defined SYSCLK_FREQ_56MHz_HSE +static void SetSysClockTo56_HSE( void ); +#elif defined SYSCLK_FREQ_72MHz_HSE +static void SetSysClockTo72_HSE( void ); +#elif defined SYSCLK_FREQ_48MHz_HSI +static void SetSysClockTo48_HSI( void ); +#elif defined SYSCLK_FREQ_56MHz_HSI +static void SetSysClockTo56_HSI( void ); +#elif defined SYSCLK_FREQ_72MHz_HSI +static void SetSysClockTo72_HSI( void ); + +#endif + +/********************************************************************* + * @fn SystemInit + * + * @brief Setup the microcontroller system Initialize the Embedded Flash Interface, + * the PLL and update the SystemCoreClock variable. + * + * @return none + */ +void SystemInit(void) +{ + RCC->CTLR |= (uint32_t)0x00000001; + RCC->CFGR0 &= (uint32_t)0xF8FF0000; + RCC->CTLR &= (uint32_t)0xFEF6FFFF; + RCC->CTLR &= (uint32_t)0xFFFBFFFF; + RCC->CFGR0 &= (uint32_t)0xFF80FFFF; + RCC->INTR = 0x009F0000; + SetSysClock(); +} + +/********************************************************************* + * @fn SystemCoreClockUpdate + * + * @brief Update SystemCoreClock variable according to Clock Register Values. + * + * @return none + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllmull = 0, pllsource = 0; + + tmp = RCC->CFGR0 & RCC_SWS; + + switch(tmp) + { + case 0x00: + SystemCoreClock = HSI_VALUE; + break; + case 0x04: + SystemCoreClock = HSE_VALUE; + break; + case 0x08: + pllmull = RCC->CFGR0 & RCC_PLLMULL; + pllsource = RCC->CFGR0 & RCC_PLLSRC; + pllmull = (pllmull >> 18) + 2; + if(pllsource == 0x00) + { + if( EXTEN->EXTEN_CTR & EXTEN_PLL_HSI_PRE ) + { + SystemCoreClock = ( HSI_VALUE ) * pllmull; + } + else + { + SystemCoreClock = ( HSI_VALUE >> 1 ) * pllmull; + } + } + else + { + if((RCC->CFGR0 & RCC_PLLXTPRE) != (uint32_t)RESET) + { + SystemCoreClock = (HSE_VALUE >> 1) * pllmull; + } + else + { + SystemCoreClock = HSE_VALUE * pllmull; + } + } + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + + tmp = AHBPrescTable[((RCC->CFGR0 & RCC_HPRE) >> 4)]; + SystemCoreClock >>= tmp; +} + +/********************************************************************* + * @fn SetSysClock + * + * @brief Configures the System clock frequency, HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClock(void) +{ + //GPIO_IPD_Unused(); +#ifdef SYSCLK_FREQ_HSE + SetSysClockToHSE(); +#elif defined SYSCLK_FREQ_48MHz_HSE + SetSysClockTo48_HSE(); +#elif defined SYSCLK_FREQ_56MHz_HSE + SetSysClockTo56_HSE(); +#elif defined SYSCLK_FREQ_72MHz_HSE + SetSysClockTo72_HSE(); +#elif defined SYSCLK_FREQ_48MHz_HSI + SetSysClockTo48_HSI(); +#elif defined SYSCLK_FREQ_56MHz_HSI + SetSysClockTo56_HSI(); +#elif defined SYSCLK_FREQ_72MHz_HSI + SetSysClockTo72_HSI(); + +#endif + + /* If none of the define above is enabled, the HSI is used as System clock + * source (default after reset) + */ +} + +#ifdef SYSCLK_FREQ_HSE + +/********************************************************************* + * @fn SetSysClockToHSE + * + * @brief Sets HSE as System clock source and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockToHSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if(HSEStatus == (uint32_t)0x01) + { + FLASH->ACTLR |= FLASH_ACTLR_PRFTBE; + /* Flash 0 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_0; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV1; + + /* Select HSE as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_HSE; + + /* Wait till HSE is used as system clock source */ + while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x04) + { + } + } + else + { + /* If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + + +#elif defined SYSCLK_FREQ_48MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo48_HSE + * + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo48_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if(HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACTLR |= FLASH_ACTLR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 6 = 48 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL6); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_56MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo56_HSE + * + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo56_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if(HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACTLR |= FLASH_ACTLR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 7 = 56 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL7); + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_72MHz_HSE + +/********************************************************************* + * @fn SetSysClockTo72_HSE + * + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo72_HSE(void) +{ + __IO uint32_t StartUpCounter = 0, HSEStatus = 0; + + RCC->CTLR |= ((uint32_t)RCC_HSEON); + + /* Wait till HSE is ready and if Time out is reached exit */ + do + { + HSEStatus = RCC->CTLR & RCC_HSERDY; + StartUpCounter++; + } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT)); + + if((RCC->CTLR & RCC_HSERDY) != RESET) + { + HSEStatus = (uint32_t)0x01; + } + else + { + HSEStatus = (uint32_t)0x00; + } + + if(HSEStatus == (uint32_t)0x01) + { + /* Enable Prefetch Buffer */ + FLASH->ACTLR |= FLASH_ACTLR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | + RCC_PLLMULL)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSE | RCC_PLLMULL9); + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } + } + else + { + /* + * If HSE fails to start-up, the application will have wrong clock + * configuration. User can add here some code to deal with this error + */ + } +} + +#elif defined SYSCLK_FREQ_48MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo48_HSI + * + * @brief Sets System clock frequency to 48MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo48_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* Enable Prefetch Buffer */ + FLASH->ACTLR |= FLASH_ACTLR_PRFTBE; + + /* Flash 1 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_1; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 6 = 48 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL6); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + +#elif defined SYSCLK_FREQ_56MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo56_HSI + * + * @brief Sets System clock frequency to 56MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo56_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* Enable Prefetch Buffer */ + FLASH->ACTLR |= FLASH_ACTLR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 7 = 56 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL7); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + +#elif defined SYSCLK_FREQ_72MHz_HSI + +/********************************************************************* + * @fn SetSysClockTo72_HSI + * + * @brief Sets System clock frequency to 72MHz and configure HCLK, PCLK2 and PCLK1 prescalers. + * + * @return none + */ +static void SetSysClockTo72_HSI(void) +{ + EXTEN->EXTEN_CTR |= EXTEN_PLL_HSI_PRE; + + /* Enable Prefetch Buffer */ + FLASH->ACTLR |= FLASH_ACTLR_PRFTBE; + + /* Flash 2 wait state */ + FLASH->ACTLR &= (uint32_t)((uint32_t)~FLASH_ACTLR_LATENCY); + FLASH->ACTLR |= (uint32_t)FLASH_ACTLR_LATENCY_2; + + /* HCLK = SYSCLK */ + RCC->CFGR0 |= (uint32_t)RCC_HPRE_DIV1; + /* PCLK2 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE2_DIV1; + /* PCLK1 = HCLK */ + RCC->CFGR0 |= (uint32_t)RCC_PPRE1_DIV2; + + /* PLL configuration: PLLCLK = HSI * 9 = 72 MHz */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_PLLSRC | RCC_PLLXTPRE | RCC_PLLMULL)); + RCC->CFGR0 |= (uint32_t)(RCC_PLLSRC_HSI_Div2 | RCC_PLLMULL9); + + /* Enable PLL */ + RCC->CTLR |= RCC_PLLON; + /* Wait till PLL is ready */ + while((RCC->CTLR & RCC_PLLRDY) == 0) + { + } + /* Select PLL as system clock source */ + RCC->CFGR0 &= (uint32_t)((uint32_t) ~(RCC_SW)); + RCC->CFGR0 |= (uint32_t)RCC_SW_PLL; + /* Wait till PLL is used as system clock source */ + while((RCC->CFGR0 & (uint32_t)RCC_SWS) != (uint32_t)0x08) + { + } +} + +#endif diff --git a/ch32v103_hallarray_controller/src/user/system_ch32v10x.h b/ch32v103_hallarray_controller/src/user/system_ch32v10x.h new file mode 100644 index 0000000..03652f0 --- /dev/null +++ b/ch32v103_hallarray_controller/src/user/system_ch32v10x.h @@ -0,0 +1,29 @@ +/********************************** (C) COPYRIGHT ******************************* + * File Name : system_ch32v10x.h + * Author : WCH + * Version : V1.0.0 + * Date : 2020/04/30 + * Description : CH32V10x Device Peripheral Access Layer System Header File. +********************************************************************************* +* Copyright (c) 2021 Nanjing Qinheng Microelectronics Co., Ltd. +* Attention: This software (modified or not) and binary are used for +* microcontroller manufactured by Nanjing Qinheng Microelectronics. +*******************************************************************************/ +#ifndef __SYSTEM_CH32V10x_H +#define __SYSTEM_CH32V10x_H + +#ifdef __cplusplus +extern "C" { +#endif + +extern uint32_t SystemCoreClock; /* System Clock Frequency (Core Clock) */ + +/* System_Exported_Functions */ +extern void SystemInit(void); +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /*__CH32V10x_SYSTEM_H */ diff --git a/ch32v103_hallarray_controller/src/user/usb_config.h b/ch32v103_hallarray_controller/src/user/usb_config.h new file mode 100644 index 0000000..653519e --- /dev/null +++ b/ch32v103_hallarray_controller/src/user/usb_config.h @@ -0,0 +1,21 @@ +#ifndef CHERRYUSB_CONFIG_H +#define CHERRYUSB_CONFIG_H + +/* ==================== USB common Configuration =================== */ + +#define CONFIG_USB_PRINTF(...) +#define CONFIG_USB_DBG_LEVEL USB_DBG_INFO + +#define CONFIG_USB_ALIGN_SIZE 4 +#define USB_NOCACHE_RAM_SECTION + +/* ================= USB Device Stack Configuration ================ */ + +#define CONFIG_USBDEV_REQUEST_BUFFER_LEN 256 + +/* ================== USB Device Port Configuration =================*/ + +#define CONFIG_USBDEV_MAX_BUS 1 +#define CONFIG_USBDEV_EP_NUM 8 + +#endif diff --git a/ch32v103_hallarray_controller/src/user/util_delay.c b/ch32v103_hallarray_controller/src/user/util_delay.c new file mode 100644 index 0000000..478b653 --- /dev/null +++ b/ch32v103_hallarray_controller/src/user/util_delay.c @@ -0,0 +1,38 @@ +#include "util_delay.h" + +static uint8_t p_us = 0; +static uint16_t p_ms = 0; + +void delay_init(void) +{ + p_us = SystemCoreClock / 8000000; + p_ms = (uint16_t)p_us * 1000; +} + +void delay_us(uint32_t n_us) +{ + SysTick->CNTL0 = 0; + SysTick->CNTL1 = 0; + SysTick->CNTL2 = 0; + SysTick->CNTL3 = 0; + SysTick->CTLR = 1; + + uint32_t i = (uint32_t)n_us * p_us; + while((*(__IO uint32_t *)0xE000F004) <= i); + + SysTick->CTLR = 0; +} + +void delay_ms(uint32_t n_ms) +{ + SysTick->CNTL0 = 0; + SysTick->CNTL1 = 0; + SysTick->CNTL2 = 0; + SysTick->CNTL3 = 0; + SysTick->CTLR = 1; + + uint32_t i = (uint32_t)n_ms * p_ms; + while((*(__IO uint32_t *)0xE000F004) <= i); + + SysTick->CTLR = 0; +} diff --git a/ch32v103_hallarray_controller/src/user/util_delay.h b/ch32v103_hallarray_controller/src/user/util_delay.h new file mode 100644 index 0000000..f3cfec3 --- /dev/null +++ b/ch32v103_hallarray_controller/src/user/util_delay.h @@ -0,0 +1,10 @@ +#ifndef __UTIL_DELAY_H +#define __UTIL_DELAY_H + +#include "ch32v10x.h" + +void delay_init(void); +void delay_us(uint32_t n); +void delay_ms(uint32_t n); + +#endif