优化工程结构
This commit is contained in:
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bf321079b3
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@ -1,22 +1,47 @@
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set(CMAKE_SYSTEM_NAME Generic)
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set(CMAKE_SYSTEM_PROCESSOR ARM)
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set(CMAKE_SYSTEM_VERSION 1)
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set(CMAKE_SYSTEM_NAME Generic)
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set(CMAKE_SYSTEM_PROCESSOR arm)
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set(CMAKE_CROSSCOMPILING TRUE)
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set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY)
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set(CMAKE_C_COMPILER_FORCED TRUE)
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set(CMAKE_CXX_COMPILER_FORCED TRUE)
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set(CMAKE_C_COMPILER_ID GNU)
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set(CMAKE_CXX_COMPILER_ID GNU)
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set(CROSS_COMPILE_PREFIX arm-none-eabi-)
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# Some default GCC settings
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# arm-none-eabi- must be part of path environment
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set(TOOLCHAIN_PREFIX arm-none-eabi-)
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set(CMAKE_C_FLAGS "-Wall -fdata-sections -ffunction-sections -Wl,--gc-sections")
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set(CMAKE_CXX_FLAGS "${CMAKE_C_FLAGS} -fno-rtti -fno-exceptions -fno-threadsafe-statics")
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set(CMAKE_EXE_LINKER_FLAGS "-Wl,-Map=${CMAKE_PROJECT_NAME}.map,--cref -Wl,--print-memory-usage")
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set(CMAKE_C_COMPILER ${CROSS_COMPILE_PREFIX}gcc)
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set(CMAKE_CXX_COMPILER ${CROSS_COMPILE_PREFIX}g++)
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set(CMAKE_ASM_COMPILER ${CMAKE_C_COMPILER} -x assembler-with-cpp)
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set(CMAKE_OBJCOPY ${CROSS_COMPILE_PREFIX}objcopy)
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set(CMAKE_SIZE ${CROSS_COMPILE_PREFIX}size)
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set(CMAKE_C_COMPILER ${TOOLCHAIN_PREFIX}gcc)
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set(CMAKE_ASM_COMPILER ${CMAKE_C_COMPILER})
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set(CMAKE_CXX_COMPILER ${TOOLCHAIN_PREFIX}g++)
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set(CMAKE_LINKER ${TOOLCHAIN_PREFIX}g++)
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set(CMAKE_OBJCOPY ${TOOLCHAIN_PREFIX}objcopy)
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set(CMAKE_SIZE ${TOOLCHAIN_PREFIX}size)
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set(CMAKE_EXECUTABLE_SUFFIX_ASM ".elf")
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set(CMAKE_EXECUTABLE_SUFFIX_C ".elf")
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set(CMAKE_EXECUTABLE_SUFFIX_CXX ".elf")
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set(CMAKE_EXECUTABLE_SUFFIX_ASM ".elf")
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set(CMAKE_TRY_COMPILE_TARGET_TYPE STATIC_LIBRARY)
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# MCU specific flags
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set(TARGET_FLAGS "-mcpu=cortex-m7 -mthumb -mfpu=fpv5-d16 -mfloat-abi=hard")
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set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} ${TARGET_FLAGS}")
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set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -Wall -fdata-sections -ffunction-sections")
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if(CMAKE_BUILD_TYPE MATCHES Debug)
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set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -O0 -g3")
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endif()
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if(CMAKE_BUILD_TYPE MATCHES Release)
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set(CMAKE_C_FLAGS "${CMAKE_C_FLAGS} -Os -g0")
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endif()
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set(CMAKE_ASM_FLAGS "${CMAKE_C_FLAGS} -x assembler-with-cpp -MMD -MP")
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set(CMAKE_CXX_FLAGS "${CMAKE_C_FLAGS} -fno-rtti -fno-exceptions -fno-threadsafe-statics")
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set(CMAKE_C_LINK_FLAGS "${TARGET_FLAGS}")
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set(CMAKE_C_LINK_FLAGS "${CMAKE_C_LINK_FLAGS} --specs=nano.specs")
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set(CMAKE_C_LINK_FLAGS "${CMAKE_C_LINK_FLAGS} -Wl,-Map=${CMAKE_PROJECT_NAME}.map -Wl,--gc-sections")
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set(CMAKE_C_LINK_FLAGS "${CMAKE_C_LINK_FLAGS} -Wl,--start-group -lc -lm -Wl,--end-group")
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set(CMAKE_C_LINK_FLAGS "${CMAKE_C_LINK_FLAGS} -Wl,--print-memory-usage")
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set(CMAKE_CXX_LINK_FLAGS "${CMAKE_C_LINK_FLAGS} -Wl,--start-group -lstdc++ -lsupc++ -Wl,--end-group")
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@ -1,7 +1,7 @@
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cmake_minimum_required(VERSION 3.15)
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if(NOT CMAKE_TOOLCHAIN_FILE)
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set(CMAKE_TOOLCHAIN_FILE ${CMAKE_SOURCE_DIR}/CMake/gcc-arm-none-eabi.cmake)
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set(CMAKE_TOOLCHAIN_FILE ${CMAKE_SOURCE_DIR}/CMake/gcc-arm-none-eabi.cmake)
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endif()
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if(NOT CMAKE_BUILD_TYPE)
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@ -19,71 +19,62 @@ set(CMAKE_CXX_EXTENSIONS ON)
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set(CMAKE_BINARY_DIR ${CMAKE_SOURCE_DIR}/build)
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set(EXECUTABLE_OUTPUT_PATH ${CMAKE_BINARY_DIR})
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set(TARGET_BUILD_ARCH_OPTIONS
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-mcpu=cortex-m7 -mthumb # cortex-m7 core
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-mfpu=fpv5-d16 -mfloat-abi=hard # enable hardware fpu
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--specs=nano.specs --specs=nosys.specs # use newlib-nano
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-Wl,-wrap,_malloc_r -Wl,-wrap,_free_r -Wl,-wrap,_realloc_r # wrap newlib memory allocator functions
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# 全局包含路径
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include_directories(
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"${CMAKE_CURRENT_LIST_DIR}/Core/Inc"
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"${CMAKE_CURRENT_LIST_DIR}/Drivers/CMSIS/Include"
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"${CMAKE_CURRENT_LIST_DIR}/Drivers/CMSIS/Device/ST/STM32H7xx/Include"
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"${CMAKE_CURRENT_LIST_DIR}/User/utils"
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"${CMAKE_CURRENT_LIST_DIR}/User/ports/lvgl"
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"${CMAKE_CURRENT_LIST_DIR}/User/ports/fatfs"
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)
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set(TARGET_BUILD_DEFINATIONS
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-DUSE_HAL_DRIVER -DSTM32H743xx
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-DLV_CONF_INCLUDE_SIMPLE
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# 全局定义
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add_compile_definitions(
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USE_HAL_DRIVER
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STM32H743xx
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STM32_THREAD_SAFE_STRATEGY=4
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)
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set(LINKER_SCRIPT
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${CMAKE_SOURCE_DIR}/STM32H743IITX_FLASH.ld
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# 全局编译器选项
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add_compile_options(
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-fdiagnostics-color=always
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)
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include_directories(PUBLIC
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"${CMAKE_SOURCE_DIR}/Core/Inc"
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"${CMAKE_SOURCE_DIR}/Drivers/CMSIS/Include"
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"${CMAKE_SOURCE_DIR}/Drivers/CMSIS/Device/ST/STM32H7xx/Include"
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"${CMAKE_SOURCE_DIR}/Drivers/STM32H7xx_HAL_Driver/Inc"
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"${CMAKE_SOURCE_DIR}/Drivers/STM32H7xx_HAL_Driver/Inc/Legacy"
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# 全局连接器选项
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add_link_options(
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-Wl,-wrap,_malloc_r -Wl,-wrap,_free_r -Wl,-wrap,_realloc_r # wrap newlib memory allocator functions
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-T${CMAKE_CURRENT_LIST_DIR}/STM32H743IITX_FLASH.ld
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)
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add_subdirectory(Drivers)
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add_subdirectory(Middlewares/Third_Party)
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add_subdirectory(Middlewares)
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set(TARGET_SOURCE_DIRS
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"${CMAKE_SOURCE_DIR}/Core/Src/*.c"
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"${CMAKE_SOURCE_DIR}/Core/Startup/*.s"
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"${CMAKE_SOURCE_DIR}/User/audio/*.c"
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"${CMAKE_SOURCE_DIR}/User/bsp/*.c"
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"${CMAKE_SOURCE_DIR}/User/ports/*.c"
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"${CMAKE_SOURCE_DIR}/User/tasks/*.c"
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"${CMAKE_SOURCE_DIR}/Core/Src/*.c"
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"${CMAKE_SOURCE_DIR}/Core/Startup/*.s"
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"${CMAKE_SOURCE_DIR}/User/*.c"
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)
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file(GLOB_RECURSE TARGET_SOURCES ${TARGET_SOURCE_DIRS})
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list(REMOVE_ITEM TARGET_SOURCES "${CMAKE_SOURCE_DIR}/Core/Src/sysmem.c")
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add_executable(${CMAKE_PROJECT_NAME} ${TARGET_SOURCES})
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target_include_directories(${CMAKE_PROJECT_NAME} PRIVATE
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"${CMAKE_SOURCE_DIR}/Core/ThreadSafe"
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"${CMAKE_CURRENT_LIST_DIR}/User/audio"
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"${CMAKE_CURRENT_LIST_DIR}/User/bsp"
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"${CMAKE_CURRENT_LIST_DIR}/User/ports/lvgl"
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"${CMAKE_CURRENT_LIST_DIR}/User/ports/heap"
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"${CMAKE_CURRENT_LIST_DIR}/User/tasks"
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"${CMAKE_SOURCE_DIR}/Core/ThreadSafe"
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"${CMAKE_CURRENT_LIST_DIR}/User/audio"
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"${CMAKE_CURRENT_LIST_DIR}/User/bsp"
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"${CMAKE_CURRENT_LIST_DIR}/User/ports/fatfs"
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"${CMAKE_CURRENT_LIST_DIR}/User/ports/lvgl"
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"${CMAKE_CURRENT_LIST_DIR}/User/tasks"
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)
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target_link_libraries(${CMAKE_PROJECT_NAME} PRIVATE
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hal_driver
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# lvgl
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minimp3
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tlsf
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freertos
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easylogger
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fatfs
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)
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target_compile_options(${CMAKE_PROJECT_NAME} PRIVATE
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${TARGET_BUILD_ARCH_OPTIONS}
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${TARGET_BUILD_DEFINATIONS}
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)
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target_link_options(${CMAKE_PROJECT_NAME} PRIVATE
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${TARGET_BUILD_ARCH_OPTIONS}
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-T${LINKER_SCRIPT}
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hal_driver
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lvgl
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lvgl_demos
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minimp3
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tlsf
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freertos
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easylogger
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fatfs
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)
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@ -59,13 +59,13 @@
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/* #define HAL_JPEG_MODULE_ENABLED */
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/* #define HAL_OPAMP_MODULE_ENABLED */
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/* #define HAL_OSPI_MODULE_ENABLED */
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/* #define HAL_OSPI_MODULE_ENABLED */
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/* #define HAL_XSPI_MODULE_ENABLED */
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/* #define HAL_I2S_MODULE_ENABLED */
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/* #define HAL_SMBUS_MODULE_ENABLED */
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/* #define HAL_IWDG_MODULE_ENABLED */
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/* #define HAL_LPTIM_MODULE_ENABLED */
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/* #define HAL_LTDC_MODULE_ENABLED */
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/* #define HAL_QSPI_MODULE_ENABLED */
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/* #define HAL_XSPI_MODULE_ENABLED */
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/* #define HAL_RAMECC_MODULE_ENABLED */
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/* #define HAL_RNG_MODULE_ENABLED */
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/* #define HAL_RTC_MODULE_ENABLED */
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@ -90,10 +90,12 @@ void task_elog_entry(void const * argument);
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*/
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int main(void)
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{
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/* USER CODE BEGIN 1 */
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/* USER CODE END 1 */
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/* Enable the CPU Cache */
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/* Enable the CPU Cache */
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/* Enable I-Cache---------------------------------------------------------*/
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SCB_EnableICache();
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@ -159,6 +161,7 @@ int main(void)
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osKernelStart();
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/* We should never get here as control is now taken by the scheduler */
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/* Infinite loop */
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/* USER CODE BEGIN WHILE */
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while (1)
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@ -20,7 +20,6 @@
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/* Includes ------------------------------------------------------------------*/
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#include "main.h"
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/* USER CODE BEGIN Includes */
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/* USER CODE END Includes */
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@ -66,6 +65,7 @@ extern DMA_HandleTypeDef hdma_usart1_tx;
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*/
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void HAL_MspInit(void)
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{
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/* USER CODE BEGIN MspInit 0 */
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/* USER CODE END MspInit 0 */
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@ -20,6 +20,8 @@
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******************************************************************************
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*/
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#if 0
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/* Includes */
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#include <errno.h>
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#include <stdint.h>
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@ -77,3 +79,5 @@ void *_sbrk(ptrdiff_t incr)
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return (void *)prev_heap_end;
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}
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#endif
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@ -19,7 +19,7 @@
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2023 STMicroelectronics.
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* Copyright (c) 2024 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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@ -48,7 +48,7 @@
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2023 STMicroelectronics.
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* Copyright (c) 2024 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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@ -213,7 +213,7 @@ typedef enum
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/**
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* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
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*/
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#define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
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#define __CM7_REV 0x0101U /*!< Cortex-M7 revision r1p1 */
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#define __MPU_PRESENT 1U /*!< CM7 provides an MPU */
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#define __NVIC_PRIO_BITS 4U /*!< CM7 uses 4 Bits for the Priority Levels */
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#define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */
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@ -228,7 +228,6 @@ typedef enum
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#include "system_stm32h7xx.h"
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#include <stdint.h>
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@ -11464,7 +11463,7 @@ typedef struct
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#define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
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#define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
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#define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
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#define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
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#define FMC_SDCMR_MODE_2 (0x4UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000004 */
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#define FMC_SDCMR_CTB2_Pos (3U)
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#define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
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@ -13211,7 +13210,7 @@ typedef struct
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/******************** Bit definition for SR register ********************/
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#define JPEG_SR_IFTF_Pos (1U)
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#define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */
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#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */
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#define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is below its threshold flag */
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#define JPEG_SR_IFNFF_Pos (2U)
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#define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */
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#define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */
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@ -21308,7 +21307,7 @@ typedef struct
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#define HRTIM_MCR_DACSYNC_Pos (25U)
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#define HRTIM_MCR_DACSYNC_Msk (0x3UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x06000000 */
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#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC sychronization mask */
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#define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC synchronization mask */
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#define HRTIM_MCR_DACSYNC_0 (0x1UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x02000000 */
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#define HRTIM_MCR_DACSYNC_1 (0x2UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x04000000 */
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@ -21517,7 +21516,7 @@ typedef struct
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#define HRTIM_TIMCR_DACSYNC_Pos (25U)
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#define HRTIM_TIMCR_DACSYNC_Msk (0x3UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x06000000 */
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#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC sychronization mask */
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#define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC synchronization mask */
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#define HRTIM_TIMCR_DACSYNC_0 (0x1UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x02000000 */
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#define HRTIM_TIMCR_DACSYNC_1 (0x2UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x04000000 */
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#define HRTIM_TIMCR_PREEN_Pos (27U)
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@ -24292,6 +24291,9 @@ typedef struct
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#define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
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#define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
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#define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
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||||
#define USB_OTG_GOTGCTL_CURMOD_Pos (21U)
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#define USB_OTG_GOTGCTL_CURMOD_Msk (0x1UL << USB_OTG_GOTGCTL_CURMOD_Pos) /*!< 0x00200000 */
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||||
#define USB_OTG_GOTGCTL_CURMOD USB_OTG_GOTGCTL_CURMOD_Msk /*!< Current mode of operation */
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||||
/******************** Bit definition forUSB_OTG_HCFG register ********************/
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||||
@ -24317,7 +24319,7 @@ typedef struct
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||||
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||||
#define USB_OTG_DCFG_DAD_Pos (4U)
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#define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
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||||
#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
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#define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
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#define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
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#define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
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#define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
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@ -24328,13 +24330,21 @@ typedef struct
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||||
#define USB_OTG_DCFG_PFIVL_Pos (11U)
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#define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
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||||
#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
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#define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
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||||
#define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
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#define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
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||||
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||||
#define USB_OTG_DCFG_XCVRDLY_Pos (14U)
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||||
#define USB_OTG_DCFG_XCVRDLY_Msk (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos) /*!< 0x00004000 */
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#define USB_OTG_DCFG_XCVRDLY USB_OTG_DCFG_XCVRDLY_Msk /*!< Transceiver delay */
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#define USB_OTG_DCFG_ERRATIM_Pos (15U)
|
||||
#define USB_OTG_DCFG_ERRATIM_Msk (0x1UL << USB_OTG_DCFG_ERRATIM_Pos) /*!< 0x00008000 */
|
||||
#define USB_OTG_DCFG_ERRATIM USB_OTG_DCFG_ERRATIM_Msk /*!< Erratic error interrupt mask */
|
||||
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
|
||||
#define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
|
||||
#define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
|
||||
|
||||
@ -24404,6 +24414,12 @@ typedef struct
|
||||
#define USB_OTG_DCTL_POPRGDNE_Pos (11U)
|
||||
#define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
|
||||
#define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Pos (17U)
|
||||
#define USB_OTG_DCTL_ENCONTONBNA_Msk (0x1UL << USB_OTG_DCTL_ENCONTONBNA_Pos) /*!< 0x00020000 */
|
||||
#define USB_OTG_DCTL_ENCONTONBNA USB_OTG_DCTL_ENCONTONBNA_Msk /*!< Enable continue on BNA */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Pos (18U)
|
||||
#define USB_OTG_DCTL_DSBESLRJCT_Msk (0x1UL << USB_OTG_DCTL_DSBESLRJCT_Pos) /*!< 0x00040000 */
|
||||
#define USB_OTG_DCTL_DSBESLRJCT USB_OTG_DCTL_DSBESLRJCT_Msk /*!< Deep sleep BESL reject */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_HFIR register ********************/
|
||||
#define USB_OTG_HFIR_FRIVL_Pos (0U)
|
||||
@ -24521,7 +24537,7 @@ typedef struct
|
||||
#define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
|
||||
#define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
|
||||
#define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet for debug propose only; must be kept at reset value */
|
||||
|
||||
/******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
|
||||
#define USB_OTG_GRSTCTL_CSRST_Pos (0U)
|
||||
|
||||
@ -102,11 +102,11 @@
|
||||
#endif /* USE_HAL_DRIVER */
|
||||
|
||||
/**
|
||||
* @brief CMSIS Device version number V1.10.3
|
||||
* @brief CMSIS Device version number V1.10.4
|
||||
*/
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_MAIN (0x01) /*!< [31:24] main version */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 (0x0A) /*!< [23:16] sub1 version */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x03) /*!< [15:8] sub2 version */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_SUB2 (0x04) /*!< [15:8] sub2 version */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION_RC (0x00) /*!< [7:0] release candidate */
|
||||
#define __STM32H7xx_CMSIS_DEVICE_VERSION ((__STM32H7xx_CMSIS_DEVICE_VERSION_MAIN << 24)\
|
||||
|(__STM32H7xx_CMSIS_DEVICE_VERSION_SUB1 << 16)\
|
||||
|
||||
@ -6,11 +6,7 @@ file(GLOB SOURCE_FILES ${SOURCE_DIRS})
|
||||
|
||||
add_library(hal_driver ${SOURCE_FILES})
|
||||
|
||||
target_compile_options(hal_driver PUBLIC
|
||||
${TARGET_BUILD_ARCH_OPTIONS}
|
||||
${TARGET_BUILD_DEFINATIONS}
|
||||
)
|
||||
|
||||
target_link_options(hal_driver PUBLIC
|
||||
${TARGET_BUILD_ARCH_OPTIONS}
|
||||
target_include_directories(hal_driver PUBLIC
|
||||
"${CMAKE_CURRENT_LIST_DIR}/STM32H7xx_HAL_Driver/Inc"
|
||||
"${CMAKE_CURRENT_LIST_DIR}/STM32H7xx_HAL_Driver/Inc/Legacy"
|
||||
)
|
||||
|
||||
@ -37,16 +37,12 @@ extern "C" {
|
||||
#define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF
|
||||
#define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR
|
||||
#define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR
|
||||
#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1)
|
||||
#if defined(STM32H7) || defined(STM32MP1)
|
||||
#define CRYP_DATATYPE_32B CRYP_NO_SWAP
|
||||
#define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP
|
||||
#define CRYP_DATATYPE_8B CRYP_BYTE_SWAP
|
||||
#define CRYP_DATATYPE_1B CRYP_BIT_SWAP
|
||||
#if defined(STM32U5)
|
||||
#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF
|
||||
#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF
|
||||
#endif /* STM32U5 */
|
||||
#endif /* STM32U5 || STM32H7 || STM32MP1 */
|
||||
#endif /* STM32H7 || STM32MP1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -113,6 +109,9 @@ extern "C" {
|
||||
#define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5
|
||||
#endif /* STM32U5 */
|
||||
|
||||
#if defined(STM32H5)
|
||||
#define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE
|
||||
#endif /* STM32H5 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -140,7 +139,8 @@ extern "C" {
|
||||
#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
|
||||
#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
|
||||
#if defined(STM32L0)
|
||||
#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
|
||||
#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM
|
||||
input 1 for COMP1, LPTIM input 2 for COMP2 */
|
||||
#endif
|
||||
#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
|
||||
#if defined(STM32F373xC) || defined(STM32F378xx)
|
||||
@ -239,10 +239,12 @@ extern "C" {
|
||||
/** @defgroup CRC_Aliases CRC API aliases
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32C0)
|
||||
#if defined(STM32H5) || defined(STM32C0)
|
||||
#else
|
||||
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */
|
||||
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */
|
||||
#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for
|
||||
inter STM32 series compatibility */
|
||||
#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for
|
||||
inter STM32 series compatibility */
|
||||
#endif
|
||||
/**
|
||||
* @}
|
||||
@ -273,7 +275,7 @@ extern "C" {
|
||||
#define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE
|
||||
#define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE
|
||||
|
||||
#if defined(STM32G4) || defined(STM32L5) || defined(STM32H7) || defined (STM32U5)
|
||||
#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5)
|
||||
#define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL
|
||||
#define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL
|
||||
#endif
|
||||
@ -285,7 +287,13 @@ extern "C" {
|
||||
#define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1
|
||||
#endif
|
||||
|
||||
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4)
|
||||
#if defined(STM32H5)
|
||||
#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1
|
||||
#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1
|
||||
#endif
|
||||
|
||||
#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \
|
||||
defined(STM32F4) || defined(STM32G4)
|
||||
#define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID
|
||||
#define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID
|
||||
#endif
|
||||
@ -350,7 +358,8 @@ extern "C" {
|
||||
#define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
|
||||
#define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
|
||||
|
||||
#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx)
|
||||
#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \
|
||||
defined(STM32L4S7xx) || defined(STM32L4S9xx)
|
||||
#define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI
|
||||
#endif
|
||||
|
||||
@ -539,6 +548,16 @@ extern "C" {
|
||||
#define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE
|
||||
#define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE
|
||||
#endif /* STM32U5 */
|
||||
#if defined(STM32U0)
|
||||
#define OB_USER_nRST_STOP OB_USER_NRST_STOP
|
||||
#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY
|
||||
#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW
|
||||
#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL
|
||||
#define OB_USER_nBOOT0 OB_USER_NBOOT0
|
||||
#define OB_USER_nBOOT1 OB_USER_NBOOT1
|
||||
#define OB_nBOOT0_RESET OB_NBOOT0_RESET
|
||||
#define OB_nBOOT0_SET OB_NBOOT0_SET
|
||||
#endif /* STM32U0 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
@ -582,6 +601,106 @@ extern "C" {
|
||||
#define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD
|
||||
#endif /* STM32G4 */
|
||||
|
||||
#if defined(STM32H5)
|
||||
#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC
|
||||
#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC
|
||||
#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC
|
||||
#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC
|
||||
#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC
|
||||
#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC
|
||||
|
||||
#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC
|
||||
#define SYSCFG_BREAK_PVD SBS_BREAK_PVD
|
||||
#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC
|
||||
#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP
|
||||
|
||||
#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0
|
||||
#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1
|
||||
#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2
|
||||
#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3
|
||||
|
||||
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE
|
||||
#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE
|
||||
|
||||
#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6
|
||||
#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7
|
||||
#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8
|
||||
#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9
|
||||
|
||||
#define SYSCFG_ETH_MII SBS_ETH_MII
|
||||
#define SYSCFG_ETH_RMII SBS_ETH_RMII
|
||||
#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG
|
||||
|
||||
#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE
|
||||
#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR
|
||||
#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG
|
||||
|
||||
#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG
|
||||
|
||||
#define SYSCFG_MPU_NSEC SBS_MPU_NSEC
|
||||
#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#define SYSCFG_SAU SBS_SAU
|
||||
#define SYSCFG_MPU_SEC SBS_MPU_SEC
|
||||
#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC
|
||||
#define SYSCFG_LOCK_ALL SBS_LOCK_ALL
|
||||
#else
|
||||
#define SYSCFG_LOCK_ALL SBS_LOCK_ALL
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
|
||||
#define SYSCFG_CLK SBS_CLK
|
||||
#define SYSCFG_CLASSB SBS_CLASSB
|
||||
#define SYSCFG_FPU SBS_FPU
|
||||
#define SYSCFG_ALL SBS_ALL
|
||||
|
||||
#define SYSCFG_SEC SBS_SEC
|
||||
#define SYSCFG_NSEC SBS_NSEC
|
||||
|
||||
#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE
|
||||
#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE
|
||||
|
||||
#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK
|
||||
#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK
|
||||
#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK
|
||||
#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK
|
||||
|
||||
#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE
|
||||
#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE
|
||||
|
||||
#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS
|
||||
#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS
|
||||
|
||||
#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT
|
||||
#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG
|
||||
#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE
|
||||
#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE
|
||||
#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING
|
||||
#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS
|
||||
#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES
|
||||
#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES
|
||||
#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS
|
||||
|
||||
#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig
|
||||
#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig
|
||||
#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig
|
||||
#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF
|
||||
#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF
|
||||
|
||||
#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster
|
||||
#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster
|
||||
#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect
|
||||
|
||||
#define HAL_SYSCFG_Lock HAL_SBS_Lock
|
||||
#define HAL_SYSCFG_GetLock HAL_SBS_GetLock
|
||||
|
||||
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||
#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes
|
||||
#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes
|
||||
#endif /* __ARM_FEATURE_CMSE */
|
||||
|
||||
#endif /* STM32H5 */
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -649,14 +768,16 @@ extern "C" {
|
||||
#define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS
|
||||
#define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS
|
||||
#define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS
|
||||
#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */
|
||||
#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \
|
||||
STM32H757xx */
|
||||
#endif /* STM32H7 */
|
||||
|
||||
#define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1
|
||||
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
|
||||
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
|
||||
|
||||
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
|
||||
#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \
|
||||
defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5)
|
||||
#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
|
||||
#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
|
||||
#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
|
||||
@ -678,8 +799,10 @@ extern "C" {
|
||||
|
||||
#define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1
|
||||
|
||||
#if defined(STM32U5)
|
||||
#if defined(STM32U5) || defined(STM32H5)
|
||||
#define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ
|
||||
#endif /* STM32U5 || STM32H5 */
|
||||
#if defined(STM32U5)
|
||||
#define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP
|
||||
#define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1
|
||||
#endif /* STM32U5 */
|
||||
@ -694,7 +817,23 @@ extern "C" {
|
||||
#define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI
|
||||
#define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB
|
||||
#endif /* STM32U5 */
|
||||
|
||||
#if defined(STM32H5)
|
||||
#define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1
|
||||
#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC
|
||||
#define GTZC_PERIPH_USBFS GTZC_PERIPH_USB
|
||||
#endif /* STM32H5 */
|
||||
#if defined(STM32H5) || defined(STM32U5)
|
||||
#define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX
|
||||
#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX
|
||||
#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED
|
||||
#define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED
|
||||
#define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC
|
||||
#define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC
|
||||
#define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV
|
||||
#define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV
|
||||
#define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF
|
||||
#define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON
|
||||
#endif /* STM32H5 || STM32U5 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -875,7 +1014,8 @@ extern "C" {
|
||||
#define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE
|
||||
#define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE
|
||||
#define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE
|
||||
#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7)
|
||||
#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \
|
||||
defined(STM32L1) || defined(STM32F7)
|
||||
#define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX
|
||||
#define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX
|
||||
#define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX
|
||||
@ -1109,6 +1249,26 @@ extern "C" {
|
||||
#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
|
||||
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
|
||||
|
||||
#if defined(STM32H5) || defined(STM32H7RS)
|
||||
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
|
||||
#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM
|
||||
#endif /* STM32H5 || STM32H7RS */
|
||||
|
||||
#if defined(STM32WBA)
|
||||
#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE
|
||||
#define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2
|
||||
#define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK
|
||||
#define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE
|
||||
#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH
|
||||
#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM
|
||||
#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL
|
||||
#endif /* STM32WBA */
|
||||
|
||||
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
|
||||
#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE
|
||||
#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL
|
||||
#endif /* STM32H5 || STM32WBA || STM32H7RS */
|
||||
|
||||
#if defined(STM32F7)
|
||||
#define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK
|
||||
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK
|
||||
@ -1119,12 +1279,12 @@ extern "C" {
|
||||
#define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT
|
||||
#endif /* STM32H7 */
|
||||
|
||||
#if defined(STM32F7) || defined(STM32H7)
|
||||
#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0)
|
||||
#define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1
|
||||
#define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2
|
||||
#define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3
|
||||
#define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP
|
||||
#endif /* STM32F7 || STM32H7 */
|
||||
#endif /* STM32F7 || STM32H7 || STM32L0 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
@ -1291,7 +1451,7 @@ extern "C" {
|
||||
#define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2
|
||||
#endif
|
||||
|
||||
#if defined(STM32U5) || defined(STM32MP2)
|
||||
#if defined(STM32U5)
|
||||
#define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS
|
||||
#define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK
|
||||
#endif
|
||||
@ -1404,30 +1564,40 @@ extern "C" {
|
||||
#define ETH_MMCRFAECR 0x00000198U
|
||||
#define ETH_MMCRGUFCR 0x000001C4U
|
||||
|
||||
#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
|
||||
#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
|
||||
#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
|
||||
#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
|
||||
#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
|
||||
#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
|
||||
#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
|
||||
#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */
|
||||
#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
|
||||
#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
|
||||
#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
|
||||
#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */
|
||||
#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to
|
||||
the MAC transmitter) */
|
||||
#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from
|
||||
MAC transmitter */
|
||||
#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus
|
||||
or flushing the TxFIFO */
|
||||
#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status
|
||||
of previous frame or IFG/backoff period to be over */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and
|
||||
transmitting a Pause control frame (in full duplex mode) */
|
||||
#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input
|
||||
frame for transmission */
|
||||
#define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */
|
||||
#define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */
|
||||
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
|
||||
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
|
||||
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control
|
||||
de-activate threshold */
|
||||
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control
|
||||
activate threshold */
|
||||
#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
|
||||
#if defined(STM32F1)
|
||||
#else
|
||||
#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
|
||||
#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
|
||||
#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
|
||||
#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status
|
||||
(or time-stamp) */
|
||||
#endif
|
||||
#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
|
||||
#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and
|
||||
status */
|
||||
#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
|
||||
#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
|
||||
#define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */
|
||||
@ -1435,6 +1605,8 @@ extern "C" {
|
||||
#define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */
|
||||
#define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */
|
||||
|
||||
#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -1598,7 +1770,8 @@ extern "C" {
|
||||
#define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode
|
||||
#define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode
|
||||
#define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\
|
||||
)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
|
||||
)==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \
|
||||
HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph))
|
||||
#define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect
|
||||
#define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT())
|
||||
#if defined(STM32L0)
|
||||
@ -1607,8 +1780,10 @@ extern "C" {
|
||||
#endif
|
||||
#define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT())
|
||||
#define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\
|
||||
)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor())
|
||||
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
|
||||
)==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \
|
||||
HAL_ADCEx_DisableVREFINTTempSensor())
|
||||
#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \
|
||||
defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ)
|
||||
#define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode
|
||||
#define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode
|
||||
#define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode
|
||||
@ -1642,16 +1817,21 @@ extern "C" {
|
||||
#define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter
|
||||
#define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter
|
||||
|
||||
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\
|
||||
)==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
|
||||
#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \
|
||||
HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \
|
||||
HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus))
|
||||
|
||||
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
|
||||
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \
|
||||
defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \
|
||||
defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1)
|
||||
#define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT
|
||||
#define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT
|
||||
#define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT
|
||||
#define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT
|
||||
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */
|
||||
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
|
||||
#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 ||
|
||||
STM32L4 || STM32L5 || STM32G4 || STM32L1 */
|
||||
#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \
|
||||
defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1)
|
||||
#define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA
|
||||
#define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA
|
||||
#define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA
|
||||
@ -1776,6 +1956,17 @@ extern "C" {
|
||||
#define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP
|
||||
#define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP
|
||||
|
||||
#define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP
|
||||
#define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP
|
||||
#define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP
|
||||
#define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP
|
||||
#define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP
|
||||
#define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP
|
||||
#define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP
|
||||
#define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP
|
||||
#define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP
|
||||
|
||||
|
||||
#define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP
|
||||
#define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP
|
||||
#define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP
|
||||
@ -1784,6 +1975,8 @@ extern "C" {
|
||||
#define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP
|
||||
#define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP
|
||||
#define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP
|
||||
#define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP
|
||||
|
||||
|
||||
#define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY
|
||||
#define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY
|
||||
@ -1794,6 +1987,7 @@ extern "C" {
|
||||
#define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN
|
||||
#define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN
|
||||
#define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN
|
||||
#define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN
|
||||
|
||||
#define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK
|
||||
#endif
|
||||
@ -1802,6 +1996,20 @@ extern "C" {
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS)
|
||||
#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey
|
||||
#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock
|
||||
#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock
|
||||
#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets
|
||||
#endif /* STM32H5 || STM32WBA || STM32H7RS */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
@ -1827,7 +2035,8 @@ extern "C" {
|
||||
#define HAL_TIM_DMAError TIM_DMAError
|
||||
#define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt
|
||||
#define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt
|
||||
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
|
||||
#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \
|
||||
defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4)
|
||||
#define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro
|
||||
#define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT
|
||||
#define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback
|
||||
@ -2084,7 +2293,8 @@ extern "C" {
|
||||
#define COMP_STOP __HAL_COMP_DISABLE
|
||||
#define COMP_LOCK __HAL_COMP_LOCK
|
||||
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
|
||||
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \
|
||||
defined(STM32F334x8) || defined(STM32F328xx)
|
||||
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
|
||||
__HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE())
|
||||
@ -2109,8 +2319,8 @@ extern "C" {
|
||||
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
|
||||
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
|
||||
# endif
|
||||
# if defined(STM32F302xE) || defined(STM32F302xC)
|
||||
#endif
|
||||
#if defined(STM32F302xE) || defined(STM32F302xC)
|
||||
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
|
||||
@ -2143,8 +2353,8 @@ extern "C" {
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \
|
||||
__HAL_COMP_COMP6_EXTI_CLEAR_FLAG())
|
||||
# endif
|
||||
# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
|
||||
#endif
|
||||
#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx)
|
||||
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
|
||||
((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \
|
||||
@ -2201,8 +2411,8 @@ extern "C" {
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \
|
||||
((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \
|
||||
__HAL_COMP_COMP7_EXTI_CLEAR_FLAG())
|
||||
# endif
|
||||
# if defined(STM32F373xC) ||defined(STM32F378xx)
|
||||
#endif
|
||||
#if defined(STM32F373xC) ||defined(STM32F378xx)
|
||||
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
|
||||
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
|
||||
#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \
|
||||
@ -2219,7 +2429,7 @@ extern "C" {
|
||||
__HAL_COMP_COMP2_EXTI_GET_FLAG())
|
||||
#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \
|
||||
__HAL_COMP_COMP2_EXTI_CLEAR_FLAG())
|
||||
# endif
|
||||
#endif
|
||||
#else
|
||||
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \
|
||||
__HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE())
|
||||
@ -2256,8 +2466,10 @@ extern "C" {
|
||||
/** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
|
||||
#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */
|
||||
#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is
|
||||
done into HAL_COMP_Init() */
|
||||
#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is
|
||||
done into HAL_COMP_Init() */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -2416,7 +2628,9 @@ extern "C" {
|
||||
#define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine
|
||||
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig
|
||||
#define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig
|
||||
#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0)
|
||||
#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \
|
||||
__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \
|
||||
} while(0)
|
||||
#define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT
|
||||
#define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT
|
||||
#define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE
|
||||
@ -2425,8 +2639,12 @@ extern "C" {
|
||||
#define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
|
||||
#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE
|
||||
#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE
|
||||
#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0)
|
||||
#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0)
|
||||
#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \
|
||||
HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \
|
||||
} while(0)
|
||||
#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \
|
||||
HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \
|
||||
} while(0)
|
||||
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention
|
||||
#define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention
|
||||
#define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2
|
||||
@ -2462,8 +2680,8 @@ extern "C" {
|
||||
#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
|
||||
|
||||
#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
|
||||
#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\
|
||||
)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
|
||||
#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \
|
||||
HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
|
||||
|
||||
#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
|
||||
#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
|
||||
@ -3436,7 +3654,12 @@ extern "C" {
|
||||
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
|
||||
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
|
||||
|
||||
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0)
|
||||
#if defined(STM32U0)
|
||||
#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK
|
||||
#endif
|
||||
|
||||
#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \
|
||||
defined(STM32WL) || defined(STM32C0) || defined(STM32H7RS) || defined(STM32U0)
|
||||
#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
|
||||
#else
|
||||
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
|
||||
@ -3538,8 +3761,10 @@ extern "C" {
|
||||
#define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE
|
||||
#define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2
|
||||
#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
|
||||
#if !defined(STM32U0)
|
||||
#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
|
||||
#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
|
||||
#endif
|
||||
|
||||
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
|
||||
#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
|
||||
@ -3581,6 +3806,92 @@ extern "C" {
|
||||
#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
|
||||
#endif /* STM32U5 */
|
||||
|
||||
#if defined(STM32H5)
|
||||
#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE
|
||||
#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE
|
||||
#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG
|
||||
#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE
|
||||
|
||||
#define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE
|
||||
#define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI
|
||||
#define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI
|
||||
#define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE
|
||||
#define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0
|
||||
#define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1
|
||||
#define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2
|
||||
#define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3
|
||||
#define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE
|
||||
#define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM
|
||||
|
||||
#define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE
|
||||
#define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE
|
||||
#define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE
|
||||
#define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE
|
||||
#define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE
|
||||
#define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE
|
||||
#define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE
|
||||
#define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE
|
||||
#define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE
|
||||
#define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE
|
||||
|
||||
#define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE
|
||||
#define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE
|
||||
#define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE
|
||||
#define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE
|
||||
#define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG
|
||||
#define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG
|
||||
#define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG
|
||||
#define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG
|
||||
#define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE
|
||||
#define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE
|
||||
#define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE
|
||||
#define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE
|
||||
#define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE
|
||||
#define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG
|
||||
|
||||
#define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE
|
||||
#define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE
|
||||
#define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE
|
||||
#define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE
|
||||
#define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG
|
||||
#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG
|
||||
|
||||
#define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE
|
||||
#define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE
|
||||
#define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE
|
||||
#define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE
|
||||
#define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG
|
||||
#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG
|
||||
|
||||
#define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0
|
||||
#define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1
|
||||
#define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2
|
||||
#define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3
|
||||
|
||||
#define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE
|
||||
#define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM
|
||||
|
||||
#define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE
|
||||
#define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI
|
||||
#define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI
|
||||
#define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE
|
||||
|
||||
#define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0
|
||||
#define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1
|
||||
#define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2
|
||||
#define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3
|
||||
|
||||
#define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE
|
||||
#define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM
|
||||
|
||||
#define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE
|
||||
#define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI
|
||||
#define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI
|
||||
#define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE
|
||||
|
||||
|
||||
#endif /* STM32H5 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -3597,9 +3908,9 @@ extern "C" {
|
||||
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
|
||||
* @{
|
||||
*/
|
||||
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| \
|
||||
defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
|
||||
defined (STM32C0)
|
||||
#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \
|
||||
defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \
|
||||
defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32H7RS) || defined (STM32U0)
|
||||
#else
|
||||
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
|
||||
#endif
|
||||
@ -3634,6 +3945,13 @@ extern "C" {
|
||||
__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT()))
|
||||
#endif /* STM32F1 */
|
||||
|
||||
#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \
|
||||
defined (STM32H7) || \
|
||||
defined (STM32L0) || defined (STM32L1) || \
|
||||
defined (STM32WB)
|
||||
#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG
|
||||
#endif
|
||||
|
||||
#define IS_ALARM IS_RTC_ALARM
|
||||
#define IS_ALARM_MASK IS_RTC_ALARM_MASK
|
||||
#define IS_TAMPER IS_RTC_TAMPER
|
||||
@ -3652,6 +3970,11 @@ extern "C" {
|
||||
#define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE
|
||||
#define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE
|
||||
|
||||
#if defined (STM32H5)
|
||||
#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE
|
||||
#define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE
|
||||
#endif /* STM32H5 */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -3910,6 +4233,9 @@ extern "C" {
|
||||
#define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE
|
||||
|
||||
#define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1
|
||||
|
||||
#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1
|
||||
#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@ -307,6 +307,8 @@ uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
|
||||
#if (__MPU_PRESENT == 1)
|
||||
void HAL_MPU_Enable(uint32_t MPU_Control);
|
||||
void HAL_MPU_Disable(void);
|
||||
void HAL_MPU_EnableRegion(uint32_t RegionNumber);
|
||||
void HAL_MPU_DisableRegion(uint32_t RegionNumber);
|
||||
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init);
|
||||
#endif /* __MPU_PRESENT */
|
||||
uint32_t HAL_NVIC_GetPriorityGrouping(void);
|
||||
|
||||
@ -66,7 +66,9 @@ typedef enum
|
||||
(__DMA_HANDLE__).Parent = (__HANDLE__); \
|
||||
} while(0)
|
||||
|
||||
#define UNUSED(x) ((void)(x))
|
||||
#if !defined(UNUSED)
|
||||
#define UNUSED(x) ((void)(x)) /* To avoid gcc/g++ warnings */
|
||||
#endif /* UNUSED */
|
||||
|
||||
/** @brief Reset the Handle's State field.
|
||||
* @param __HANDLE__: specifies the Peripheral Handle.
|
||||
|
||||
@ -176,6 +176,20 @@ typedef struct
|
||||
|
||||
} FLASH_CRCInitTypeDef;
|
||||
|
||||
#if (USE_FLASH_ECC == 1U)
|
||||
/**
|
||||
* @brief ECC Info Structure definition
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t Area; /*!< Area from which an ECC was detected.
|
||||
This parameter can be a value of @ref FLASHEx_ECC_Area */
|
||||
|
||||
uint32_t Address; /*!< ECC error address */
|
||||
|
||||
} FLASH_EccInfoTypeDef;
|
||||
#endif /* USE_FLASH_ECC */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -216,6 +230,18 @@ typedef struct
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if (USE_FLASH_ECC == 1U)
|
||||
/** @defgroup FLASH_ECC_Area FLASH ECC Area
|
||||
* @brief FLASH ECC Area
|
||||
* @{
|
||||
*/
|
||||
#define FLASH_ECC_AREA_USER_BANK1 0x00000000U /*!< FLASH bank 1 area */
|
||||
#define FLASH_ECC_AREA_USER_BANK2 0x00000001U /*!< FLASH bank 2 area */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_FLASH_ECC */
|
||||
|
||||
/** @defgroup FLASHEx_Option_Type FLASH Option Type
|
||||
* @{
|
||||
*/
|
||||
@ -837,6 +863,38 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if (USE_FLASH_ECC == 1U)
|
||||
/** @addtogroup FLASHEx_Exported_Functions_Group3
|
||||
* @{
|
||||
*/
|
||||
void HAL_FLASHEx_EnableEccCorrectionInterrupt(void);
|
||||
void HAL_FLASHEx_DisableEccCorrectionInterrupt(void);
|
||||
void HAL_FLASHEx_EnableEccCorrectionInterrupt_Bank1(void);
|
||||
void HAL_FLASHEx_DisableEccCorrectionInterrupt_Bank1(void);
|
||||
#if defined (DUAL_BANK)
|
||||
void HAL_FLASHEx_EnableEccCorrectionInterrupt_Bank2(void);
|
||||
void HAL_FLASHEx_DisableEccCorrectionInterrupt_Bank2(void);
|
||||
#endif /* DUAL_BANK */
|
||||
|
||||
void HAL_FLASHEx_EnableEccDetectionInterrupt(void);
|
||||
void HAL_FLASHEx_DisableEccDetectionInterrupt(void);
|
||||
void HAL_FLASHEx_EnableEccDetectionInterrupt_Bank1(void);
|
||||
void HAL_FLASHEx_DisableEccDetectionInterrupt_Bank1(void);
|
||||
#if defined (DUAL_BANK)
|
||||
void HAL_FLASHEx_EnableEccDetectionInterrupt_Bank2(void);
|
||||
void HAL_FLASHEx_DisableEccDetectionInterrupt_Bank2(void);
|
||||
#endif /* DUAL_BANK */
|
||||
|
||||
void HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef *pData);
|
||||
void HAL_FLASHEx_BusFault_IRQHandler(void);
|
||||
|
||||
__weak void HAL_FLASHEx_EccDetectionCallback(void);
|
||||
__weak void HAL_FLASHEx_EccCorrectionCallback(void);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_FLASH_ECC */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@ -54,7 +54,12 @@ extern "C" {
|
||||
#define GPIO_AF0_SWJ ((uint8_t)0x00) /* SWJ (SWD and JTAG) Alternate Function mapping */
|
||||
#define GPIO_AF0_LCDBIAS ((uint8_t)0x00) /* LCDBIAS Alternate Function mapping */
|
||||
#define GPIO_AF0_TRACE ((uint8_t)0x00) /* TRACE Alternate Function mapping */
|
||||
#if defined (PWR_CPUCR_PDDS_D2) /* PWR D1 and D2 domains exists */
|
||||
#if defined(PWR_CPUCR_RETDS_CD) /* CPU domain power down Deepsleep */
|
||||
#define GPIO_AF0_CSLEEP ((uint8_t)0x00) /* CSLEEP Alternate Function mapping */
|
||||
#define GPIO_AF0_CSTOP ((uint8_t)0x00) /* CSTOP Alternate Function mapping */
|
||||
#define GPIO_AF0_NDSTOP2 ((uint8_t)0x00) /* NDSTOP2 Alternate Function mapping */
|
||||
#endif /* PWR_CPUCR_RETDS_CD */
|
||||
#if defined(PWR_CPUCR_PDDS_D2) /* PWR D1 and D2 domains exists */
|
||||
#define GPIO_AF0_C1DSLEEP ((uint8_t)0x00) /* Cortex-M7 Deep Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */
|
||||
#define GPIO_AF0_C1SLEEP ((uint8_t)0x00) /* Cortex-M7 Sleep Alternate Function mapping : available on STM32H7 Rev.B and above */
|
||||
#define GPIO_AF0_D1PWREN ((uint8_t)0x00) /* Domain 1 PWR enable Alternate Function mapping : available on STM32H7 Rev.B and above */
|
||||
|
||||
@ -118,8 +118,6 @@ typedef enum
|
||||
HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
|
||||
process is ongoing */
|
||||
HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
|
||||
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
|
||||
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
|
||||
|
||||
} HAL_I2C_StateTypeDef;
|
||||
|
||||
@ -207,6 +205,7 @@ typedef struct __I2C_HandleTypeDef
|
||||
|
||||
DMA_HandleTypeDef *hdmarx; /*!< I2C Rx DMA handle parameters */
|
||||
|
||||
|
||||
HAL_LockTypeDef Lock; /*!< I2C locking object */
|
||||
|
||||
__IO HAL_I2C_StateTypeDef State; /*!< I2C communication state */
|
||||
@ -709,9 +708,9 @@ void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c);
|
||||
* @{
|
||||
*/
|
||||
/* Peripheral State, Mode and Error functions *********************************/
|
||||
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
|
||||
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c);
|
||||
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
|
||||
HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c);
|
||||
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c);
|
||||
uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c);
|
||||
|
||||
/**
|
||||
* @}
|
||||
@ -804,8 +803,8 @@ uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
|
||||
(I2C_CR2_START) | (I2C_CR2_AUTOEND)) & \
|
||||
(~I2C_CR2_RD_WRN)) : \
|
||||
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | \
|
||||
(I2C_CR2_ADD10) | (I2C_CR2_START)) & \
|
||||
(~I2C_CR2_RD_WRN)))
|
||||
(I2C_CR2_ADD10) | (I2C_CR2_START) | \
|
||||
(I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)))
|
||||
|
||||
#define I2C_CHECK_FLAG(__ISR__, __FLAG__) ((((__ISR__) & ((__FLAG__) & I2C_FLAG_MASK)) == \
|
||||
((__FLAG__) & I2C_FLAG_MASK)) ? SET : RESET)
|
||||
|
||||
@ -406,29 +406,28 @@ typedef struct
|
||||
*/
|
||||
typedef enum
|
||||
{
|
||||
HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
|
||||
, HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
|
||||
, HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
|
||||
, HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
|
||||
, HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
|
||||
, HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
|
||||
, HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
|
||||
, HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
|
||||
, HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
|
||||
, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
|
||||
, HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
|
||||
, HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
|
||||
, HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
|
||||
, HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
|
||||
HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */
|
||||
, HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */
|
||||
, HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */
|
||||
, HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */
|
||||
, HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */
|
||||
, HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */
|
||||
, HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */
|
||||
, HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */
|
||||
, HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */
|
||||
, HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */
|
||||
, HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */
|
||||
, HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */
|
||||
, HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */
|
||||
, HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */
|
||||
, HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */
|
||||
, HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */
|
||||
, HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */
|
||||
, HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */
|
||||
|
||||
, HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */
|
||||
, HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */
|
||||
, HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */
|
||||
, HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
|
||||
, HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */
|
||||
, HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */
|
||||
, HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */
|
||||
, HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */
|
||||
@ -1037,8 +1036,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to
|
||||
#define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */
|
||||
#define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */
|
||||
#define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */
|
||||
#define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */
|
||||
#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */
|
||||
#define TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */
|
||||
#define TIM_OCMODE_ASYMMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -1864,6 +1863,10 @@ mode.
|
||||
((__PRESCALER__) == TIM_ICPSC_DIV4) || \
|
||||
((__PRESCALER__) == TIM_ICPSC_DIV8))
|
||||
|
||||
#define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) && \
|
||||
((__CHANNEL__) != (TIM_CHANNEL_5)) && \
|
||||
((__CHANNEL__) != (TIM_CHANNEL_6)))
|
||||
|
||||
#define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
|
||||
((__MODE__) == TIM_OPMODE_REPETITIVE))
|
||||
|
||||
@ -1884,8 +1887,9 @@ mode.
|
||||
#define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
|
||||
((__CHANNEL__) == TIM_CHANNEL_2))
|
||||
|
||||
#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) \
|
||||
((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U))
|
||||
#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \
|
||||
(((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \
|
||||
((__PERIOD__) > 0U))
|
||||
|
||||
#define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \
|
||||
((__CHANNEL__) == TIM_CHANNEL_2) || \
|
||||
@ -1938,7 +1942,6 @@ mode.
|
||||
|
||||
#define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL)
|
||||
|
||||
|
||||
#define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
|
||||
((__STATE__) == TIM_BREAK_DISABLE))
|
||||
|
||||
@ -2009,8 +2012,8 @@ mode.
|
||||
((__MODE__) == TIM_OCMODE_PWM2) || \
|
||||
((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \
|
||||
((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \
|
||||
((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \
|
||||
((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2))
|
||||
((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM1) || \
|
||||
((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM2))
|
||||
|
||||
#define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \
|
||||
((__MODE__) == TIM_OCMODE_ACTIVE) || \
|
||||
@ -2304,7 +2307,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out
|
||||
* @{
|
||||
*/
|
||||
/* Timer Encoder functions ****************************************************/
|
||||
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig);
|
||||
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig);
|
||||
HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
|
||||
void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
|
||||
@ -2353,7 +2356,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S
|
||||
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
|
||||
HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
|
||||
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength);
|
||||
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
|
||||
uint32_t BurstLength);
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
|
||||
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
|
||||
uint32_t BurstLength, uint32_t DataLength);
|
||||
|
||||
@ -471,7 +471,7 @@ HAL_StatusTypeDef HAL_TIMEx_TISelection(TIM_HandleTypeDef *htim, uint32_t TISel
|
||||
#if defined(TIM_BDTR_BKBID)
|
||||
|
||||
HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput);
|
||||
HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput);
|
||||
HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput);
|
||||
#endif /* TIM_BDTR_BKBID */
|
||||
/**
|
||||
* @}
|
||||
|
||||
@ -178,7 +178,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
|
||||
|
||||
HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart);
|
||||
HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart);
|
||||
|
||||
|
||||
/**
|
||||
|
||||
@ -85,98 +85,107 @@ static const uint8_t LL_DMA_STR_OFFSET_TAB[] =
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
|
||||
or as Source base address in case of memory to memory transfer direction.
|
||||
uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
|
||||
or as Source base address in case of memory to memory transfer direction.
|
||||
|
||||
This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
|
||||
This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
|
||||
|
||||
uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
|
||||
or as Destination base address in case of memory to memory transfer direction.
|
||||
uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
|
||||
or as Destination base address in case of memory to memory transfer direction.
|
||||
|
||||
This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
|
||||
This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
|
||||
|
||||
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
|
||||
from memory to memory or from peripheral to memory.
|
||||
This parameter can be a value of @ref DMA_LL_EC_DIRECTION
|
||||
uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
|
||||
from memory to memory or from peripheral to memory.
|
||||
This parameter can be a value of @ref DMA_LL_EC_DIRECTION
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
|
||||
|
||||
uint32_t Mode; /*!< Specifies the normal or circular operation mode.
|
||||
This parameter can be a value of @ref DMA_LL_EC_MODE
|
||||
@note The circular buffer mode cannot be used if the memory to memory
|
||||
data transfer direction is configured on the selected Stream
|
||||
uint32_t Mode; /*!< Specifies the normal or circular operation mode.
|
||||
This parameter can be a value of @ref DMA_LL_EC_MODE
|
||||
@note The circular buffer mode cannot be used if the memory to memory
|
||||
data transfer direction is configured on the selected Stream
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
|
||||
|
||||
uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
|
||||
is incremented or not.
|
||||
This parameter can be a value of @ref DMA_LL_EC_PERIPH
|
||||
uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
|
||||
is incremented or not.
|
||||
This parameter can be a value of @ref DMA_LL_EC_PERIPH
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
|
||||
|
||||
uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
|
||||
is incremented or not.
|
||||
This parameter can be a value of @ref DMA_LL_EC_MEMORY
|
||||
uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
|
||||
is incremented or not.
|
||||
This parameter can be a value of @ref DMA_LL_EC_MEMORY
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
|
||||
|
||||
uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
|
||||
in case of memory to memory transfer direction.
|
||||
This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
|
||||
uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
|
||||
in case of memory to memory transfer direction.
|
||||
This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
|
||||
|
||||
uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
|
||||
in case of memory to memory transfer direction.
|
||||
This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
|
||||
uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
|
||||
in case of memory to memory transfer direction.
|
||||
This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
|
||||
|
||||
uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
|
||||
The data unit is equal to the source buffer configuration set in PeripheralSize
|
||||
or MemorySize parameters depending in the transfer direction.
|
||||
This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
|
||||
uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
|
||||
The data unit is equal to the source buffer configuration set in PeripheralSize
|
||||
or MemorySize parameters depending in the transfer direction.
|
||||
This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
|
||||
|
||||
uint32_t PeriphRequest; /*!< Specifies the peripheral request.
|
||||
This parameter can be a value of @ref DMAMUX1_Request_selection
|
||||
uint32_t PeriphRequest; /*!< Specifies the peripheral request.
|
||||
This parameter can be a value of @ref DMAMUX1_Request_selection
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
|
||||
|
||||
uint32_t Priority; /*!< Specifies the channel priority level.
|
||||
This parameter can be a value of @ref DMA_LL_EC_PRIORITY
|
||||
uint32_t Priority; /*!< Specifies the channel priority level.
|
||||
This parameter can be a value of @ref DMA_LL_EC_PRIORITY
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
|
||||
|
||||
uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
|
||||
This parameter can be a value of @ref DMA_LL_FIFOMODE
|
||||
@note The Direct mode (FIFO mode disabled) cannot be used if the
|
||||
memory-to-memory data transfer is configured on the selected stream
|
||||
uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
|
||||
This parameter can be a value of @ref DMA_LL_FIFOMODE
|
||||
@note The Direct mode (FIFO mode disabled) cannot be used if the
|
||||
memory-to-memory data transfer is configured on the selected stream
|
||||
|
||||
This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
|
||||
This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
|
||||
|
||||
uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
|
||||
This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD
|
||||
uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
|
||||
This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
|
||||
|
||||
uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
|
||||
It specifies the amount of data to be transferred in a single non interruptible
|
||||
transaction.
|
||||
This parameter can be a value of @ref DMA_LL_EC_MBURST
|
||||
@note The burst mode is possible only if the address Increment mode is enabled.
|
||||
uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
|
||||
It specifies the amount of data to be transferred in a single non interruptible
|
||||
transaction.
|
||||
This parameter can be a value of @ref DMA_LL_EC_MBURST
|
||||
@note The burst mode is possible only if the address Increment mode is enabled.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
|
||||
|
||||
uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
|
||||
It specifies the amount of data to be transferred in a single non interruptible
|
||||
transaction.
|
||||
This parameter can be a value of @ref DMA_LL_EC_PBURST
|
||||
@note The burst mode is possible only if the address Increment mode is enabled.
|
||||
uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
|
||||
It specifies the amount of data to be transferred in a single non interruptible
|
||||
transaction.
|
||||
This parameter can be a value of @ref DMA_LL_EC_PBURST
|
||||
@note The burst mode is possible only if the address Increment mode is enabled.
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
|
||||
|
||||
uint32_t DoubleBufferMode; /*!< Specifies the double buffer mode.
|
||||
This parameter can be a value of @ref DMA_LL_EC_DOUBLEBUFFER_MODE
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_EnableDoubleBufferMode() & LL_DMA_DisableDoubleBufferMode(). */
|
||||
|
||||
uint32_t TargetMemInDoubleBufferMode; /*!< Specifies the target memory in double buffer mode.
|
||||
This parameter can be a value of @ref DMA_LL_EC_CURRENTTARGETMEM
|
||||
|
||||
This feature can be modified afterwards using unitary function @ref LL_DMA_SetCurrentTargetMem(). */
|
||||
} LL_DMA_InitTypeDef;
|
||||
/**
|
||||
* @}
|
||||
@ -233,6 +242,15 @@ typedef struct
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
|
||||
* @{
|
||||
*/
|
||||
#define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */
|
||||
#define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentTarget Memory to Memory 1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_LL_EC_PERIPH PERIPH
|
||||
* @{
|
||||
*/
|
||||
@ -347,15 +365,6 @@ typedef struct
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
|
||||
* @{
|
||||
*/
|
||||
#define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */
|
||||
#define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentTarget Memory to Memory 1 */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -537,7 +546,9 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stre
|
||||
* CR PSIZE LL_DMA_ConfigTransfer\n
|
||||
* CR MSIZE LL_DMA_ConfigTransfer\n
|
||||
* CR PL LL_DMA_ConfigTransfer\n
|
||||
* CR PFCTRL LL_DMA_ConfigTransfer
|
||||
* CR PFCTRL LL_DMA_ConfigTransfer\n
|
||||
* CR DBM LL_DMA_ConfigTransfer\n
|
||||
* CR CT LL_DMA_ConfigTransfer
|
||||
* @param DMAx DMAx Instance
|
||||
* @param Stream This parameter can be one of the following values:
|
||||
* @arg @ref LL_DMA_STREAM_0
|
||||
@ -556,6 +567,8 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stre
|
||||
* @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
|
||||
* @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
|
||||
* @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
|
||||
* @arg @ref LL_DMA_DOUBLEBUFFER_MODE_DISABLE or @ref LL_DMA_DOUBLEBUFFER_MODE_ENABLE
|
||||
* @arg @ref LL_DMA_CURRENTTARGETMEM0 or @ref LL_DMA_CURRENTTARGETMEM1
|
||||
*@retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
|
||||
@ -563,8 +576,8 @@ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, u
|
||||
uint32_t dma_base_addr = (uint32_t)DMAx;
|
||||
|
||||
MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR,
|
||||
DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL,
|
||||
Configuration);
|
||||
DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | \
|
||||
DMA_SxCR_PFCTRL | DMA_SxCR_DBM | DMA_SxCR_CT, Configuration);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -1587,6 +1600,28 @@ __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t
|
||||
CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Check if double buffer mode is enabled or not.
|
||||
* @rmtoll CR DBM LL_DMA_IsEnabledDoubleBufferMode
|
||||
* @param DMAx DMAx Instance
|
||||
* @param Stream This parameter can be one of the following values:
|
||||
* @arg @ref LL_DMA_STREAM_0
|
||||
* @arg @ref LL_DMA_STREAM_1
|
||||
* @arg @ref LL_DMA_STREAM_2
|
||||
* @arg @ref LL_DMA_STREAM_3
|
||||
* @arg @ref LL_DMA_STREAM_4
|
||||
* @arg @ref LL_DMA_STREAM_5
|
||||
* @arg @ref LL_DMA_STREAM_6
|
||||
* @arg @ref LL_DMA_STREAM_7
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_DMA_IsEnabledDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
|
||||
{
|
||||
register uint32_t dma_base_addr = (uint32_t)DMAx;
|
||||
|
||||
return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM) == (DMA_SxCR_DBM)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get FIFO status.
|
||||
* @rmtoll FCR FS LL_DMA_GetFIFOStatus
|
||||
|
||||
@ -1135,7 +1135,7 @@ HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device,
|
||||
HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
|
||||
HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device,
|
||||
uint32_t AutoRefreshNumber);
|
||||
uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
|
||||
uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank);
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@ -451,7 +451,7 @@ __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabled(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -500,7 +500,7 @@ __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t Digital
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x0 and Max_Data=0xF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
|
||||
}
|
||||
@ -535,7 +535,7 @@ __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -568,7 +568,7 @@ __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -601,7 +601,7 @@ __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -616,7 +616,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
|
||||
* @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
|
||||
* @retval Address of data register
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
|
||||
__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(const I2C_TypeDef *I2Cx, uint32_t Direction)
|
||||
{
|
||||
uint32_t data_reg_addr;
|
||||
|
||||
@ -664,7 +664,7 @@ __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -697,7 +697,7 @@ __STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -737,7 +737,7 @@ __STATIC_INLINE void LL_I2C_DisableWakeUpFromStop(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledWakeUpFromStop(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_WUPEN) == (I2C_CR1_WUPEN)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -772,7 +772,7 @@ __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -800,7 +800,7 @@ __STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t
|
||||
* @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
|
||||
* @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
|
||||
}
|
||||
@ -849,7 +849,7 @@ __STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -905,7 +905,7 @@ __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -930,7 +930,7 @@ __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x0 and Max_Data=0xF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
|
||||
}
|
||||
@ -941,7 +941,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
|
||||
}
|
||||
@ -952,7 +952,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
|
||||
}
|
||||
@ -963,7 +963,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x0 and Max_Data=0xF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
|
||||
}
|
||||
@ -974,7 +974,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x0 and Max_Data=0xF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
|
||||
}
|
||||
@ -1011,7 +1011,7 @@ __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
|
||||
* @arg @ref LL_I2C_MODE_SMBUS_DEVICE
|
||||
* @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetMode(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
|
||||
}
|
||||
@ -1060,7 +1060,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1099,7 +1099,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1150,7 +1150,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t Timeout
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0 and Max_Data=0xFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
|
||||
}
|
||||
@ -1182,7 +1182,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t Tim
|
||||
* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
|
||||
* @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
|
||||
}
|
||||
@ -1210,7 +1210,7 @@ __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t Timeout
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0 and Max_Data=0xFFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
|
||||
}
|
||||
@ -1264,7 +1264,7 @@ __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t Cloc
|
||||
* @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(const I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == \
|
||||
(ClockTimeout)) ? 1UL : 0UL);
|
||||
@ -1306,7 +1306,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1339,7 +1339,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1372,7 +1372,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1405,7 +1405,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1438,7 +1438,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1477,7 +1477,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1528,7 +1528,7 @@ __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1549,7 +1549,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1562,7 +1562,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1575,7 +1575,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1588,7 +1588,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1601,7 +1601,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1614,7 +1614,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1627,7 +1627,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1640,7 +1640,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1653,7 +1653,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1666,7 +1666,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1679,7 +1679,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1694,7 +1694,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1709,7 +1709,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1725,7 +1725,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1738,7 +1738,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1899,7 +1899,7 @@ __STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1934,7 +1934,7 @@ __STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -1958,7 +1958,7 @@ __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t Transfer
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x0 and Max_Data=0xFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetTransferSize(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
|
||||
}
|
||||
@ -2035,7 +2035,7 @@ __STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -2063,7 +2063,7 @@ __STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t Trans
|
||||
* @arg @ref LL_I2C_REQUEST_WRITE
|
||||
* @arg @ref LL_I2C_REQUEST_READ
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
|
||||
}
|
||||
@ -2087,7 +2087,7 @@ __STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x0 and Max_Data=0x3F
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
|
||||
}
|
||||
@ -2133,11 +2133,18 @@ __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
|
||||
uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
|
||||
{
|
||||
/* Declaration of tmp to prevent undefined behavior of volatile usage */
|
||||
uint32_t tmp = ((uint32_t)(((uint32_t)SlaveAddr & I2C_CR2_SADD) | \
|
||||
((uint32_t)SlaveAddrSize & I2C_CR2_ADD10) | \
|
||||
(((uint32_t)TransferSize << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \
|
||||
(uint32_t)EndMode | (uint32_t)Request) & (~0x80000000U));
|
||||
|
||||
/* update CR2 register */
|
||||
MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 |
|
||||
(I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) |
|
||||
I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
|
||||
I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
|
||||
SlaveAddr | SlaveAddrSize | (TransferSize << I2C_CR2_NBYTES_Pos) | EndMode | Request);
|
||||
tmp);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -2150,7 +2157,7 @@ __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr
|
||||
* @arg @ref LL_I2C_DIRECTION_WRITE
|
||||
* @arg @ref LL_I2C_DIRECTION_READ
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
|
||||
}
|
||||
@ -2161,7 +2168,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x00 and Max_Data=0x3F
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
|
||||
}
|
||||
@ -2191,7 +2198,7 @@ __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return ((READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -2204,7 +2211,7 @@ __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
|
||||
}
|
||||
@ -2215,7 +2222,7 @@ __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
|
||||
* @param I2Cx I2C Instance.
|
||||
* @retval Value between Min_Data=0x00 and Max_Data=0xFF
|
||||
*/
|
||||
__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
|
||||
__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(const I2C_TypeDef *I2Cx)
|
||||
{
|
||||
return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
|
||||
}
|
||||
@ -2241,8 +2248,8 @@ __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
|
||||
* @{
|
||||
*/
|
||||
|
||||
ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
|
||||
ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx);
|
||||
ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct);
|
||||
ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx);
|
||||
void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
|
||||
|
||||
|
||||
|
||||
@ -653,10 +653,10 @@ typedef struct
|
||||
/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
|
||||
* @{
|
||||
*/
|
||||
#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
|
||||
#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!< Counter used as upcounter */
|
||||
#define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
|
||||
#define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
|
||||
#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
|
||||
#define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_1 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
|
||||
#define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
|
||||
/**
|
||||
* @}
|
||||
@ -737,6 +737,15 @@ typedef struct
|
||||
*/
|
||||
#endif /* USE_FULL_LL_DRIVER */
|
||||
|
||||
/** Legacy definitions for compatibility purpose
|
||||
@cond 0
|
||||
*/
|
||||
#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 LL_TIM_OCMODE_ASYMMETRIC_PWM1
|
||||
#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 LL_TIM_OCMODE_ASYMMETRIC_PWM2
|
||||
/**
|
||||
@endcond
|
||||
*/
|
||||
|
||||
/** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
|
||||
* @{
|
||||
*/
|
||||
@ -752,8 +761,8 @@ typedef struct
|
||||
#define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
|
||||
#define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
|
||||
#define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
|
||||
#define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
|
||||
#define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
|
||||
#define LL_TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
|
||||
#define LL_TIM_OCMODE_ASYMMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -967,11 +976,11 @@ typedef struct
|
||||
#define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=6 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=5 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=6 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=8 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
|
||||
#define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
|
||||
@ -1157,6 +1166,15 @@ typedef struct
|
||||
* @}
|
||||
*/
|
||||
|
||||
/** Legacy definitions for compatibility purpose
|
||||
@cond 0
|
||||
*/
|
||||
#define LL_TIM_ReArmBRK(_PARAM_)
|
||||
#define LL_TIM_ReArmBRK2(_PARAM_)
|
||||
/**
|
||||
@endcond
|
||||
*/
|
||||
|
||||
#endif /*TIM_BDTR_BKBID */
|
||||
/** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
|
||||
* @{
|
||||
@ -1340,6 +1358,9 @@ typedef struct
|
||||
#define LL_TIM_TIM24_TI1_RMP_CAN_TMP TIM_TISEL_TI1SEL_0 /*!< TIM24 input 1 is connected to CAN TMP */
|
||||
#define LL_TIM_TIM24_TI1_RMP_CAN_RTP TIM_TISEL_TI1SEL_1 /*!< TIM24 input 1 is connected to CAN RTP */
|
||||
#define LL_TIM_TIM24_TI1_RMP_CAN_SOC (TIM_TISEL_TI4SEL_0 | TIM_TISEL_TI4SEL_1) /*!< TIM24 input 1 is connected to CAN SOC */
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if defined(TIM_BREAK_INPUT_SUPPORT)
|
||||
/** Legacy definitions for compatibility purpose
|
||||
@ -1350,6 +1371,7 @@ typedef struct
|
||||
@endcond
|
||||
*/
|
||||
#endif /* TIM_BREAK_INPUT_SUPPORT */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -1480,11 +1502,6 @@ typedef struct
|
||||
((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
@ -1941,6 +1958,17 @@ __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
|
||||
CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled.
|
||||
* @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload
|
||||
* @param TIMx Timer instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx)
|
||||
{
|
||||
return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
|
||||
* @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
|
||||
@ -2085,7 +2113,7 @@ __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channe
|
||||
* @arg @ref LL_TIM_CHANNEL_CH6
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
|
||||
__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels)
|
||||
{
|
||||
return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -2171,8 +2199,8 @@ __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel,
|
||||
* @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
|
||||
* @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
|
||||
* @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
|
||||
* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
|
||||
* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
|
||||
* @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
|
||||
* @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
|
||||
@ -2211,8 +2239,8 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint
|
||||
* @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
|
||||
* @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
|
||||
* @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
|
||||
* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
|
||||
* @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
|
||||
* @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1
|
||||
* @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
@ -2426,7 +2454,7 @@ __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
* @arg @ref LL_TIM_CHANNEL_CH6
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
@ -2502,7 +2530,7 @@ __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channe
|
||||
* @arg @ref LL_TIM_CHANNEL_CH6
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
@ -2587,7 +2615,7 @@ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
* @arg @ref LL_TIM_CHANNEL_CH6
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel)
|
||||
{
|
||||
uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
|
||||
const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
|
||||
@ -3136,7 +3164,7 @@ __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
|
||||
* @param TIMx Timer instance
|
||||
* @retval State of bit (1 or 0).
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
|
||||
__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx)
|
||||
{
|
||||
return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL);
|
||||
}
|
||||
@ -3688,18 +3716,6 @@ __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx)
|
||||
SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Re-arm the break input (when it operates in bidirectional mode).
|
||||
* @note The Break input is automatically armed as soon as MOE bit is set.
|
||||
* @rmtoll BDTR BKDSRM LL_TIM_ReArmBRK
|
||||
* @param TIMx Timer instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx)
|
||||
{
|
||||
CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM);
|
||||
}
|
||||
|
||||
#endif /*TIM_BDTR_BKBID */
|
||||
/**
|
||||
* @brief Enable the break 2 function.
|
||||
@ -3828,18 +3844,6 @@ __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx)
|
||||
SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Re-arm the break 2 input (when it operates in bidirectional mode).
|
||||
* @note The Break 2 input is automatically armed as soon as MOE bit is set.
|
||||
* @rmtoll BDTR BK2DSRM LL_TIM_ReArmBRK2
|
||||
* @param TIMx Timer instance
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx)
|
||||
{
|
||||
CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM);
|
||||
}
|
||||
|
||||
#endif /*TIM_BDTR_BKBID */
|
||||
/**
|
||||
* @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
|
||||
@ -5170,7 +5174,7 @@ __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
|
||||
* @{
|
||||
*/
|
||||
|
||||
ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
|
||||
ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx);
|
||||
void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
|
||||
ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct);
|
||||
void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
|
||||
|
||||
@ -1567,7 +1567,7 @@ __STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_
|
||||
* @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME
|
||||
* @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME
|
||||
*/
|
||||
__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx)
|
||||
__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(const USART_TypeDef *USARTx)
|
||||
{
|
||||
return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE));
|
||||
}
|
||||
|
||||
@ -345,7 +345,7 @@ __STATIC_INLINE uint32_t LL_GetPackageType(void)
|
||||
* @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro)
|
||||
* @note When a RTOS is used, it is recommended to avoid changing the SysTick
|
||||
* configuration by calling this function, for a delay use rather osDelay RTOS service.
|
||||
* @param Ticks Number of ticks
|
||||
* @param Ticks Frequency of Ticks (Hz)
|
||||
* @retval None
|
||||
*/
|
||||
__STATIC_INLINE void LL_InitTick(uint32_t HCLKFrequency, uint32_t Ticks)
|
||||
|
||||
@ -47,11 +47,11 @@
|
||||
/* Private typedef -----------------------------------------------------------*/
|
||||
/* Private define ------------------------------------------------------------*/
|
||||
/**
|
||||
* @brief STM32H7xx HAL Driver version number V1.11.1
|
||||
* @brief STM32H7xx HAL Driver version number
|
||||
*/
|
||||
#define __STM32H7xx_HAL_VERSION_MAIN (0x01UL) /*!< [31:24] main version */
|
||||
#define __STM32H7xx_HAL_VERSION_SUB1 (0x0BUL) /*!< [23:16] sub1 version */
|
||||
#define __STM32H7xx_HAL_VERSION_SUB2 (0x01UL) /*!< [15:8] sub2 version */
|
||||
#define __STM32H7xx_HAL_VERSION_SUB2 (0x03UL) /*!< [15:8] sub2 version */
|
||||
#define __STM32H7xx_HAL_VERSION_RC (0x00UL) /*!< [7:0] release candidate */
|
||||
#define __STM32H7xx_HAL_VERSION ((__STM32H7xx_HAL_VERSION_MAIN << 24)\
|
||||
|(__STM32H7xx_HAL_VERSION_SUB1 << 16)\
|
||||
@ -383,7 +383,8 @@ HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
|
||||
|
||||
/**
|
||||
* @brief Return tick frequency.
|
||||
* @retval tick period in Hz
|
||||
* @retval Tick frequency.
|
||||
* Value of @ref HAL_TickFreqTypeDef.
|
||||
*/
|
||||
HAL_TickFreqTypeDef HAL_GetTickFreq(void)
|
||||
{
|
||||
|
||||
@ -288,10 +288,43 @@ void HAL_MPU_Enable(uint32_t MPU_Control)
|
||||
__DSB();
|
||||
__ISB();
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enables the MPU Region.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_MPU_EnableRegion(uint32_t RegionNumber)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
|
||||
|
||||
/* Set the Region number */
|
||||
MPU->RNR = RegionNumber;
|
||||
|
||||
/* Enable the Region */
|
||||
SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disables the MPU Region.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_MPU_DisableRegion(uint32_t RegionNumber)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_MPU_REGION_NUMBER(RegionNumber));
|
||||
|
||||
/* Set the Region number */
|
||||
MPU->RNR = RegionNumber;
|
||||
|
||||
/* Disable the Region */
|
||||
CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initializes and configures the Region and the memory to be protected.
|
||||
* @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
|
||||
* the initialization and configuration information.
|
||||
* @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
|
||||
* the initialization and configuration information.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
|
||||
@ -299,38 +332,32 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init)
|
||||
/* Check the parameters */
|
||||
assert_param(IS_MPU_REGION_NUMBER(MPU_Init->Number));
|
||||
assert_param(IS_MPU_REGION_ENABLE(MPU_Init->Enable));
|
||||
assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
|
||||
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
|
||||
assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
|
||||
assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
|
||||
assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
|
||||
assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
|
||||
assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
|
||||
assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
|
||||
|
||||
/* Set the Region number */
|
||||
MPU->RNR = MPU_Init->Number;
|
||||
|
||||
if ((MPU_Init->Enable) != 0UL)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_MPU_INSTRUCTION_ACCESS(MPU_Init->DisableExec));
|
||||
assert_param(IS_MPU_REGION_PERMISSION_ATTRIBUTE(MPU_Init->AccessPermission));
|
||||
assert_param(IS_MPU_TEX_LEVEL(MPU_Init->TypeExtField));
|
||||
assert_param(IS_MPU_ACCESS_SHAREABLE(MPU_Init->IsShareable));
|
||||
assert_param(IS_MPU_ACCESS_CACHEABLE(MPU_Init->IsCacheable));
|
||||
assert_param(IS_MPU_ACCESS_BUFFERABLE(MPU_Init->IsBufferable));
|
||||
assert_param(IS_MPU_SUB_REGION_DISABLE(MPU_Init->SubRegionDisable));
|
||||
assert_param(IS_MPU_REGION_SIZE(MPU_Init->Size));
|
||||
/* Disable the Region */
|
||||
CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
|
||||
|
||||
MPU->RBAR = MPU_Init->BaseAddress;
|
||||
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
|
||||
((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
|
||||
((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
|
||||
((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
|
||||
((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
|
||||
((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
|
||||
((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
|
||||
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
|
||||
((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
|
||||
}
|
||||
else
|
||||
{
|
||||
MPU->RBAR = 0x00;
|
||||
MPU->RASR = 0x00;
|
||||
}
|
||||
/* Apply configuration */
|
||||
MPU->RBAR = MPU_Init->BaseAddress;
|
||||
MPU->RASR = ((uint32_t)MPU_Init->DisableExec << MPU_RASR_XN_Pos) |
|
||||
((uint32_t)MPU_Init->AccessPermission << MPU_RASR_AP_Pos) |
|
||||
((uint32_t)MPU_Init->TypeExtField << MPU_RASR_TEX_Pos) |
|
||||
((uint32_t)MPU_Init->IsShareable << MPU_RASR_S_Pos) |
|
||||
((uint32_t)MPU_Init->IsCacheable << MPU_RASR_C_Pos) |
|
||||
((uint32_t)MPU_Init->IsBufferable << MPU_RASR_B_Pos) |
|
||||
((uint32_t)MPU_Init->SubRegionDisable << MPU_RASR_SRD_Pos) |
|
||||
((uint32_t)MPU_Init->Size << MPU_RASR_SIZE_Pos) |
|
||||
((uint32_t)MPU_Init->Enable << MPU_RASR_ENABLE_Pos);
|
||||
}
|
||||
#endif /* __MPU_PRESENT */
|
||||
|
||||
|
||||
@ -98,7 +98,7 @@
|
||||
(++) Provide exiting handle as parameter.
|
||||
(++) Provide pointer on EXTI_ConfigTypeDef structure as second parameter.
|
||||
|
||||
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_GetConfigLine().
|
||||
(#) Clear Exti configuration of a dedicated line using HAL_EXTI_ClearConfigLine().
|
||||
(++) Provide exiting handle as parameter.
|
||||
|
||||
(#) Register callback to treat Exti interrupts using HAL_EXTI_RegisterCallback().
|
||||
@ -109,7 +109,7 @@
|
||||
|
||||
(#) Get interrupt pending bit using HAL_EXTI_GetPending().
|
||||
|
||||
(#) Clear interrupt pending bit using HAL_EXTI_GetPending().
|
||||
(#) Clear interrupt pending bit using HAL_EXTI_ClearPending().
|
||||
|
||||
(#) Generate software interrupt using HAL_EXTI_GenerateSWI().
|
||||
|
||||
@ -742,6 +742,9 @@ uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
|
||||
uint32_t maskline;
|
||||
uint32_t offset;
|
||||
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(Edge);
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
|
||||
@ -788,6 +791,9 @@ void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge)
|
||||
uint32_t maskline;
|
||||
uint32_t offset;
|
||||
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(Edge);
|
||||
|
||||
/* Check parameters */
|
||||
assert_param(IS_EXTI_LINE(hexti->Line));
|
||||
assert_param(IS_EXTI_CONFIG_LINE(hexti->Line));
|
||||
|
||||
@ -123,8 +123,8 @@ FLASH_ProcessTypeDef pFlash;
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions
|
||||
* @brief Programming operation functions
|
||||
*
|
||||
* @brief Programming operation functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Programming operation functions #####
|
||||
@ -173,6 +173,8 @@ HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t FlashAddress,
|
||||
#endif /* FLASH_OPTCR_PG_OTP */
|
||||
{
|
||||
bank = FLASH_BANK_1;
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(TypeProgram);
|
||||
}
|
||||
#if defined (DUAL_BANK)
|
||||
else if(IS_FLASH_PROGRAM_ADDRESS_BANK2(FlashAddress))
|
||||
@ -339,6 +341,8 @@ HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t FlashAddre
|
||||
#endif /* FLASH_OPTCR_PG_OTP */
|
||||
{
|
||||
bank = FLASH_BANK_1;
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(TypeProgram);
|
||||
}
|
||||
#if defined (DUAL_BANK)
|
||||
else if(IS_FLASH_PROGRAM_ADDRESS_BANK2(FlashAddress))
|
||||
@ -655,6 +659,38 @@ void HAL_FLASH_IRQHandler(void)
|
||||
HAL_FLASH_OperationErrorCallback(temp);
|
||||
}
|
||||
|
||||
#if (USE_FLASH_ECC == 1U)
|
||||
/* Check FLASH Bank1 ECC single correction error flag */
|
||||
errorflag = FLASH->SR1 & FLASH_FLAG_SNECCERR_BANK1;
|
||||
|
||||
if(errorflag != 0U)
|
||||
{
|
||||
/* Save the error code */
|
||||
pFlash.ErrorCode |= errorflag;
|
||||
|
||||
/* Call User callback */
|
||||
HAL_FLASHEx_EccCorrectionCallback();
|
||||
|
||||
/* Clear FLASH Bank1 ECC single correction error flag in order to allow new ECC error record */
|
||||
__HAL_FLASH_CLEAR_FLAG_BANK1(errorflag);
|
||||
}
|
||||
|
||||
/* Check FLASH Bank1 ECC double detection error flag */
|
||||
errorflag = FLASH->SR1 & FLASH_FLAG_DBECCERR_BANK1;
|
||||
|
||||
if(errorflag != 0U)
|
||||
{
|
||||
/* Save the error code */
|
||||
pFlash.ErrorCode |= errorflag;
|
||||
|
||||
/* Call User callback */
|
||||
HAL_FLASHEx_EccDetectionCallback();
|
||||
|
||||
/* Clear FLASH Bank1 ECC double detection error flag in order to allow new ECC error record */
|
||||
__HAL_FLASH_CLEAR_FLAG_BANK1(errorflag);
|
||||
}
|
||||
#endif /* USE_FLASH_ECC */
|
||||
|
||||
#if defined (DUAL_BANK)
|
||||
/* Check FLASH Bank2 operation error flags */
|
||||
#if defined (FLASH_SR_OPERR)
|
||||
@ -698,6 +734,39 @@ void HAL_FLASH_IRQHandler(void)
|
||||
/* FLASH error interrupt user callback */
|
||||
HAL_FLASH_OperationErrorCallback(temp);
|
||||
}
|
||||
|
||||
#if (USE_FLASH_ECC == 1U)
|
||||
/* Check FLASH Bank2 ECC single correction error flag */
|
||||
errorflag = FLASH->SR2 & FLASH_FLAG_SNECCERR_BANK2;
|
||||
|
||||
if(errorflag != 0U)
|
||||
{
|
||||
/* Save the error code */
|
||||
pFlash.ErrorCode |= (errorflag | 0x80000000U);
|
||||
|
||||
/* Call User callback */
|
||||
HAL_FLASHEx_EccCorrectionCallback();
|
||||
|
||||
/* Clear FLASH Bank2 ECC single correction error flag in order to allow new ECC error record */
|
||||
__HAL_FLASH_CLEAR_FLAG_BANK2(errorflag);
|
||||
}
|
||||
|
||||
/* Check FLASH Bank2 ECC double detection error flag */
|
||||
errorflag = FLASH->SR2 & FLASH_FLAG_DBECCERR_BANK2;
|
||||
|
||||
if(errorflag != 0U)
|
||||
{
|
||||
/* Save the error code */
|
||||
pFlash.ErrorCode |= (errorflag | 0x80000000U);
|
||||
|
||||
/* Call User callback */
|
||||
HAL_FLASHEx_EccDetectionCallback();
|
||||
|
||||
/* Clear FLASH Bank2 ECC double detection error flag in order to allow new ECC error record */
|
||||
__HAL_FLASH_CLEAR_FLAG_BANK2(errorflag);
|
||||
}
|
||||
|
||||
#endif /* USE_FLASH_ECC */
|
||||
#endif /* DUAL_BANK */
|
||||
|
||||
if(pFlash.ProcedureOnGoing == FLASH_PROC_NONE)
|
||||
@ -771,8 +840,8 @@ __weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions
|
||||
* @brief Management functions
|
||||
*
|
||||
* @brief Management functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Control functions #####
|
||||
@ -932,8 +1001,8 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
|
||||
*/
|
||||
|
||||
/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions
|
||||
* @brief Peripheral Errors functions
|
||||
*
|
||||
* @brief Peripheral Errors functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Peripheral Errors functions #####
|
||||
@ -971,7 +1040,7 @@ HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
|
||||
* @arg HAL_FLASH_ERROR_SNECC_BANK2: SNECC Error on Bank 2
|
||||
* @arg HAL_FLASH_ERROR_DBECC_BANK2: Double Detection ECC on Bank 2
|
||||
* @arg HAL_FLASH_ERROR_CRCRD_BANK2: CRC Read Error on Bank 2
|
||||
*/
|
||||
*/
|
||||
|
||||
uint32_t HAL_FLASH_GetError(void)
|
||||
{
|
||||
|
||||
@ -58,6 +58,16 @@
|
||||
(++) Perform the CRC computation
|
||||
(++) Disable CRC feature
|
||||
|
||||
(#) Error correction code error functions:
|
||||
(++) Use the HAL_FLASHEx_EnableEccCorrectionInterrupt() and HAL_FLASHEx_DisableEccCorrectionInterrupt()
|
||||
functions to enable and disable the FLASH ECC correction interruption.
|
||||
(++) Use the HAL_FLASHEx_EnableEccDetectionInterrupt() and HAL_FLASHEx_DisableEccDetectionInterrupt()
|
||||
functions to enable and disable the FLASH ECC Detection interruption.
|
||||
(++) Handle ECCD interrupt by calling HAL_FLASHEx_BusFault_IRQHandler()
|
||||
(++) Use HAL_FLASHEx_BusFault_IRQHandler() function called under BusFault_IRQHandler() interrupt subroutine
|
||||
to handle the ECCD interrupt.
|
||||
(++) Use HAL_FLASHEx_GetEccInfo() function to get the flash ECC fail information.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
* @attention
|
||||
@ -818,6 +828,251 @@ HAL_StatusTypeDef HAL_FLASHEx_ComputeCRC(FLASH_CRCInitTypeDef *pCRCInit, uint32_
|
||||
* @}
|
||||
*/
|
||||
|
||||
#if (USE_FLASH_ECC == 1U)
|
||||
/** @defgroup FLASHEx_Exported_Functions_Group2 Extended ECC operation functions
|
||||
* @brief Extended ECC operation functions
|
||||
*
|
||||
@verbatim
|
||||
===============================================================================
|
||||
##### Extended ECC operation functions #####
|
||||
===============================================================================
|
||||
[..]
|
||||
This subsection provides a set of functions allowing to manage the Extended FLASH
|
||||
ECC Operations.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Enable ECC correction interrupts on FLASH BANK1 and BANK2.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASHEx_EnableEccCorrectionInterrupt(void)
|
||||
{
|
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_SNECCERR_BANK1);
|
||||
|
||||
#if defined (DUAL_BANK)
|
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_SNECCERR_BANK2);
|
||||
#endif /* DUAL_BANK */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable ECC correction interrupts on FLASH BANK1 and BANK2.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASHEx_DisableEccCorrectionInterrupt(void)
|
||||
{
|
||||
__HAL_FLASH_DISABLE_IT(FLASH_IT_SNECCERR_BANK1);
|
||||
|
||||
#if defined (DUAL_BANK)
|
||||
__HAL_FLASH_DISABLE_IT(FLASH_IT_SNECCERR_BANK2);
|
||||
#endif /* DUAL_BANK */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable ECC correction interrupt on FLASH BANK1.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASHEx_EnableEccCorrectionInterrupt_Bank1(void)
|
||||
{
|
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_SNECCERR_BANK1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable ECC correction interrupt on FLASH BANK1.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASHEx_DisableEccCorrectionInterrupt_Bank1(void)
|
||||
{
|
||||
__HAL_FLASH_DISABLE_IT(FLASH_IT_SNECCERR_BANK1);
|
||||
}
|
||||
|
||||
#if defined (DUAL_BANK)
|
||||
/**
|
||||
* @brief Enable ECC correction interrupt on FLASH BANK2.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASHEx_EnableEccCorrectionInterrupt_Bank2(void)
|
||||
{
|
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_SNECCERR_BANK2);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable ECC correction interrupt on FLASH BANK2.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASHEx_DisableEccCorrectionInterrupt_Bank2(void)
|
||||
{
|
||||
__HAL_FLASH_DISABLE_IT(FLASH_IT_SNECCERR_BANK2);
|
||||
}
|
||||
#endif /* DUAL_BANK */
|
||||
|
||||
/**
|
||||
* @brief Enable ECC Detection interrupts on FLASH BANK1 and BANK2.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASHEx_EnableEccDetectionInterrupt(void)
|
||||
{
|
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_DBECCERR_BANK1);
|
||||
|
||||
#if defined (DUAL_BANK)
|
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_DBECCERR_BANK2);
|
||||
#endif /* DUAL_BANK */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable ECC Detection interrupts on FLASH BANK1 and BANK2.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASHEx_DisableEccDetectionInterrupt(void)
|
||||
{
|
||||
__HAL_FLASH_DISABLE_IT(FLASH_IT_DBECCERR_BANK1);
|
||||
|
||||
#if defined (DUAL_BANK)
|
||||
__HAL_FLASH_DISABLE_IT(FLASH_IT_DBECCERR_BANK2);
|
||||
#endif /* DUAL_BANK */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Enable ECC Detection interrupt on FLASH BANK1.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASHEx_EnableEccDetectionInterrupt_Bank1(void)
|
||||
{
|
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_DBECCERR_BANK1);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable ECC correction interrupt on FLASH BANK1.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASHEx_DisableEccDetectionInterrupt_Bank1(void)
|
||||
{
|
||||
__HAL_FLASH_DISABLE_IT(FLASH_IT_DBECCERR_BANK1);
|
||||
}
|
||||
|
||||
#if defined (DUAL_BANK)
|
||||
/**
|
||||
* @brief Enable ECC Detection interrupt on FLASH BANK2.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASHEx_EnableEccDetectionInterrupt_Bank2(void)
|
||||
{
|
||||
__HAL_FLASH_ENABLE_IT(FLASH_IT_DBECCERR_BANK2);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Disable ECC Detection interrupt on FLASH BANK2.
|
||||
* @param None
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASHEx_DisableEccDetectionInterrupt_Bank2(void)
|
||||
{
|
||||
__HAL_FLASH_DISABLE_IT(FLASH_IT_DBECCERR_BANK2);
|
||||
}
|
||||
#endif /* DUAL_BANK */
|
||||
|
||||
/**
|
||||
* @brief Get the ECC error information.
|
||||
* @param pData Pointer to an FLASH_EccInfoTypeDef structure that contains the
|
||||
* ECC error information.
|
||||
* @note This function should be called before ECC bit is cleared
|
||||
* (in callback function)
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASHEx_GetEccInfo(FLASH_EccInfoTypeDef *pData)
|
||||
{
|
||||
uint32_t errorflag;
|
||||
|
||||
/* Check FLASH Bank1 ECC single correction and double detection error flags */
|
||||
errorflag = FLASH->SR1 & (FLASH_FLAG_SNECCERR_BANK1 | FLASH_FLAG_DBECCERR_BANK1);
|
||||
if(errorflag != 0U)
|
||||
{
|
||||
pData->Area = FLASH_ECC_AREA_USER_BANK1;
|
||||
pData->Address = ((((FLASH->ECC_FA1 & FLASH_ECC_FA_FAIL_ECC_ADDR))* FLASH_NB_32BITWORD_IN_FLASHWORD * 4) + FLASH_BANK1_BASE);
|
||||
}
|
||||
#if defined (DUAL_BANK)
|
||||
/* Check FLASH Bank2 ECC single correction and double detection error flags */
|
||||
errorflag = FLASH->SR2 & (FLASH_FLAG_SNECCERR_BANK2 | FLASH_FLAG_DBECCERR_BANK2);
|
||||
if(errorflag != 0U)
|
||||
{
|
||||
pData->Area = FLASH_ECC_AREA_USER_BANK2;
|
||||
pData->Address = ((((FLASH->ECC_FA2 & FLASH_ECC_FA_FAIL_ECC_ADDR))* FLASH_NB_32BITWORD_IN_FLASHWORD * 4) + FLASH_BANK2_BASE);
|
||||
}
|
||||
#endif /* DUAL_BANK */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Handle Flash ECC Detection interrupt request.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_FLASHEx_BusFault_IRQHandler(void)
|
||||
{
|
||||
/* Check if the ECC double error occured*/
|
||||
if ((FLASH->SR1 & FLASH_FLAG_DBECCERR_BANK1) != 0)
|
||||
{
|
||||
/* FLASH ECC detection user callback */
|
||||
HAL_FLASHEx_EccDetectionCallback();
|
||||
|
||||
/* Clear Bank 1 ECC double detection error flag
|
||||
note : this step will clear all the informations related to the flash ECC detection
|
||||
*/
|
||||
__HAL_FLASH_CLEAR_FLAG_BANK1(FLASH_FLAG_DBECCERR_BANK1);
|
||||
}
|
||||
#if defined (DUAL_BANK)
|
||||
/* Check if the ECC double error occured*/
|
||||
if ((FLASH->SR2 & FLASH_FLAG_DBECCERR_BANK2) != 0)
|
||||
{
|
||||
/* FLASH ECC detection user callback */
|
||||
HAL_FLASHEx_EccDetectionCallback();
|
||||
|
||||
/* Clear Bank 2 ECC double detection error flag
|
||||
note : this step will clear all the informations related to the flash ECC detection
|
||||
*/
|
||||
__HAL_FLASH_CLEAR_FLAG_BANK2(FLASH_FLAG_DBECCERR_BANK2);
|
||||
}
|
||||
#endif /* DUAL_BANK */
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief FLASH ECC Correction interrupt callback.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_FLASHEx_EccCorrectionCallback(void)
|
||||
{
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_FLASHEx_EccCorrectionCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief FLASH ECC Detection interrupt callback.
|
||||
* @retval None
|
||||
*/
|
||||
__weak void HAL_FLASHEx_EccDetectionCallback(void)
|
||||
{
|
||||
/* NOTE : This function should not be modified, when the callback is needed,
|
||||
the HAL_FLASHEx_EccDetectionCallback could be implemented in the user file
|
||||
*/
|
||||
}
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
#endif /* USE_FLASH_ECC */
|
||||
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
@ -400,9 +400,15 @@
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private macro -------------------------------------------------------------*/
|
||||
/* Private macros ------------------------------------------------------------*/
|
||||
/** @addtogroup I2C_Private_Macro
|
||||
* @{
|
||||
*/
|
||||
/* Macro to get remaining data to transfer on DMA side */
|
||||
#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) __HAL_DMA_GET_COUNTER(__HANDLE__)
|
||||
/**
|
||||
* @}
|
||||
*/
|
||||
|
||||
/* Private variables ---------------------------------------------------------*/
|
||||
/* Private function prototypes -----------------------------------------------*/
|
||||
@ -418,6 +424,7 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
|
||||
static void I2C_DMAError(DMA_HandleTypeDef *hdma);
|
||||
static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
|
||||
|
||||
|
||||
/* Private functions to handle IT transfer */
|
||||
static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
|
||||
static void I2C_ITMasterSeqCplt(I2C_HandleTypeDef *hi2c);
|
||||
@ -601,7 +608,12 @@ HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
|
||||
/* Configure I2Cx: Addressing Master mode */
|
||||
if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
|
||||
{
|
||||
hi2c->Instance->CR2 = (I2C_CR2_ADD10);
|
||||
SET_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear the I2C ADD10 bit */
|
||||
CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_ADD10);
|
||||
}
|
||||
/* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
|
||||
hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
|
||||
@ -1108,6 +1120,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
|
||||
uint16_t Size, uint32_t Timeout)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
uint32_t xfermode;
|
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_READY)
|
||||
{
|
||||
@ -1131,18 +1144,39 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevA
|
||||
hi2c->XferCount = Size;
|
||||
hi2c->XferISR = NULL;
|
||||
|
||||
/* Send Slave Address */
|
||||
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
|
||||
if (hi2c->XferCount > MAX_NBYTE_SIZE)
|
||||
{
|
||||
hi2c->XferSize = MAX_NBYTE_SIZE;
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_RELOAD_MODE,
|
||||
I2C_GENERATE_START_WRITE);
|
||||
xfermode = I2C_RELOAD_MODE;
|
||||
}
|
||||
else
|
||||
{
|
||||
hi2c->XferSize = hi2c->XferCount;
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
|
||||
xfermode = I2C_AUTOEND_MODE;
|
||||
}
|
||||
|
||||
if (hi2c->XferSize > 0U)
|
||||
{
|
||||
/* Preload TX register */
|
||||
/* Write data to TXDR */
|
||||
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
|
||||
|
||||
/* Increment Buffer pointer */
|
||||
hi2c->pBuffPtr++;
|
||||
|
||||
hi2c->XferCount--;
|
||||
hi2c->XferSize--;
|
||||
|
||||
/* Send Slave Address */
|
||||
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode,
|
||||
I2C_GENERATE_START_WRITE);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Send Slave Address */
|
||||
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode,
|
||||
I2C_GENERATE_START_WRITE);
|
||||
}
|
||||
|
||||
@ -1345,6 +1379,8 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
|
||||
uint32_t Timeout)
|
||||
{
|
||||
uint32_t tickstart;
|
||||
uint16_t tmpXferCount;
|
||||
HAL_StatusTypeDef error;
|
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_READY)
|
||||
{
|
||||
@ -1438,31 +1474,48 @@ HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData
|
||||
}
|
||||
|
||||
/* Wait until AF flag is set */
|
||||
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart) != HAL_OK)
|
||||
error = I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout, tickstart);
|
||||
|
||||
if (error != HAL_OK)
|
||||
{
|
||||
/* Disable Address Acknowledge */
|
||||
hi2c->Instance->CR2 |= I2C_CR2_NACK;
|
||||
return HAL_ERROR;
|
||||
/* Check that I2C transfer finished */
|
||||
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
|
||||
/* Mean XferCount == 0 */
|
||||
|
||||
tmpXferCount = hi2c->XferCount;
|
||||
if ((hi2c->ErrorCode == HAL_I2C_ERROR_AF) && (tmpXferCount == 0U))
|
||||
{
|
||||
/* Reset ErrorCode to NONE */
|
||||
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Disable Address Acknowledge */
|
||||
hi2c->Instance->CR2 |= I2C_CR2_NACK;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
}
|
||||
|
||||
/* Flush TX register */
|
||||
I2C_Flush_TXDR(hi2c);
|
||||
|
||||
/* Clear AF flag */
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
||||
|
||||
/* Wait until STOP flag is set */
|
||||
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
|
||||
else
|
||||
{
|
||||
/* Disable Address Acknowledge */
|
||||
hi2c->Instance->CR2 |= I2C_CR2_NACK;
|
||||
/* Flush TX register */
|
||||
I2C_Flush_TXDR(hi2c);
|
||||
|
||||
return HAL_ERROR;
|
||||
/* Clear AF flag */
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
||||
|
||||
/* Wait until STOP flag is set */
|
||||
if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
|
||||
{
|
||||
/* Disable Address Acknowledge */
|
||||
hi2c->Instance->CR2 |= I2C_CR2_NACK;
|
||||
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Clear STOP flag */
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
||||
}
|
||||
|
||||
/* Clear STOP flag */
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
||||
|
||||
/* Wait until BUSY flag is reset */
|
||||
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
|
||||
{
|
||||
@ -1665,7 +1718,26 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t D
|
||||
|
||||
/* Send Slave Address */
|
||||
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
|
||||
if (hi2c->XferSize > 0U)
|
||||
{
|
||||
/* Preload TX register */
|
||||
/* Write data to TXDR */
|
||||
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
|
||||
|
||||
/* Increment Buffer pointer */
|
||||
hi2c->pBuffPtr++;
|
||||
|
||||
hi2c->XferCount--;
|
||||
hi2c->XferSize--;
|
||||
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U), xfermode,
|
||||
I2C_GENERATE_START_WRITE);
|
||||
}
|
||||
else
|
||||
{
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode,
|
||||
I2C_GENERATE_START_WRITE);
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
@ -1888,6 +1960,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
|
||||
{
|
||||
uint32_t xfermode;
|
||||
HAL_StatusTypeDef dmaxferstatus;
|
||||
uint32_t sizetoxfer = 0U;
|
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_READY)
|
||||
{
|
||||
@ -1920,6 +1993,20 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
|
||||
xfermode = I2C_AUTOEND_MODE;
|
||||
}
|
||||
|
||||
if (hi2c->XferSize > 0U)
|
||||
{
|
||||
/* Preload TX register */
|
||||
/* Write data to TXDR */
|
||||
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
|
||||
|
||||
/* Increment Buffer pointer */
|
||||
hi2c->pBuffPtr++;
|
||||
|
||||
sizetoxfer = hi2c->XferSize;
|
||||
hi2c->XferCount--;
|
||||
hi2c->XferSize--;
|
||||
}
|
||||
|
||||
if (hi2c->XferSize > 0U)
|
||||
{
|
||||
if (hi2c->hdmatx != NULL)
|
||||
@ -1935,8 +2022,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
|
||||
hi2c->hdmatx->XferAbortCallback = NULL;
|
||||
|
||||
/* Enable the DMA stream or channel depends on Instance */
|
||||
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
|
||||
hi2c->XferSize);
|
||||
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr,
|
||||
(uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
|
||||
}
|
||||
else
|
||||
{
|
||||
@ -1957,7 +2044,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
|
||||
{
|
||||
/* Send Slave Address */
|
||||
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)(hi2c->XferSize + 1U),
|
||||
xfermode, I2C_GENERATE_START_WRITE);
|
||||
|
||||
/* Update XferCount value */
|
||||
hi2c->XferCount -= hi2c->XferSize;
|
||||
@ -1996,7 +2084,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t
|
||||
|
||||
/* Send Slave Address */
|
||||
/* Set NBYTES to write and generate START condition */
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, I2C_AUTOEND_MODE,
|
||||
I2C_GENERATE_START_WRITE);
|
||||
|
||||
/* Process Unlocked */
|
||||
@ -2152,11 +2240,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t D
|
||||
/* Note : The I2C interrupts must be enabled after unlocking current process
|
||||
to avoid the risk of I2C interrupt handle execution before current
|
||||
process unlock */
|
||||
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
|
||||
/* Enable ERR, TC, STOP, NACK, RXI interrupt */
|
||||
/* possible to enable all of these */
|
||||
/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
|
||||
I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
|
||||
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
|
||||
I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
@ -2406,6 +2494,7 @@ HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pD
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write an amount of data in blocking mode to a specific memory address
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
@ -2720,6 +2809,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddr
|
||||
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
||||
|
||||
/* Prepare transfer parameters */
|
||||
hi2c->XferSize = 0U;
|
||||
hi2c->pBuffPtr = pData;
|
||||
hi2c->XferCount = Size;
|
||||
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
|
||||
@ -2841,11 +2931,11 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
|
||||
to avoid the risk of I2C interrupt handle execution before current
|
||||
process unlock */
|
||||
|
||||
/* Enable ERR, TC, STOP, NACK, RXI interrupt */
|
||||
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
|
||||
/* possible to enable all of these */
|
||||
/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
|
||||
I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
|
||||
I2C_Enable_IRQ(hi2c, (I2C_XFER_TX_IT | I2C_XFER_RX_IT));
|
||||
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
|
||||
|
||||
return HAL_OK;
|
||||
}
|
||||
@ -2854,6 +2944,7 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddre
|
||||
return HAL_BUSY;
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
|
||||
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
|
||||
@ -3250,22 +3341,6 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
||||
}
|
||||
|
||||
/* Check if the maximum allowed number of trials has been reached */
|
||||
if (I2C_Trials == Trials)
|
||||
{
|
||||
/* Generate Stop */
|
||||
hi2c->Instance->CR2 |= I2C_CR2_STOP;
|
||||
|
||||
/* Wait until STOPF flag is reset */
|
||||
if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Clear STOP Flag */
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
||||
}
|
||||
|
||||
/* Increment Trials */
|
||||
I2C_Trials++;
|
||||
} while (I2C_Trials < Trials);
|
||||
@ -3304,6 +3379,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16
|
||||
{
|
||||
uint32_t xfermode;
|
||||
uint32_t xferrequest = I2C_GENERATE_START_WRITE;
|
||||
uint32_t sizetoxfer = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
|
||||
@ -3335,6 +3411,21 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16
|
||||
xfermode = hi2c->XferOptions;
|
||||
}
|
||||
|
||||
if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \
|
||||
(XferOptions == I2C_FIRST_AND_LAST_FRAME)))
|
||||
{
|
||||
/* Preload TX register */
|
||||
/* Write data to TXDR */
|
||||
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
|
||||
|
||||
/* Increment Buffer pointer */
|
||||
hi2c->pBuffPtr++;
|
||||
|
||||
sizetoxfer = hi2c->XferSize;
|
||||
hi2c->XferCount--;
|
||||
hi2c->XferSize--;
|
||||
}
|
||||
|
||||
/* If transfer direction not change and there is no request to start another frame,
|
||||
do not generate Restart Condition */
|
||||
/* Mean Previous state is same as current state */
|
||||
@ -3356,7 +3447,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16
|
||||
}
|
||||
|
||||
/* Send Slave Address and set NBYTES to write */
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
|
||||
if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
|
||||
{
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
|
||||
}
|
||||
else
|
||||
{
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
@ -3396,6 +3494,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
|
||||
uint32_t xfermode;
|
||||
uint32_t xferrequest = I2C_GENERATE_START_WRITE;
|
||||
HAL_StatusTypeDef dmaxferstatus;
|
||||
uint32_t sizetoxfer = 0U;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
|
||||
@ -3427,6 +3526,21 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
|
||||
xfermode = hi2c->XferOptions;
|
||||
}
|
||||
|
||||
if ((hi2c->XferSize > 0U) && ((XferOptions == I2C_FIRST_FRAME) || \
|
||||
(XferOptions == I2C_FIRST_AND_LAST_FRAME)))
|
||||
{
|
||||
/* Preload TX register */
|
||||
/* Write data to TXDR */
|
||||
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
|
||||
|
||||
/* Increment Buffer pointer */
|
||||
hi2c->pBuffPtr++;
|
||||
|
||||
sizetoxfer = hi2c->XferSize;
|
||||
hi2c->XferCount--;
|
||||
hi2c->XferSize--;
|
||||
}
|
||||
|
||||
/* If transfer direction not change and there is no request to start another frame,
|
||||
do not generate Restart Condition */
|
||||
/* Mean Previous state is same as current state */
|
||||
@ -3462,8 +3576,8 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
|
||||
hi2c->hdmatx->XferAbortCallback = NULL;
|
||||
|
||||
/* Enable the DMA stream or channel depends on Instance */
|
||||
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR,
|
||||
hi2c->XferSize);
|
||||
dmaxferstatus = HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr,
|
||||
(uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
|
||||
}
|
||||
else
|
||||
{
|
||||
@ -3483,7 +3597,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
|
||||
if (dmaxferstatus == HAL_OK)
|
||||
{
|
||||
/* Send Slave Address and set NBYTES to write */
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
|
||||
if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
|
||||
{
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
|
||||
}
|
||||
else
|
||||
{
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
|
||||
}
|
||||
|
||||
/* Update XferCount value */
|
||||
hi2c->XferCount -= hi2c->XferSize;
|
||||
@ -3522,8 +3643,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint1
|
||||
|
||||
/* Send Slave Address */
|
||||
/* Set NBYTES to write and generate START condition */
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, I2C_AUTOEND_MODE,
|
||||
I2C_GENERATE_START_WRITE);
|
||||
if ((XferOptions == I2C_FIRST_FRAME) || (XferOptions == I2C_FIRST_AND_LAST_FRAME))
|
||||
{
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)sizetoxfer, xfermode, xferrequest);
|
||||
}
|
||||
else
|
||||
{
|
||||
I2C_TransferConfig(hi2c, DevAddress, (uint8_t)hi2c->XferSize, xfermode, xferrequest);
|
||||
}
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
@ -3786,11 +3913,11 @@ HAL_StatusTypeDef HAL_I2C_Master_Seq_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16
|
||||
/* Note : The I2C interrupts must be enabled after unlocking current process
|
||||
to avoid the risk of I2C interrupt handle execution before current
|
||||
process unlock */
|
||||
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
|
||||
/* Enable ERR, TC, STOP, NACK, RXI interrupt */
|
||||
/* possible to enable all of these */
|
||||
/* I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI |
|
||||
I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
|
||||
I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
|
||||
I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
|
||||
}
|
||||
|
||||
return HAL_OK;
|
||||
@ -4494,7 +4621,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevA
|
||||
* the configuration information for the specified I2C.
|
||||
* @retval None
|
||||
*/
|
||||
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
|
||||
void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c) /* Derogation MISRAC2012-Rule-8.13 */
|
||||
{
|
||||
/* Get current IT Flags and IT sources value */
|
||||
uint32_t itflags = READ_REG(hi2c->Instance->ISR);
|
||||
@ -4747,7 +4874,7 @@ __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
|
||||
* the configuration information for the specified I2C.
|
||||
* @retval HAL state
|
||||
*/
|
||||
HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
|
||||
HAL_I2C_StateTypeDef HAL_I2C_GetState(const I2C_HandleTypeDef *hi2c)
|
||||
{
|
||||
/* Return I2C handle state */
|
||||
return hi2c->State;
|
||||
@ -4759,7 +4886,7 @@ HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
|
||||
* the configuration information for I2C module
|
||||
* @retval HAL mode
|
||||
*/
|
||||
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
|
||||
HAL_I2C_ModeTypeDef HAL_I2C_GetMode(const I2C_HandleTypeDef *hi2c)
|
||||
{
|
||||
return hi2c->Mode;
|
||||
}
|
||||
@ -4770,7 +4897,7 @@ HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
|
||||
* the configuration information for the specified I2C.
|
||||
* @retval I2C Error Code
|
||||
*/
|
||||
uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
|
||||
uint32_t HAL_I2C_GetError(const I2C_HandleTypeDef *hi2c)
|
||||
{
|
||||
return hi2c->ErrorCode;
|
||||
}
|
||||
@ -4833,17 +4960,22 @@ static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uin
|
||||
hi2c->XferSize--;
|
||||
hi2c->XferCount--;
|
||||
}
|
||||
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
|
||||
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET))
|
||||
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) == RESET) && \
|
||||
((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TXIS) != RESET) && \
|
||||
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TXI) != RESET)))
|
||||
{
|
||||
/* Write data to TXDR */
|
||||
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
|
||||
if (hi2c->XferCount != 0U)
|
||||
{
|
||||
/* Write data to TXDR */
|
||||
hi2c->Instance->TXDR = *hi2c->pBuffPtr;
|
||||
|
||||
/* Increment Buffer pointer */
|
||||
hi2c->pBuffPtr++;
|
||||
/* Increment Buffer pointer */
|
||||
hi2c->pBuffPtr++;
|
||||
|
||||
hi2c->XferSize--;
|
||||
hi2c->XferCount--;
|
||||
hi2c->XferSize--;
|
||||
hi2c->XferCount--;
|
||||
}
|
||||
}
|
||||
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TCR) != RESET) && \
|
||||
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
|
||||
@ -5030,6 +5162,12 @@ static HAL_StatusTypeDef I2C_Mem_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32
|
||||
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_TC) != RESET) && \
|
||||
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
|
||||
{
|
||||
/* Disable Interrupt related to address step */
|
||||
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
|
||||
|
||||
/* Enable ERR, TC, STOP, NACK and RXI interrupts */
|
||||
I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
|
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
|
||||
{
|
||||
direction = I2C_GENERATE_START_READ;
|
||||
@ -5094,9 +5232,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint
|
||||
/* Call I2C Slave complete process */
|
||||
I2C_ITSlaveCplt(hi2c, tmpITFlags);
|
||||
}
|
||||
|
||||
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
|
||||
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
|
||||
else if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
|
||||
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
|
||||
{
|
||||
/* Check that I2C transfer finished */
|
||||
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
|
||||
@ -5396,6 +5533,9 @@ static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint3
|
||||
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TCR) != RESET) && \
|
||||
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
|
||||
{
|
||||
/* Disable Interrupt related to address step */
|
||||
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
|
||||
|
||||
/* Enable only Error interrupt */
|
||||
I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
|
||||
|
||||
@ -5438,6 +5578,12 @@ static HAL_StatusTypeDef I2C_Mem_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint3
|
||||
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_TC) != RESET) && \
|
||||
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_TCI) != RESET))
|
||||
{
|
||||
/* Disable Interrupt related to address step */
|
||||
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
|
||||
|
||||
/* Enable only Error and NACK interrupt for data transfer */
|
||||
I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
|
||||
|
||||
if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
|
||||
{
|
||||
direction = I2C_GENERATE_START_READ;
|
||||
@ -5515,9 +5661,8 @@ static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uin
|
||||
/* Call I2C Slave complete process */
|
||||
I2C_ITSlaveCplt(hi2c, ITFlags);
|
||||
}
|
||||
|
||||
if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
|
||||
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
|
||||
else if ((I2C_CHECK_FLAG(ITFlags, I2C_FLAG_AF) != RESET) && \
|
||||
(I2C_CHECK_IT_SOURCE(ITSources, I2C_IT_NACKI) != RESET))
|
||||
{
|
||||
/* Check that I2C transfer finished */
|
||||
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
|
||||
@ -6116,6 +6261,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
|
||||
{
|
||||
uint32_t tmpcr1value = READ_REG(hi2c->Instance->CR1);
|
||||
uint32_t tmpITFlags = ITFlags;
|
||||
uint32_t tmpoptions = hi2c->XferOptions;
|
||||
HAL_I2C_StateTypeDef tmpstate = hi2c->State;
|
||||
|
||||
/* Clear STOP Flag */
|
||||
@ -6132,6 +6278,11 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
|
||||
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
|
||||
hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
|
||||
}
|
||||
else if (tmpstate == HAL_I2C_STATE_LISTEN)
|
||||
{
|
||||
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
|
||||
hi2c->PreviousState = I2C_STATE_NONE;
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Do nothing */
|
||||
@ -6198,6 +6349,57 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
|
||||
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
|
||||
}
|
||||
|
||||
if ((I2C_CHECK_FLAG(tmpITFlags, I2C_FLAG_AF) != RESET) && \
|
||||
(I2C_CHECK_IT_SOURCE(tmpcr1value, I2C_IT_NACKI) != RESET))
|
||||
{
|
||||
/* Check that I2C transfer finished */
|
||||
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
|
||||
/* Mean XferCount == 0*/
|
||||
/* So clear Flag NACKF only */
|
||||
if (hi2c->XferCount == 0U)
|
||||
{
|
||||
if ((hi2c->State == HAL_I2C_STATE_LISTEN) && (tmpoptions == I2C_FIRST_AND_LAST_FRAME))
|
||||
/* Same action must be done for (tmpoptions == I2C_LAST_FRAME) which removed for
|
||||
Warning[Pa134]: left and right operands are identical */
|
||||
{
|
||||
/* Call I2C Listen complete process */
|
||||
I2C_ITListenCplt(hi2c, tmpITFlags);
|
||||
}
|
||||
else if ((hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) && (tmpoptions != I2C_NO_OPTION_FRAME))
|
||||
{
|
||||
/* Clear NACK Flag */
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
||||
|
||||
/* Flush TX register */
|
||||
I2C_Flush_TXDR(hi2c);
|
||||
|
||||
/* Last Byte is Transmitted */
|
||||
/* Call I2C Slave Sequential complete process */
|
||||
I2C_ITSlaveSeqCplt(hi2c);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Clear NACK Flag */
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
|
||||
/* Clear NACK Flag */
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
||||
|
||||
/* Set ErrorCode corresponding to a Non-Acknowledge */
|
||||
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
|
||||
|
||||
if ((tmpoptions == I2C_FIRST_FRAME) || (tmpoptions == I2C_NEXT_FRAME))
|
||||
{
|
||||
/* Call the corresponding callback to inform upper layer of End of Transfer */
|
||||
I2C_ITError(hi2c, hi2c->ErrorCode);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
hi2c->Mode = HAL_I2C_MODE_NONE;
|
||||
hi2c->XferISR = NULL;
|
||||
|
||||
@ -6325,6 +6527,7 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
|
||||
static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
|
||||
{
|
||||
HAL_I2C_StateTypeDef tmpstate = hi2c->State;
|
||||
|
||||
uint32_t tmppreviousstate;
|
||||
|
||||
/* Reset handle parameters */
|
||||
@ -6381,6 +6584,7 @@ static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
|
||||
|
||||
/* Abort DMA TX transfer if any */
|
||||
tmppreviousstate = hi2c->PreviousState;
|
||||
|
||||
if ((hi2c->hdmatx != NULL) && ((tmppreviousstate == I2C_STATE_MASTER_BUSY_TX) || \
|
||||
(tmppreviousstate == I2C_STATE_SLAVE_BUSY_TX)))
|
||||
{
|
||||
@ -6555,6 +6759,7 @@ static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief DMA I2C slave transmit process complete callback.
|
||||
* @param hdma DMA handle
|
||||
@ -6583,6 +6788,7 @@ static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief DMA I2C master receive process complete callback.
|
||||
* @param hdma DMA handle
|
||||
@ -6633,6 +6839,7 @@ static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief DMA I2C slave receive process complete callback.
|
||||
* @param hdma DMA handle
|
||||
@ -6661,6 +6868,7 @@ static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief DMA I2C communication error callback.
|
||||
* @param hdma DMA handle
|
||||
@ -6699,6 +6907,7 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma)
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief DMA I2C communication abort callback
|
||||
* (To be called at end of DMA Abort procedure).
|
||||
@ -6723,6 +6932,7 @@ static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
|
||||
I2C_TreatErrorCallback(hi2c);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief This function handles I2C Communication Timeout. It waits
|
||||
* until a flag is no longer in the specified status.
|
||||
@ -6739,6 +6949,12 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin
|
||||
{
|
||||
while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
|
||||
{
|
||||
/* Check if an error is detected */
|
||||
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check for the Timeout */
|
||||
if (Timeout != HAL_MAX_DELAY)
|
||||
{
|
||||
@ -6850,16 +7066,18 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
|
||||
static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout,
|
||||
uint32_t Tickstart)
|
||||
{
|
||||
while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) && (status == HAL_OK))
|
||||
{
|
||||
/* Check if an error is detected */
|
||||
if (I2C_IsErrorOccurred(hi2c, Timeout, Tickstart) != HAL_OK)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check if a STOPF is detected */
|
||||
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
|
||||
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && (status == HAL_OK))
|
||||
{
|
||||
/* Check if an RXNE is pending */
|
||||
/* Store Last receive data if any */
|
||||
@ -6867,19 +7085,14 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
|
||||
{
|
||||
/* Return HAL_OK */
|
||||
/* The Reading of data from RXDR will be done in caller function */
|
||||
return HAL_OK;
|
||||
status = HAL_OK;
|
||||
}
|
||||
else
|
||||
|
||||
/* Check a no-acknowledge have been detected */
|
||||
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
|
||||
{
|
||||
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
|
||||
{
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
||||
hi2c->ErrorCode = HAL_I2C_ERROR_AF;
|
||||
}
|
||||
else
|
||||
{
|
||||
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
||||
}
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
|
||||
hi2c->ErrorCode = HAL_I2C_ERROR_AF;
|
||||
|
||||
/* Clear STOP Flag */
|
||||
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
|
||||
@ -6893,12 +7106,16 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_ERROR;
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
else
|
||||
{
|
||||
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
|
||||
}
|
||||
}
|
||||
|
||||
/* Check for the Timeout */
|
||||
if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U))
|
||||
if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK))
|
||||
{
|
||||
if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET))
|
||||
{
|
||||
@ -6908,11 +7125,11 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c,
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(hi2c);
|
||||
|
||||
return HAL_ERROR;
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
}
|
||||
}
|
||||
return HAL_OK;
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -7095,8 +7312,9 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
|
||||
{
|
||||
uint32_t tmpisr = 0U;
|
||||
|
||||
if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \
|
||||
(hi2c->XferISR == I2C_Slave_ISR_DMA))
|
||||
if ((hi2c->XferISR != I2C_Master_ISR_DMA) && \
|
||||
(hi2c->XferISR != I2C_Slave_ISR_DMA) && \
|
||||
(hi2c->XferISR != I2C_Mem_ISR_DMA))
|
||||
{
|
||||
if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
|
||||
{
|
||||
@ -7104,6 +7322,51 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
|
||||
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
|
||||
}
|
||||
|
||||
if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
|
||||
{
|
||||
/* Enable ERR, TC, STOP, NACK and TXI interrupts */
|
||||
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
|
||||
}
|
||||
|
||||
if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
|
||||
{
|
||||
/* Enable ERR, TC, STOP, NACK and RXI interrupts */
|
||||
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
|
||||
}
|
||||
|
||||
if (InterruptRequest == I2C_XFER_ERROR_IT)
|
||||
{
|
||||
/* Enable ERR and NACK interrupts */
|
||||
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
|
||||
}
|
||||
|
||||
if (InterruptRequest == I2C_XFER_CPLT_IT)
|
||||
{
|
||||
/* Enable STOP interrupts */
|
||||
tmpisr |= I2C_IT_STOPI;
|
||||
}
|
||||
}
|
||||
|
||||
else
|
||||
{
|
||||
if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
|
||||
{
|
||||
/* Enable ERR, STOP, NACK and ADDR interrupts */
|
||||
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
|
||||
}
|
||||
|
||||
if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
|
||||
{
|
||||
/* Enable ERR, TC, STOP, NACK and TXI interrupts */
|
||||
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
|
||||
}
|
||||
|
||||
if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
|
||||
{
|
||||
/* Enable ERR, TC, STOP, NACK and RXI interrupts */
|
||||
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
|
||||
}
|
||||
|
||||
if (InterruptRequest == I2C_XFER_ERROR_IT)
|
||||
{
|
||||
/* Enable ERR and NACK interrupts */
|
||||
@ -7122,38 +7385,6 @@ static void I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
|
||||
tmpisr |= I2C_IT_TCI;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
|
||||
{
|
||||
/* Enable ERR, STOP, NACK, and ADDR interrupts */
|
||||
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
|
||||
}
|
||||
|
||||
if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
|
||||
{
|
||||
/* Enable ERR, TC, STOP, NACK and RXI interrupts */
|
||||
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
|
||||
}
|
||||
|
||||
if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
|
||||
{
|
||||
/* Enable ERR, TC, STOP, NACK and TXI interrupts */
|
||||
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
|
||||
}
|
||||
|
||||
if (InterruptRequest == I2C_XFER_ERROR_IT)
|
||||
{
|
||||
/* Enable ERR and NACK interrupts */
|
||||
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
|
||||
}
|
||||
|
||||
if (InterruptRequest == I2C_XFER_CPLT_IT)
|
||||
{
|
||||
/* Enable STOP interrupts */
|
||||
tmpisr |= I2C_IT_STOPI;
|
||||
}
|
||||
}
|
||||
|
||||
/* Enable interrupts only at the end */
|
||||
/* to avoid the risk of I2C interrupt handle execution before */
|
||||
|
||||
@ -567,6 +567,9 @@ void HAL_PWR_EnterSLEEPMode (uint32_t Regulator, uint8_t SLEEPEntry)
|
||||
assert_param (IS_PWR_REGULATOR (Regulator));
|
||||
assert_param (IS_PWR_SLEEP_ENTRY (SLEEPEntry));
|
||||
|
||||
/* Prevent unused argument(s) compilation warning */
|
||||
UNUSED(Regulator);
|
||||
|
||||
/* Clear SLEEPDEEP bit of Cortex System Control Register */
|
||||
CLEAR_BIT (SCB->SCR, SCB_SCR_SLEEPDEEP_Msk);
|
||||
|
||||
|
||||
@ -2058,8 +2058,11 @@ void HAL_PWREx_PVD_AVD_IRQHandler (void)
|
||||
/* PWR PVD interrupt user callback */
|
||||
HAL_PWR_PVDCallback ();
|
||||
|
||||
/* Clear PWR EXTI D1/CD pending bit */
|
||||
__HAL_PWR_PVD_EXTI_CLEAR_FLAG ();
|
||||
if(__HAL_PWR_GET_FLAG (PWR_FLAG_AVDO) == 0U)
|
||||
{
|
||||
/* Clear PWR EXTI D1/CD pending bit */
|
||||
__HAL_PWR_PVD_EXTI_CLEAR_FLAG ();
|
||||
}
|
||||
}
|
||||
}
|
||||
#if defined (DUAL_CORE)
|
||||
@ -2071,8 +2074,11 @@ void HAL_PWREx_PVD_AVD_IRQHandler (void)
|
||||
/* PWR PVD interrupt user callback */
|
||||
HAL_PWR_PVDCallback ();
|
||||
|
||||
/* Clear PWR EXTI D2 pending bit */
|
||||
__HAL_PWR_PVD_EXTID2_CLEAR_FLAG();
|
||||
if(__HAL_PWR_GET_FLAG (PWR_FLAG_AVDO) == 0U)
|
||||
{
|
||||
/* Clear PWR EXTI D2 pending bit */
|
||||
__HAL_PWR_PVD_EXTID2_CLEAR_FLAG ();
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif /* defined (DUAL_CORE) */
|
||||
@ -2091,8 +2097,11 @@ void HAL_PWREx_PVD_AVD_IRQHandler (void)
|
||||
/* PWR AVD interrupt user callback */
|
||||
HAL_PWREx_AVDCallback ();
|
||||
|
||||
/* Clear PWR EXTI D1/CD pending bit */
|
||||
__HAL_PWR_AVD_EXTI_CLEAR_FLAG ();
|
||||
if(__HAL_PWR_GET_FLAG (PWR_FLAG_PVDO) == 0U)
|
||||
{
|
||||
/* Clear PWR EXTI D1/CD pending bit */
|
||||
__HAL_PWR_AVD_EXTI_CLEAR_FLAG ();
|
||||
}
|
||||
}
|
||||
}
|
||||
#if defined (DUAL_CORE)
|
||||
@ -2104,8 +2113,11 @@ void HAL_PWREx_PVD_AVD_IRQHandler (void)
|
||||
/* PWR AVD interrupt user callback */
|
||||
HAL_PWREx_AVDCallback ();
|
||||
|
||||
/* Clear PWR EXTI D2 pending bit */
|
||||
__HAL_PWR_AVD_EXTID2_CLEAR_FLAG ();
|
||||
if(__HAL_PWR_GET_FLAG (PWR_FLAG_PVDO) == 0U)
|
||||
{
|
||||
/* Clear PWR EXTI D2 pending bit */
|
||||
__HAL_PWR_AVD_EXTID2_CLEAR_FLAG ();
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif /* defined (DUAL_CORE) */
|
||||
|
||||
@ -172,7 +172,7 @@
|
||||
|
||||
[..]
|
||||
Use function HAL_SAI_UnRegisterCallback() to reset a callback to the default
|
||||
weak (surcharged) function.
|
||||
weak function.
|
||||
HAL_SAI_UnRegisterCallback() takes as parameters the HAL peripheral handle,
|
||||
and the callback ID.
|
||||
[..]
|
||||
@ -187,10 +187,10 @@
|
||||
|
||||
[..]
|
||||
By default, after the HAL_SAI_Init and if the state is HAL_SAI_STATE_RESET
|
||||
all callbacks are reset to the corresponding legacy weak (surcharged) functions:
|
||||
all callbacks are reset to the corresponding legacy weak functions:
|
||||
examples HAL_SAI_RxCpltCallback(), HAL_SAI_ErrorCallback().
|
||||
Exception done for MspInit and MspDeInit callbacks that are respectively
|
||||
reset to the legacy weak (surcharged) functions in the HAL_SAI_Init
|
||||
reset to the legacy weak functions in the HAL_SAI_Init
|
||||
and HAL_SAI_DeInit only when these callbacks are null (not registered beforehand).
|
||||
If not, MspInit or MspDeInit are not null, the HAL_SAI_Init and HAL_SAI_DeInit
|
||||
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
|
||||
@ -207,7 +207,7 @@
|
||||
[..]
|
||||
When the compilation define USE_HAL_SAI_REGISTER_CALLBACKS is set to 0 or
|
||||
not defined, the callback registering feature is not available
|
||||
and weak (surcharged) callbacks are used.
|
||||
and weak callbacks are used.
|
||||
|
||||
@endverbatim
|
||||
*/
|
||||
@ -1516,6 +1516,12 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hsai);
|
||||
|
||||
/* Disable SAI peripheral */
|
||||
if (SAI_Disable(hsai) != HAL_OK)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Disable the SAI DMA request */
|
||||
hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
|
||||
|
||||
@ -1547,12 +1553,6 @@ HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)
|
||||
}
|
||||
}
|
||||
|
||||
/* Disable SAI peripheral */
|
||||
if (SAI_Disable(hsai) != HAL_OK)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Flush the fifo */
|
||||
SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
|
||||
|
||||
@ -1578,6 +1578,12 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai)
|
||||
/* Process Locked */
|
||||
__HAL_LOCK(hsai);
|
||||
|
||||
/* Disable SAI peripheral */
|
||||
if (SAI_Disable(hsai) != HAL_OK)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Check SAI DMA is enabled or not */
|
||||
if ((hsai->Instance->CR1 & SAI_xCR1_DMAEN) == SAI_xCR1_DMAEN)
|
||||
{
|
||||
@ -1617,12 +1623,6 @@ HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai)
|
||||
hsai->Instance->IMR = 0;
|
||||
hsai->Instance->CLRFR = 0xFFFFFFFFU;
|
||||
|
||||
/* Disable SAI peripheral */
|
||||
if (SAI_Disable(hsai) != HAL_OK)
|
||||
{
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Flush the fifo */
|
||||
SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
|
||||
|
||||
|
||||
@ -82,15 +82,15 @@
|
||||
and a pointer to the user callback function.
|
||||
|
||||
Use function HAL_SDRAM_UnRegisterCallback() to reset a callback to the default
|
||||
weak (surcharged) function. It allows to reset following callbacks:
|
||||
weak (overridden) function. It allows to reset following callbacks:
|
||||
(+) MspInitCallback : SDRAM MspInit.
|
||||
(+) MspDeInitCallback : SDRAM MspDeInit.
|
||||
This function) takes as parameters the HAL peripheral handle and the Callback ID.
|
||||
|
||||
By default, after the HAL_SDRAM_Init and if the state is HAL_SDRAM_STATE_RESET
|
||||
all callbacks are reset to the corresponding legacy weak (surcharged) functions.
|
||||
all callbacks are reset to the corresponding legacy weak (overridden) functions.
|
||||
Exception done for MspInit and MspDeInit callbacks that are respectively
|
||||
reset to the legacy weak (surcharged) functions in the HAL_SDRAM_Init
|
||||
reset to the legacy weak (overridden) functions in the HAL_SDRAM_Init
|
||||
and HAL_SDRAM_DeInit only when these callbacks are null (not registered beforehand).
|
||||
If not, MspInit or MspDeInit are not null, the HAL_SDRAM_Init and HAL_SDRAM_DeInit
|
||||
keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
|
||||
@ -105,7 +105,7 @@
|
||||
|
||||
When The compilation define USE_HAL_SDRAM_REGISTER_CALLBACKS is set to 0 or
|
||||
not defined, the callback registering feature is not available
|
||||
and weak (surcharged) callbacks are used.
|
||||
and weak (overridden) callbacks are used.
|
||||
|
||||
@endverbatim
|
||||
******************************************************************************
|
||||
@ -793,7 +793,7 @@ HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAd
|
||||
#if (USE_HAL_SDRAM_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief Register a User SDRAM Callback
|
||||
* To be used instead of the weak (surcharged) predefined callback
|
||||
* To be used to override the weak predefined callback
|
||||
* @param hsdram : SDRAM handle
|
||||
* @param CallbackId : ID of the callback to be registered
|
||||
* This parameter can be one of the following values:
|
||||
@ -814,9 +814,6 @@ HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SD
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hsdram);
|
||||
|
||||
state = hsdram->State;
|
||||
if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
|
||||
{
|
||||
@ -859,14 +856,12 @@ HAL_StatusTypeDef HAL_SDRAM_RegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_SD
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hsdram);
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Unregister a User SDRAM Callback
|
||||
* SDRAM Callback is redirected to the weak (surcharged) predefined callback
|
||||
* SDRAM Callback is redirected to the weak predefined callback
|
||||
* @param hsdram : SDRAM handle
|
||||
* @param CallbackId : ID of the callback to be unregistered
|
||||
* This parameter can be one of the following values:
|
||||
@ -882,9 +877,6 @@ HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
HAL_SDRAM_StateTypeDef state;
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(hsdram);
|
||||
|
||||
state = hsdram->State;
|
||||
if ((state == HAL_SDRAM_STATE_READY) || (state == HAL_SDRAM_STATE_WRITE_PROTECTED))
|
||||
{
|
||||
@ -933,14 +925,12 @@ HAL_StatusTypeDef HAL_SDRAM_UnRegisterCallback(SDRAM_HandleTypeDef *hsdram, HAL_
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(hsdram);
|
||||
return status;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Register a User SDRAM Callback for DMA transfers
|
||||
* To be used instead of the weak (surcharged) predefined callback
|
||||
* To be used to override the weak predefined callback
|
||||
* @param hsdram : SDRAM handle
|
||||
* @param CallbackId : ID of the callback to be registered
|
||||
* This parameter can be one of the following values:
|
||||
|
||||
@ -888,7 +888,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
|
||||
uint32_t tmpsmcr;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
||||
assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
|
||||
|
||||
/* Check the TIM channel state */
|
||||
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
|
||||
@ -980,7 +980,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
||||
assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
|
||||
|
||||
switch (Channel)
|
||||
{
|
||||
@ -1059,7 +1059,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
|
||||
uint32_t tmpsmcr;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
||||
assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
|
||||
|
||||
/* Set the TIM channel state */
|
||||
if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
|
||||
@ -1221,7 +1221,7 @@ HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
||||
assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
|
||||
|
||||
switch (Channel)
|
||||
{
|
||||
@ -1557,7 +1557,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel
|
||||
uint32_t tmpsmcr;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
||||
assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
|
||||
|
||||
/* Check the TIM channel state */
|
||||
if (TIM_CHANNEL_STATE_GET(htim, Channel) != HAL_TIM_CHANNEL_STATE_READY)
|
||||
@ -1649,7 +1649,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
||||
assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
|
||||
|
||||
switch (Channel)
|
||||
{
|
||||
@ -1728,7 +1728,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
|
||||
uint32_t tmpsmcr;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
||||
assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
|
||||
|
||||
/* Set the TIM channel state */
|
||||
if (TIM_CHANNEL_STATE_GET(htim, Channel) == HAL_TIM_CHANNEL_STATE_BUSY)
|
||||
@ -1889,7 +1889,7 @@ HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
||||
assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
|
||||
|
||||
switch (Channel)
|
||||
{
|
||||
@ -2133,7 +2133,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
|
||||
HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
||||
assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
|
||||
|
||||
/* Check the TIM channel state */
|
||||
if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
|
||||
@ -2181,7 +2181,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
|
||||
HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
||||
assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
|
||||
|
||||
/* Disable the Input Capture channel */
|
||||
TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
|
||||
@ -2217,7 +2217,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
|
||||
HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
||||
assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
|
||||
|
||||
/* Check the TIM channel state */
|
||||
if ((channel_state != HAL_TIM_CHANNEL_STATE_READY)
|
||||
@ -2305,7 +2305,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
||||
assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
|
||||
|
||||
switch (Channel)
|
||||
{
|
||||
@ -2381,7 +2381,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
|
||||
HAL_TIM_ChannelStateTypeDef complementary_channel_state = TIM_CHANNEL_N_STATE_GET(htim, Channel);
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
||||
assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
|
||||
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
|
||||
|
||||
/* Set the TIM channel state */
|
||||
@ -2536,7 +2536,7 @@ HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
|
||||
assert_param(IS_TIM_CCX_CHANNEL(htim->Instance, Channel));
|
||||
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
|
||||
|
||||
/* Disable the Input Capture channel */
|
||||
@ -3027,7 +3027,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out
|
||||
* @param sConfig TIM Encoder Interface configuration structure
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig)
|
||||
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig)
|
||||
{
|
||||
uint32_t tmpsmcr;
|
||||
uint32_t tmpccmr1;
|
||||
@ -3833,13 +3833,16 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
|
||||
*/
|
||||
void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
||||
{
|
||||
uint32_t itsource = htim->Instance->DIER;
|
||||
uint32_t itflag = htim->Instance->SR;
|
||||
|
||||
/* Capture compare 1 event */
|
||||
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
|
||||
if ((itflag & (TIM_FLAG_CC1)) == (TIM_FLAG_CC1))
|
||||
{
|
||||
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC1) != RESET)
|
||||
if ((itsource & (TIM_IT_CC1)) == (TIM_IT_CC1))
|
||||
{
|
||||
{
|
||||
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
|
||||
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC1);
|
||||
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
|
||||
|
||||
/* Input capture event */
|
||||
@ -3867,11 +3870,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
||||
}
|
||||
}
|
||||
/* Capture compare 2 event */
|
||||
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
|
||||
if ((itflag & (TIM_FLAG_CC2)) == (TIM_FLAG_CC2))
|
||||
{
|
||||
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC2) != RESET)
|
||||
if ((itsource & (TIM_IT_CC2)) == (TIM_IT_CC2))
|
||||
{
|
||||
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
|
||||
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC2);
|
||||
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
|
||||
/* Input capture event */
|
||||
if ((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00U)
|
||||
@ -3897,11 +3900,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
||||
}
|
||||
}
|
||||
/* Capture compare 3 event */
|
||||
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
|
||||
if ((itflag & (TIM_FLAG_CC3)) == (TIM_FLAG_CC3))
|
||||
{
|
||||
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC3) != RESET)
|
||||
if ((itsource & (TIM_IT_CC3)) == (TIM_IT_CC3))
|
||||
{
|
||||
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
|
||||
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC3);
|
||||
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
|
||||
/* Input capture event */
|
||||
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00U)
|
||||
@ -3927,11 +3930,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
||||
}
|
||||
}
|
||||
/* Capture compare 4 event */
|
||||
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
|
||||
if ((itflag & (TIM_FLAG_CC4)) == (TIM_FLAG_CC4))
|
||||
{
|
||||
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_CC4) != RESET)
|
||||
if ((itsource & (TIM_IT_CC4)) == (TIM_IT_CC4))
|
||||
{
|
||||
__HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
|
||||
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_CC4);
|
||||
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
|
||||
/* Input capture event */
|
||||
if ((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00U)
|
||||
@ -3957,11 +3960,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
||||
}
|
||||
}
|
||||
/* TIM Update event */
|
||||
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
|
||||
if ((itflag & (TIM_FLAG_UPDATE)) == (TIM_FLAG_UPDATE))
|
||||
{
|
||||
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) != RESET)
|
||||
if ((itsource & (TIM_IT_UPDATE)) == (TIM_IT_UPDATE))
|
||||
{
|
||||
__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
|
||||
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_UPDATE);
|
||||
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
||||
htim->PeriodElapsedCallback(htim);
|
||||
#else
|
||||
@ -3970,11 +3973,12 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
||||
}
|
||||
}
|
||||
/* TIM Break input event */
|
||||
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK) != RESET)
|
||||
if (((itflag & (TIM_FLAG_BREAK)) == (TIM_FLAG_BREAK)) || \
|
||||
((itflag & (TIM_FLAG_SYSTEM_BREAK)) == (TIM_FLAG_SYSTEM_BREAK)))
|
||||
{
|
||||
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
|
||||
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
|
||||
{
|
||||
__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
|
||||
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK | TIM_FLAG_SYSTEM_BREAK);
|
||||
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
||||
htim->BreakCallback(htim);
|
||||
#else
|
||||
@ -3983,9 +3987,9 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
||||
}
|
||||
}
|
||||
/* TIM Break2 input event */
|
||||
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_BREAK2) != RESET)
|
||||
if ((itflag & (TIM_FLAG_BREAK2)) == (TIM_FLAG_BREAK2))
|
||||
{
|
||||
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) != RESET)
|
||||
if ((itsource & (TIM_IT_BREAK)) == (TIM_IT_BREAK))
|
||||
{
|
||||
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_BREAK2);
|
||||
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
||||
@ -3996,11 +4000,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
||||
}
|
||||
}
|
||||
/* TIM Trigger detection event */
|
||||
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
|
||||
if ((itflag & (TIM_FLAG_TRIGGER)) == (TIM_FLAG_TRIGGER))
|
||||
{
|
||||
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) != RESET)
|
||||
if ((itsource & (TIM_IT_TRIGGER)) == (TIM_IT_TRIGGER))
|
||||
{
|
||||
__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
|
||||
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_TRIGGER);
|
||||
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
||||
htim->TriggerCallback(htim);
|
||||
#else
|
||||
@ -4009,11 +4013,11 @@ void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
|
||||
}
|
||||
}
|
||||
/* TIM commutation event */
|
||||
if (__HAL_TIM_GET_FLAG(htim, TIM_FLAG_COM) != RESET)
|
||||
if ((itflag & (TIM_FLAG_COM)) == (TIM_FLAG_COM))
|
||||
{
|
||||
if (__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) != RESET)
|
||||
if ((itsource & (TIM_IT_COM)) == (TIM_IT_COM))
|
||||
{
|
||||
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
|
||||
__HAL_TIM_CLEAR_FLAG(htim, TIM_FLAG_COM);
|
||||
#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
|
||||
htim->CommutationCallback(htim);
|
||||
#else
|
||||
@ -4565,7 +4569,8 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_O
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress,
|
||||
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength)
|
||||
uint32_t BurstRequestSrc, const uint32_t *BurstBuffer,
|
||||
uint32_t BurstLength)
|
||||
{
|
||||
HAL_StatusTypeDef status;
|
||||
|
||||
@ -6967,6 +6972,13 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure
|
||||
/* Generate an update event to reload the Prescaler
|
||||
and the repetition counter (only for advanced timer) value immediately */
|
||||
TIMx->EGR = TIM_EGR_UG;
|
||||
|
||||
/* Check if the update flag is set after the Update Generation, if so clear the UIF flag */
|
||||
if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE))
|
||||
{
|
||||
/* Clear the update flag */
|
||||
CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
@ -6981,11 +6993,12 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co
|
||||
uint32_t tmpccer;
|
||||
uint32_t tmpcr2;
|
||||
|
||||
/* Get the TIMx CCER register value */
|
||||
tmpccer = TIMx->CCER;
|
||||
|
||||
/* Disable the Channel 1: Reset the CC1E Bit */
|
||||
TIMx->CCER &= ~TIM_CCER_CC1E;
|
||||
|
||||
/* Get the TIMx CCER register value */
|
||||
tmpccer = TIMx->CCER;
|
||||
/* Get the TIMx CR2 register value */
|
||||
tmpcr2 = TIMx->CR2;
|
||||
|
||||
@ -7056,11 +7069,12 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
||||
uint32_t tmpccer;
|
||||
uint32_t tmpcr2;
|
||||
|
||||
/* Get the TIMx CCER register value */
|
||||
tmpccer = TIMx->CCER;
|
||||
|
||||
/* Disable the Channel 2: Reset the CC2E Bit */
|
||||
TIMx->CCER &= ~TIM_CCER_CC2E;
|
||||
|
||||
/* Get the TIMx CCER register value */
|
||||
tmpccer = TIMx->CCER;
|
||||
/* Get the TIMx CR2 register value */
|
||||
tmpcr2 = TIMx->CR2;
|
||||
|
||||
@ -7089,7 +7103,6 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config)
|
||||
tmpccer |= (OC_Config->OCNPolarity << 4U);
|
||||
/* Reset the Output N State */
|
||||
tmpccer &= ~TIM_CCER_CC2NE;
|
||||
|
||||
}
|
||||
|
||||
if (IS_TIM_BREAK_INSTANCE(TIMx))
|
||||
@ -7132,11 +7145,12 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co
|
||||
uint32_t tmpccer;
|
||||
uint32_t tmpcr2;
|
||||
|
||||
/* Get the TIMx CCER register value */
|
||||
tmpccer = TIMx->CCER;
|
||||
|
||||
/* Disable the Channel 3: Reset the CC2E Bit */
|
||||
TIMx->CCER &= ~TIM_CCER_CC3E;
|
||||
|
||||
/* Get the TIMx CCER register value */
|
||||
tmpccer = TIMx->CCER;
|
||||
/* Get the TIMx CR2 register value */
|
||||
tmpcr2 = TIMx->CR2;
|
||||
|
||||
@ -7206,11 +7220,12 @@ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co
|
||||
uint32_t tmpccer;
|
||||
uint32_t tmpcr2;
|
||||
|
||||
/* Get the TIMx CCER register value */
|
||||
tmpccer = TIMx->CCER;
|
||||
|
||||
/* Disable the Channel 4: Reset the CC4E Bit */
|
||||
TIMx->CCER &= ~TIM_CCER_CC4E;
|
||||
|
||||
/* Get the TIMx CCER register value */
|
||||
tmpccer = TIMx->CCER;
|
||||
/* Get the TIMx CR2 register value */
|
||||
tmpcr2 = TIMx->CR2;
|
||||
|
||||
@ -7267,11 +7282,12 @@ static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx,
|
||||
uint32_t tmpccer;
|
||||
uint32_t tmpcr2;
|
||||
|
||||
/* Get the TIMx CCER register value */
|
||||
tmpccer = TIMx->CCER;
|
||||
|
||||
/* Disable the output: Reset the CCxE Bit */
|
||||
TIMx->CCER &= ~TIM_CCER_CC5E;
|
||||
|
||||
/* Get the TIMx CCER register value */
|
||||
tmpccer = TIMx->CCER;
|
||||
/* Get the TIMx CR2 register value */
|
||||
tmpcr2 = TIMx->CR2;
|
||||
/* Get the TIMx CCMR1 register value */
|
||||
@ -7320,11 +7336,12 @@ static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx,
|
||||
uint32_t tmpccer;
|
||||
uint32_t tmpcr2;
|
||||
|
||||
/* Get the TIMx CCER register value */
|
||||
tmpccer = TIMx->CCER;
|
||||
|
||||
/* Disable the output: Reset the CCxE Bit */
|
||||
TIMx->CCER &= ~TIM_CCER_CC6E;
|
||||
|
||||
/* Get the TIMx CCER register value */
|
||||
tmpccer = TIMx->CCER;
|
||||
/* Get the TIMx CR2 register value */
|
||||
tmpcr2 = TIMx->CR2;
|
||||
/* Get the TIMx CCMR1 register value */
|
||||
@ -7518,9 +7535,9 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_
|
||||
uint32_t tmpccer;
|
||||
|
||||
/* Disable the Channel 1: Reset the CC1E Bit */
|
||||
tmpccer = TIMx->CCER;
|
||||
TIMx->CCER &= ~TIM_CCER_CC1E;
|
||||
tmpccmr1 = TIMx->CCMR1;
|
||||
tmpccer = TIMx->CCER;
|
||||
|
||||
/* Select the Input */
|
||||
if (IS_TIM_CC2_INSTANCE(TIMx) != RESET)
|
||||
@ -7608,9 +7625,9 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
|
||||
uint32_t tmpccer;
|
||||
|
||||
/* Disable the Channel 2: Reset the CC2E Bit */
|
||||
tmpccer = TIMx->CCER;
|
||||
TIMx->CCER &= ~TIM_CCER_CC2E;
|
||||
tmpccmr1 = TIMx->CCMR1;
|
||||
tmpccer = TIMx->CCER;
|
||||
|
||||
/* Select the Input */
|
||||
tmpccmr1 &= ~TIM_CCMR1_CC2S;
|
||||
@ -7647,9 +7664,9 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity,
|
||||
uint32_t tmpccer;
|
||||
|
||||
/* Disable the Channel 2: Reset the CC2E Bit */
|
||||
tmpccer = TIMx->CCER;
|
||||
TIMx->CCER &= ~TIM_CCER_CC2E;
|
||||
tmpccmr1 = TIMx->CCMR1;
|
||||
tmpccer = TIMx->CCER;
|
||||
|
||||
/* Set the filter */
|
||||
tmpccmr1 &= ~TIM_CCMR1_IC2F;
|
||||
@ -7691,9 +7708,9 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
|
||||
uint32_t tmpccer;
|
||||
|
||||
/* Disable the Channel 3: Reset the CC3E Bit */
|
||||
tmpccer = TIMx->CCER;
|
||||
TIMx->CCER &= ~TIM_CCER_CC3E;
|
||||
tmpccmr2 = TIMx->CCMR2;
|
||||
tmpccer = TIMx->CCER;
|
||||
|
||||
/* Select the Input */
|
||||
tmpccmr2 &= ~TIM_CCMR2_CC3S;
|
||||
@ -7739,9 +7756,9 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32
|
||||
uint32_t tmpccer;
|
||||
|
||||
/* Disable the Channel 4: Reset the CC4E Bit */
|
||||
tmpccer = TIMx->CCER;
|
||||
TIMx->CCER &= ~TIM_CCER_CC4E;
|
||||
tmpccmr2 = TIMx->CCMR2;
|
||||
tmpccer = TIMx->CCER;
|
||||
|
||||
/* Select the Input */
|
||||
tmpccmr2 &= ~TIM_CCMR2_CC4S;
|
||||
|
||||
@ -849,7 +849,7 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channe
|
||||
|
||||
/* Disable the TIM Break interrupt (only if no more channel is active) */
|
||||
tmpccer = htim->Instance->CCER;
|
||||
if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
|
||||
if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
|
||||
{
|
||||
__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
|
||||
}
|
||||
@ -1095,17 +1095,6 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Chann
|
||||
(+) Stop the Complementary PWM and disable interrupts.
|
||||
(+) Start the Complementary PWM and enable DMA transfers.
|
||||
(+) Stop the Complementary PWM and disable DMA transfers.
|
||||
(+) Start the Complementary Input Capture measurement.
|
||||
(+) Stop the Complementary Input Capture.
|
||||
(+) Start the Complementary Input Capture and enable interrupts.
|
||||
(+) Stop the Complementary Input Capture and disable interrupts.
|
||||
(+) Start the Complementary Input Capture and enable DMA transfers.
|
||||
(+) Stop the Complementary Input Capture and disable DMA transfers.
|
||||
(+) Start the Complementary One Pulse generation.
|
||||
(+) Stop the Complementary One Pulse.
|
||||
(+) Start the Complementary One Pulse and enable interrupts.
|
||||
(+) Stop the Complementary One Pulse and disable interrupts.
|
||||
|
||||
@endverbatim
|
||||
* @{
|
||||
*/
|
||||
@ -1331,7 +1320,7 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Chann
|
||||
|
||||
/* Disable the TIM Break interrupt (only if no more channel is active) */
|
||||
tmpccer = htim->Instance->CCER;
|
||||
if ((tmpccer & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == (uint32_t)RESET)
|
||||
if ((tmpccer & TIM_CCER_CCxNE_MASK) == (uint32_t)RESET)
|
||||
{
|
||||
__HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
|
||||
}
|
||||
@ -1812,6 +1801,9 @@ HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t
|
||||
* @arg TIM_TS_ITR12: Internal trigger 12 selected (*)
|
||||
* @arg TIM_TS_ITR13: Internal trigger 13 selected (*)
|
||||
* @arg TIM_TS_NONE: No trigger is needed
|
||||
*
|
||||
* (*) Value not defined in all devices.
|
||||
*
|
||||
* @param CommutationSource the Commutation Event source
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
|
||||
@ -1868,9 +1860,12 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent(TIM_HandleTypeDef *htim, uint32_t
|
||||
* @arg TIM_TS_ITR1: Internal trigger 1 selected
|
||||
* @arg TIM_TS_ITR2: Internal trigger 2 selected
|
||||
* @arg TIM_TS_ITR3: Internal trigger 3 selected
|
||||
* @arg TIM_TS_ITR2: Internal trigger 12 selected (*)
|
||||
* @arg TIM_TS_ITR3: Internal trigger 13 selected (*)
|
||||
* @arg TIM_TS_ITR12: Internal trigger 12 selected (*)
|
||||
* @arg TIM_TS_ITR13: Internal trigger 13 selected (*)
|
||||
* @arg TIM_TS_NONE: No trigger is needed
|
||||
*
|
||||
* (*) Value not defined in all devices.
|
||||
*
|
||||
* @param CommutationSource the Commutation Event source
|
||||
* This parameter can be one of the following values:
|
||||
* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
|
||||
@ -1928,8 +1923,8 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigCommutEvent_IT(TIM_HandleTypeDef *htim, uint32
|
||||
* @arg TIM_TS_ITR1: Internal trigger 1 selected
|
||||
* @arg TIM_TS_ITR2: Internal trigger 2 selected
|
||||
* @arg TIM_TS_ITR3: Internal trigger 3 selected
|
||||
* @arg TIM_TS_ITR2: Internal trigger 12 selected (*)
|
||||
* @arg TIM_TS_ITR3: Internal trigger 13 selected (*)
|
||||
* @arg TIM_TS_ITR12: Internal trigger 12 selected (*)
|
||||
* @arg TIM_TS_ITR13: Internal trigger 13 selected (*)
|
||||
* @arg TIM_TS_NONE: No trigger is needed
|
||||
*
|
||||
* (*) Value not defined in all devices.
|
||||
@ -2079,6 +2074,9 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
|
||||
assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
|
||||
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->BreakFilter));
|
||||
assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
|
||||
#if defined(TIM_BDTR_BKBID)
|
||||
assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
|
||||
#endif /* TIM_BDTR_BKBID */
|
||||
|
||||
/* Check input state */
|
||||
__HAL_LOCK(htim);
|
||||
@ -2095,39 +2093,26 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
|
||||
MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, sBreakDeadTimeConfig->BreakPolarity);
|
||||
MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, sBreakDeadTimeConfig->AutomaticOutput);
|
||||
MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, (sBreakDeadTimeConfig->BreakFilter << TIM_BDTR_BKF_Pos));
|
||||
|
||||
#if defined(TIM_BDTR_BKBID)
|
||||
if (IS_TIM_ADVANCED_INSTANCE(htim->Instance))
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_BREAK_AFMODE(sBreakDeadTimeConfig->BreakAFMode));
|
||||
|
||||
/* Set BREAK AF mode */
|
||||
MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
|
||||
}
|
||||
|
||||
MODIFY_REG(tmpbdtr, TIM_BDTR_BKBID, sBreakDeadTimeConfig->BreakAFMode);
|
||||
#endif /* TIM_BDTR_BKBID */
|
||||
|
||||
if (IS_TIM_BKIN2_INSTANCE(htim->Instance))
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_BREAK2_STATE(sBreakDeadTimeConfig->Break2State));
|
||||
assert_param(IS_TIM_BREAK2_POLARITY(sBreakDeadTimeConfig->Break2Polarity));
|
||||
assert_param(IS_TIM_BREAK_FILTER(sBreakDeadTimeConfig->Break2Filter));
|
||||
#if defined(TIM_BDTR_BKBID)
|
||||
assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
|
||||
#endif /* TIM_BDTR_BKBID */
|
||||
|
||||
/* Set the BREAK2 input related BDTR bits */
|
||||
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (sBreakDeadTimeConfig->Break2Filter << TIM_BDTR_BK2F_Pos));
|
||||
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, sBreakDeadTimeConfig->Break2State);
|
||||
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, sBreakDeadTimeConfig->Break2Polarity);
|
||||
#if defined(TIM_BDTR_BKBID)
|
||||
|
||||
if (IS_TIM_ADVANCED_INSTANCE(htim->Instance))
|
||||
{
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_BREAK2_AFMODE(sBreakDeadTimeConfig->Break2AFMode));
|
||||
|
||||
/* Set BREAK2 AF mode */
|
||||
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
|
||||
}
|
||||
MODIFY_REG(tmpbdtr, TIM_BDTR_BK2BID, sBreakDeadTimeConfig->Break2AFMode);
|
||||
#endif /* TIM_BDTR_BKBID */
|
||||
}
|
||||
|
||||
@ -2153,7 +2138,6 @@ HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
|
||||
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
|
||||
uint32_t BreakInput,
|
||||
const TIMEx_BreakInputConfigTypeDef *sBreakInputConfig)
|
||||
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint32_t tmporx;
|
||||
@ -2381,49 +2365,49 @@ HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
|
||||
* @arg TIM_TIM5_TI1_CAN_RTP: TIM5 TI1 is connected to CAN RTP
|
||||
*
|
||||
* For TIM8, the parameter is one of the following values:
|
||||
* @arg TIM_TIM8_TI1_GPIO: TIM8 TI1 is connected to GPIO
|
||||
* @arg TIM_TIM8_TI1_COMP2: TIM8 TI1 is connected to COMP2 output
|
||||
* @arg TIM_TIM8_TI1_GPIO: TIM8 TI1 is connected to GPIO
|
||||
* @arg TIM_TIM8_TI1_COMP2: TIM8 TI1 is connected to COMP2 output
|
||||
*
|
||||
* For TIM12, the parameter can have the following values: (*)
|
||||
* @arg TIM_TIM12_TI1_GPIO: TIM12 TI1 is connected to GPIO
|
||||
* @arg TIM_TIM12_TI1_SPDIF_FS: TIM12 TI1 is connected to SPDIF FS
|
||||
* @arg TIM_TIM12_TI1_GPIO: TIM12 TI1 is connected to GPIO
|
||||
* @arg TIM_TIM12_TI1_SPDIF_FS: TIM12 TI1 is connected to SPDIF FS
|
||||
*
|
||||
* For TIM15, the parameter is one of the following values:
|
||||
* @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO
|
||||
* @arg TIM_TIM15_TI1_TIM2: TIM15 TI1 is connected to TIM2 CH1
|
||||
* @arg TIM_TIM15_TI1_TIM3: TIM15 TI1 is connected to TIM3 CH1
|
||||
* @arg TIM_TIM15_TI1_TIM4: TIM15 TI1 is connected to TIM4 CH1
|
||||
* @arg TIM_TIM15_TI1_LSE: TIM15 TI1 is connected to LSE
|
||||
* @arg TIM_TIM15_TI1_CSI: TIM15 TI1 is connected to CSI
|
||||
* @arg TIM_TIM15_TI1_MCO2: TIM15 TI1 is connected to MCO2
|
||||
* @arg TIM_TIM15_TI2_GPIO: TIM15 TI2 is connected to GPIO
|
||||
* @arg TIM_TIM15_TI2_TIM2: TIM15 TI2 is connected to TIM2 CH2
|
||||
* @arg TIM_TIM15_TI2_TIM3: TIM15 TI2 is connected to TIM3 CH2
|
||||
* @arg TIM_TIM15_TI2_TIM4: TIM15 TI2 is connected to TIM4 CH2
|
||||
* @arg TIM_TIM15_TI1_GPIO: TIM15 TI1 is connected to GPIO
|
||||
* @arg TIM_TIM15_TI1_TIM2_CH1: TIM15 TI1 is connected to TIM2 CH1
|
||||
* @arg TIM_TIM15_TI1_TIM3_CH1: TIM15 TI1 is connected to TIM3 CH1
|
||||
* @arg TIM_TIM15_TI1_TIM4_CH1: TIM15 TI1 is connected to TIM4 CH1
|
||||
* @arg TIM_TIM15_TI1_RCC_LSE: TIM15 TI1 is connected to LSE
|
||||
* @arg TIM_TIM15_TI1_RCC_CSI: TIM15 TI1 is connected to CSI
|
||||
* @arg TIM_TIM15_TI1_RCC_MCO2: TIM15 TI1 is connected to MCO2
|
||||
* @arg TIM_TIM15_TI2_GPIO: TIM15 TI2 is connected to GPIO
|
||||
* @arg TIM_TIM15_TI2_TIM2_CH2: TIM15 TI2 is connected to TIM2 CH2
|
||||
* @arg TIM_TIM15_TI2_TIM3_CH2: TIM15 TI2 is connected to TIM3 CH2
|
||||
* @arg TIM_TIM15_TI2_TIM4_CH2: TIM15 TI2 is connected to TIM4 CH2
|
||||
*
|
||||
* For TIM16, the parameter can have the following values:
|
||||
* @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO
|
||||
* @arg TIM_TIM16_TI1_LSI: TIM16 TI1 is connected to LSI
|
||||
* @arg TIM_TIM16_TI1_LSE: TIM16 TI1 is connected to LSE
|
||||
* @arg TIM_TIM16_TI1_RTC: TIM16 TI1 is connected to RTC wakeup interrupt
|
||||
* @arg TIM_TIM16_TI1_GPIO: TIM16 TI1 is connected to GPIO
|
||||
* @arg TIM_TIM16_TI1_RCC_LSI: TIM16 TI1 is connected to LSI
|
||||
* @arg TIM_TIM16_TI1_RCC_LSE: TIM16 TI1 is connected to LSE
|
||||
* @arg TIM_TIM16_TI1_WKUP_IT: TIM16 TI1 is connected to RTC wakeup interrupt
|
||||
*
|
||||
* For TIM17, the parameter can have the following values:
|
||||
* @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO
|
||||
* @arg TIM_TIM17_TI1_SPDIF_FS: TIM17 TI1 is connected to SPDIF FS (*)
|
||||
* @arg TIM_TIM17_TI1_HSE_1MHZ: TIM17 TI1 is connected to HSE 1MHz
|
||||
* @arg TIM_TIM17_TI1_MCO1: TIM17 TI1 is connected to MCO1
|
||||
* @arg TIM_TIM17_TI1_GPIO: TIM17 TI1 is connected to GPIO
|
||||
* @arg TIM_TIM17_TI1_SPDIF_FS: TIM17 TI1 is connected to SPDIF FS (*)
|
||||
* @arg TIM_TIM17_TI1_RCC_HSE1MHZ: TIM17 TI1 is connected to HSE 1MHz
|
||||
* @arg TIM_TIM17_TI1_RCC_MCO1: TIM17 TI1 is connected to MCO1
|
||||
*
|
||||
* For TIM23, the parameter can have the following values: (*)
|
||||
* @arg TIM_TIM23_TI4_GPIO TIM23_TI4 is connected to GPIO
|
||||
* @arg TIM_TIM23_TI4_COMP1 TIM23_TI4 is connected to COMP1 output
|
||||
* @arg TIM_TIM23_TI4_COMP2 TIM23_TI4 is connected to COMP2 output
|
||||
* @arg TIM_TIM23_TI4_COMP1_COMP2 TIM23_TI4 is connected to COMP2 output
|
||||
* @arg TIM_TIM23_TI4_GPIO TIM23_TI4 is connected to GPIO
|
||||
* @arg TIM_TIM23_TI4_COMP1 TIM23_TI4 is connected to COMP1 output
|
||||
* @arg TIM_TIM23_TI4_COMP2 TIM23_TI4 is connected to COMP2 output
|
||||
* @arg TIM_TIM23_TI4_COMP1_COMP2 TIM23_TI4 is connected to COMP2 output
|
||||
*
|
||||
* For TIM24, the parameter can have the following values: (*)
|
||||
* @arg TIM_TIM24_TI1_GPIO TIM24_TI1 is connected to GPIO
|
||||
* @arg TIM_TIM24_TI1_CAN_TMP TIM24_TI1 is connected to CAN_TMP
|
||||
* @arg TIM_TIM24_TI1_CAN_RTP TIM24_TI1 is connected to CAN_RTP
|
||||
* @arg TIM_TIM24_TI1_CAN_SOC TIM24_TI1 is connected to CAN_SOC
|
||||
* @arg TIM_TIM24_TI1_GPIO TIM24_TI1 is connected to GPIO
|
||||
* @arg TIM_TIM24_TI1_CAN_TMP TIM24_TI1 is connected to CAN_TMP
|
||||
* @arg TIM_TIM24_TI1_CAN_RTP TIM24_TI1 is connected to CAN_RTP
|
||||
* @arg TIM_TIM24_TI1_CAN_SOC TIM24_TI1 is connected to CAN_SOC
|
||||
*
|
||||
* (*) Value not defined in all devices. \n
|
||||
* @retval HAL status
|
||||
@ -2518,7 +2502,7 @@ HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t B
|
||||
uint32_t tmpbdtr;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
|
||||
assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
|
||||
assert_param(IS_TIM_BREAKINPUT(BreakInput));
|
||||
|
||||
switch (BreakInput)
|
||||
@ -2535,7 +2519,6 @@ HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t B
|
||||
}
|
||||
break;
|
||||
}
|
||||
|
||||
case TIM_BREAKINPUT_BRK2:
|
||||
{
|
||||
/* Check initial conditions */
|
||||
@ -2567,13 +2550,13 @@ HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t B
|
||||
* @note Break input is automatically armed as soon as MOE bit is set.
|
||||
* @retval HAL status
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput)
|
||||
HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
uint32_t tickstart;
|
||||
|
||||
/* Check the parameters */
|
||||
assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
|
||||
assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
|
||||
assert_param(IS_TIM_BREAKINPUT(BreakInput));
|
||||
|
||||
switch (BreakInput)
|
||||
@ -2653,7 +2636,7 @@ HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t Br
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Hall commutation changed callback in non-blocking mode
|
||||
* @brief Commutation callback in non-blocking mode
|
||||
* @param htim TIM handle
|
||||
* @retval None
|
||||
*/
|
||||
@ -2667,7 +2650,7 @@ __weak void HAL_TIMEx_CommutCallback(TIM_HandleTypeDef *htim)
|
||||
*/
|
||||
}
|
||||
/**
|
||||
* @brief Hall commutation changed half complete callback in non-blocking mode
|
||||
* @brief Commutation half complete callback in non-blocking mode
|
||||
* @param htim TIM handle
|
||||
* @retval None
|
||||
*/
|
||||
@ -2682,7 +2665,7 @@ __weak void HAL_TIMEx_CommutHalfCpltCallback(TIM_HandleTypeDef *htim)
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Hall Break detection callback in non-blocking mode
|
||||
* @brief Break detection callback in non-blocking mode
|
||||
* @param htim TIM handle
|
||||
* @retval None
|
||||
*/
|
||||
@ -2697,7 +2680,7 @@ __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Hall Break2 detection callback in non blocking mode
|
||||
* @brief Break2 detection callback in non blocking mode
|
||||
* @param htim: TIM handle
|
||||
* @retval None
|
||||
*/
|
||||
@ -2848,15 +2831,6 @@ static void TIM_DMADelayPulseNCplt(DMA_HandleTypeDef *hdma)
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_3, HAL_TIM_CHANNEL_STATE_READY);
|
||||
}
|
||||
}
|
||||
else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
|
||||
{
|
||||
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
|
||||
|
||||
if (hdma->Init.Mode == DMA_NORMAL)
|
||||
{
|
||||
TIM_CHANNEL_N_STATE_SET(htim, TIM_CHANNEL_4, HAL_TIM_CHANNEL_STATE_READY);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* nothing to do */
|
||||
@ -2925,13 +2899,13 @@ static void TIM_CCxNChannelCmd(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Cha
|
||||
{
|
||||
uint32_t tmp;
|
||||
|
||||
tmp = TIM_CCER_CC1NE << (Channel & 0x1FU); /* 0x1FU = 31 bits max shift */
|
||||
tmp = TIM_CCER_CC1NE << (Channel & 0xFU); /* 0xFU = 15 bits max shift */
|
||||
|
||||
/* Reset the CCxNE Bit */
|
||||
TIMx->CCER &= ~tmp;
|
||||
|
||||
/* Set or reset the CCxNE Bit */
|
||||
TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0x1FU)); /* 0x1FU = 31 bits max shift */
|
||||
TIMx->CCER |= (uint32_t)(ChannelNState << (Channel & 0xFU)); /* 0xFU = 15 bits max shift */
|
||||
}
|
||||
/**
|
||||
* @}
|
||||
|
||||
@ -107,7 +107,7 @@
|
||||
|
||||
[..]
|
||||
Use function HAL_UART_UnRegisterCallback() to reset a callback to the default
|
||||
weak (surcharged) function.
|
||||
weak function.
|
||||
HAL_UART_UnRegisterCallback() takes as parameters the HAL peripheral handle,
|
||||
and the Callback ID.
|
||||
This function allows to reset following callbacks:
|
||||
@ -131,10 +131,10 @@
|
||||
|
||||
[..]
|
||||
By default, after the HAL_UART_Init() and when the state is HAL_UART_STATE_RESET
|
||||
all callbacks are set to the corresponding weak (surcharged) functions:
|
||||
all callbacks are set to the corresponding weak functions:
|
||||
examples HAL_UART_TxCpltCallback(), HAL_UART_RxHalfCpltCallback().
|
||||
Exception done for MspInit and MspDeInit functions that are respectively
|
||||
reset to the legacy weak (surcharged) functions in the HAL_UART_Init()
|
||||
reset to the legacy weak functions in the HAL_UART_Init()
|
||||
and HAL_UART_DeInit() only when these callbacks are null (not registered beforehand).
|
||||
If not, MspInit or MspDeInit are not null, the HAL_UART_Init() and HAL_UART_DeInit()
|
||||
keep and use the user MspInit/MspDeInit callbacks (registered beforehand).
|
||||
@ -151,7 +151,7 @@
|
||||
[..]
|
||||
When The compilation define USE_HAL_UART_REGISTER_CALLBACKS is set to 0 or
|
||||
not defined, the callback registration feature is not available
|
||||
and weak (surcharged) callbacks are used.
|
||||
and weak callbacks are used.
|
||||
|
||||
|
||||
@endverbatim
|
||||
@ -197,8 +197,8 @@
|
||||
/** @addtogroup UART_Private_Functions
|
||||
* @{
|
||||
*/
|
||||
static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
|
||||
static void UART_EndRxTransfer(UART_HandleTypeDef *huart);
|
||||
static void UART_EndTxTransfer(UART_HandleTypeDef *huart);
|
||||
static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
|
||||
static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
|
||||
static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
|
||||
@ -348,17 +348,19 @@ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
|
||||
|
||||
__HAL_UART_DISABLE(huart);
|
||||
|
||||
/* Perform advanced settings configuration */
|
||||
/* For some items, configuration requires to be done prior TE and RE bits are set */
|
||||
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
||||
{
|
||||
UART_AdvFeatureConfig(huart);
|
||||
}
|
||||
|
||||
/* Set the UART Communication parameters */
|
||||
if (UART_SetConfig(huart) == HAL_ERROR)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
||||
{
|
||||
UART_AdvFeatureConfig(huart);
|
||||
}
|
||||
|
||||
/* In asynchronous mode, the following bits must be kept cleared:
|
||||
- LINEN and CLKEN bits in the USART_CR2 register,
|
||||
- SCEN, HDSEL and IREN bits in the USART_CR3 register.*/
|
||||
@ -413,17 +415,19 @@ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
|
||||
|
||||
__HAL_UART_DISABLE(huart);
|
||||
|
||||
/* Perform advanced settings configuration */
|
||||
/* For some items, configuration requires to be done prior TE and RE bits are set */
|
||||
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
||||
{
|
||||
UART_AdvFeatureConfig(huart);
|
||||
}
|
||||
|
||||
/* Set the UART Communication parameters */
|
||||
if (UART_SetConfig(huart) == HAL_ERROR)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
||||
{
|
||||
UART_AdvFeatureConfig(huart);
|
||||
}
|
||||
|
||||
/* In half-duplex mode, the following bits must be kept cleared:
|
||||
- LINEN and CLKEN bits in the USART_CR2 register,
|
||||
- SCEN and IREN bits in the USART_CR3 register.*/
|
||||
@ -499,17 +503,19 @@ HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLe
|
||||
|
||||
__HAL_UART_DISABLE(huart);
|
||||
|
||||
/* Perform advanced settings configuration */
|
||||
/* For some items, configuration requires to be done prior TE and RE bits are set */
|
||||
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
||||
{
|
||||
UART_AdvFeatureConfig(huart);
|
||||
}
|
||||
|
||||
/* Set the UART Communication parameters */
|
||||
if (UART_SetConfig(huart) == HAL_ERROR)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
||||
{
|
||||
UART_AdvFeatureConfig(huart);
|
||||
}
|
||||
|
||||
/* In LIN mode, the following bits must be kept cleared:
|
||||
- LINEN and CLKEN bits in the USART_CR2 register,
|
||||
- SCEN and IREN bits in the USART_CR3 register.*/
|
||||
@ -583,17 +589,19 @@ HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Add
|
||||
|
||||
__HAL_UART_DISABLE(huart);
|
||||
|
||||
/* Perform advanced settings configuration */
|
||||
/* For some items, configuration requires to be done prior TE and RE bits are set */
|
||||
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
||||
{
|
||||
UART_AdvFeatureConfig(huart);
|
||||
}
|
||||
|
||||
/* Set the UART Communication parameters */
|
||||
if (UART_SetConfig(huart) == HAL_ERROR)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
||||
{
|
||||
UART_AdvFeatureConfig(huart);
|
||||
}
|
||||
|
||||
/* In multiprocessor mode, the following bits must be kept cleared:
|
||||
- LINEN and CLKEN bits in the USART_CR2 register,
|
||||
- SCEN, HDSEL and IREN bits in the USART_CR3 register. */
|
||||
@ -696,7 +704,7 @@ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
|
||||
#if (USE_HAL_UART_REGISTER_CALLBACKS == 1)
|
||||
/**
|
||||
* @brief Register a User UART Callback
|
||||
* To be used instead of the weak predefined callback
|
||||
* To be used to override the weak predefined callback
|
||||
* @note The HAL_UART_RegisterCallback() may be called before HAL_UART_Init(), HAL_HalfDuplex_Init(),
|
||||
* HAL_LIN_Init(), HAL_MultiProcessor_Init() or HAL_RS485Ex_Init() in HAL_UART_STATE_RESET to register
|
||||
* callbacks for HAL_UART_MSPINIT_CB_ID and HAL_UART_MSPDEINIT_CB_ID
|
||||
@ -963,10 +971,7 @@ HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pU
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(huart);
|
||||
|
||||
if (huart->gState == HAL_UART_STATE_READY)
|
||||
if (huart->RxState == HAL_UART_STATE_READY)
|
||||
{
|
||||
huart->RxEventCallback = pCallback;
|
||||
}
|
||||
@ -977,9 +982,6 @@ HAL_StatusTypeDef HAL_UART_RegisterRxEventCallback(UART_HandleTypeDef *huart, pU
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(huart);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
@ -993,10 +995,7 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart)
|
||||
{
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Process locked */
|
||||
__HAL_LOCK(huart);
|
||||
|
||||
if (huart->gState == HAL_UART_STATE_READY)
|
||||
if (huart->RxState == HAL_UART_STATE_READY)
|
||||
{
|
||||
huart->RxEventCallback = HAL_UARTEx_RxEventCallback; /* Legacy weak UART Rx Event Callback */
|
||||
}
|
||||
@ -1007,8 +1006,6 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart)
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
/* Release Lock */
|
||||
__HAL_UNLOCK(huart);
|
||||
return status;
|
||||
}
|
||||
|
||||
@ -3273,6 +3270,13 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
|
||||
/* Check whether the set of advanced features to configure is properly set */
|
||||
assert_param(IS_UART_ADVFEATURE_INIT(huart->AdvancedInit.AdvFeatureInit));
|
||||
|
||||
/* if required, configure RX/TX pins swap */
|
||||
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
|
||||
{
|
||||
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
|
||||
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
|
||||
}
|
||||
|
||||
/* if required, configure TX pin active level inversion */
|
||||
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_TXINVERT_INIT))
|
||||
{
|
||||
@ -3294,13 +3298,6 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart)
|
||||
MODIFY_REG(huart->Instance->CR2, USART_CR2_DATAINV, huart->AdvancedInit.DataInvert);
|
||||
}
|
||||
|
||||
/* if required, configure RX/TX pins swap */
|
||||
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_SWAP_INIT))
|
||||
{
|
||||
assert_param(IS_UART_ADVFEATURE_SWAP(huart->AdvancedInit.Swap));
|
||||
MODIFY_REG(huart->Instance->CR2, USART_CR2_SWAP, huart->AdvancedInit.Swap);
|
||||
}
|
||||
|
||||
/* if required, configure RX overrun detection disabling */
|
||||
if (HAL_IS_BIT_SET(huart->AdvancedInit.AdvFeatureInit, UART_ADVFEATURE_RXOVERRUNDISABLE_INIT))
|
||||
{
|
||||
@ -3426,24 +3423,24 @@ HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_
|
||||
return HAL_TIMEOUT;
|
||||
}
|
||||
|
||||
if (READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U)
|
||||
if ((READ_BIT(huart->Instance->CR1, USART_CR1_RE) != 0U) && (Flag != UART_FLAG_TXE) && (Flag != UART_FLAG_TC))
|
||||
{
|
||||
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_ORE) == SET)
|
||||
{
|
||||
/* Clear Overrun Error flag*/
|
||||
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
|
||||
/* Clear Overrun Error flag*/
|
||||
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF);
|
||||
|
||||
/* Blocking error : transfer is aborted
|
||||
Set the UART state ready to be able to start again the process,
|
||||
Disable Rx Interrupts if ongoing */
|
||||
UART_EndRxTransfer(huart);
|
||||
/* Blocking error : transfer is aborted
|
||||
Set the UART state ready to be able to start again the process,
|
||||
Disable Rx Interrupts if ongoing */
|
||||
UART_EndRxTransfer(huart);
|
||||
|
||||
huart->ErrorCode = HAL_UART_ERROR_ORE;
|
||||
huart->ErrorCode = HAL_UART_ERROR_ORE;
|
||||
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(huart);
|
||||
/* Process Unlocked */
|
||||
__HAL_UNLOCK(huart);
|
||||
|
||||
return HAL_ERROR;
|
||||
return HAL_ERROR;
|
||||
}
|
||||
if (__HAL_UART_GET_FLAG(huart, UART_FLAG_RTOF) == SET)
|
||||
{
|
||||
|
||||
@ -211,17 +211,19 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity,
|
||||
/* Disable the Peripheral */
|
||||
__HAL_UART_DISABLE(huart);
|
||||
|
||||
/* Perform advanced settings configuration */
|
||||
/* For some items, configuration requires to be done prior TE and RE bits are set */
|
||||
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
||||
{
|
||||
UART_AdvFeatureConfig(huart);
|
||||
}
|
||||
|
||||
/* Set the UART Communication parameters */
|
||||
if (UART_SetConfig(huart) == HAL_ERROR)
|
||||
{
|
||||
return HAL_ERROR;
|
||||
}
|
||||
|
||||
if (huart->AdvancedInit.AdvFeatureInit != UART_ADVFEATURE_NO_INIT)
|
||||
{
|
||||
UART_AdvFeatureConfig(huart);
|
||||
}
|
||||
|
||||
/* Enable the Driver Enable mode by setting the DEM bit in the CR3 register */
|
||||
SET_BIT(huart->Instance->CR3, USART_CR3_DEM);
|
||||
|
||||
@ -833,7 +835,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *p
|
||||
*/
|
||||
HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
|
||||
{
|
||||
HAL_StatusTypeDef status;
|
||||
HAL_StatusTypeDef status = HAL_OK;
|
||||
|
||||
/* Check that a Rx process is not already ongoing */
|
||||
if (huart->RxState == HAL_UART_STATE_READY)
|
||||
@ -847,24 +849,20 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t
|
||||
huart->ReceptionType = HAL_UART_RECEPTION_TOIDLE;
|
||||
huart->RxEventType = HAL_UART_RXEVENT_TC;
|
||||
|
||||
status = UART_Start_Receive_IT(huart, pData, Size);
|
||||
(void)UART_Start_Receive_IT(huart, pData, Size);
|
||||
|
||||
/* Check Rx process has been successfully started */
|
||||
if (status == HAL_OK)
|
||||
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
||||
{
|
||||
if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE)
|
||||
{
|
||||
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
||||
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* In case of errors already pending when reception is started,
|
||||
Interrupts may have already been raised and lead to reception abortion.
|
||||
(Overrun error for instance).
|
||||
In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
__HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_IDLEF);
|
||||
ATOMIC_SET_BIT(huart->Instance->CR1, USART_CR1_IDLEIE);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* In case of errors already pending when reception is started,
|
||||
Interrupts may have already been raised and lead to reception abortion.
|
||||
(Overrun error for instance).
|
||||
In such case Reception Type has been reset to HAL_UART_RECEPTION_STANDARD. */
|
||||
status = HAL_ERROR;
|
||||
}
|
||||
|
||||
return status;
|
||||
@ -960,7 +958,7 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_
|
||||
* @param huart UART handle.
|
||||
* @retval Rx Event Type (return vale will be a value of @ref UART_RxEvent_Type_Values)
|
||||
*/
|
||||
HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart)
|
||||
HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart)
|
||||
{
|
||||
/* Return Rx Event type value, as stored in UART handle */
|
||||
return (huart->RxEventType);
|
||||
|
||||
@ -60,7 +60,8 @@
|
||||
/** @addtogroup STM32H7xx_HAL_Driver
|
||||
* @{
|
||||
*/
|
||||
#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_SRAM_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)
|
||||
#if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) || defined(HAL_SDRAM_MODULE_ENABLED)\
|
||||
|| defined(HAL_SRAM_MODULE_ENABLED)
|
||||
|
||||
/** @defgroup FMC_LL FMC Low Layer
|
||||
* @brief FMC driver modules
|
||||
@ -1043,7 +1044,7 @@ HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device,
|
||||
* FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
|
||||
* FMC_SDRAM_POWER_DOWN_MODE.
|
||||
*/
|
||||
uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
|
||||
uint32_t FMC_SDRAM_GetModeStatus(const FMC_SDRAM_TypeDef *Device, uint32_t Bank)
|
||||
{
|
||||
uint32_t tmpreg;
|
||||
|
||||
|
||||
10
Middlewares/CMakeLists.txt
Normal file
10
Middlewares/CMakeLists.txt
Normal file
@ -0,0 +1,10 @@
|
||||
cmake_minimum_required(VERSION 3.22)
|
||||
|
||||
project(middlewares)
|
||||
|
||||
add_subdirectory(Third_Party/freertos)
|
||||
add_subdirectory(Third_Party/easylogger)
|
||||
add_subdirectory(Third_Party/fatfs)
|
||||
add_subdirectory(Third_Party/lvgl)
|
||||
add_subdirectory(Third_Party/minimp3)
|
||||
add_subdirectory(Third_Party/tlsf)
|
||||
135
Middlewares/Third_Party/CMakeLists.txt
vendored
135
Middlewares/Third_Party/CMakeLists.txt
vendored
@ -1,135 +0,0 @@
|
||||
# tlsf
|
||||
set(TLSF_SOURCES
|
||||
"${CMAKE_CURRENT_LIST_DIR}/tlsf/tlsf.c"
|
||||
)
|
||||
|
||||
add_library(tlsf ${TLSF_SOURCES})
|
||||
|
||||
target_include_directories(tlsf PUBLIC
|
||||
"${CMAKE_CURRENT_LIST_DIR}/tlsf"
|
||||
)
|
||||
|
||||
target_compile_options(tlsf PRIVATE
|
||||
${TARGET_BUILD_ARCH_OPTIONS}
|
||||
${TARGET_BUILD_DEFINATIONS}
|
||||
)
|
||||
|
||||
target_link_options(tlsf PRIVATE
|
||||
${TARGET_BUILD_ARCH_OPTIONS}
|
||||
)
|
||||
|
||||
|
||||
# minimp3
|
||||
add_library(minimp3 INTERFACE)
|
||||
|
||||
target_include_directories(minimp3 INTERFACE
|
||||
"${CMAKE_CURRENT_LIST_DIR}/minimp3"
|
||||
)
|
||||
|
||||
|
||||
# lvgl
|
||||
set(LVGL_SOURCE_DIRS
|
||||
"${CMAKE_CURRENT_LIST_DIR}/lvgl/src/core/*.c"
|
||||
"${CMAKE_CURRENT_LIST_DIR}/lvgl/src/draw/*.c"
|
||||
"${CMAKE_CURRENT_LIST_DIR}/lvgl/src/extra/*.c"
|
||||
"${CMAKE_CURRENT_LIST_DIR}/lvgl/src/font/*.c"
|
||||
"${CMAKE_CURRENT_LIST_DIR}/lvgl/src/hal/*.c"
|
||||
"${CMAKE_CURRENT_LIST_DIR}/lvgl/src/misc/*.c"
|
||||
"${CMAKE_CURRENT_LIST_DIR}/lvgl/src/widgets/*.c"
|
||||
"${CMAKE_CURRENT_LIST_DIR}/lvgl/demos/*.c"
|
||||
)
|
||||
file(GLOB_RECURSE LVGL_SOURCES ${LVGL_SOURCE_DIRS})
|
||||
|
||||
#add_library(lvgl ${LVGL_SOURCES})
|
||||
|
||||
#target_include_directories(lvgl PUBLIC
|
||||
# "${CMAKE_CURRENT_LIST_DIR}/lvgl"
|
||||
# "${CMAKE_CURRENT_LIST_DIR}/lvgl/demos"
|
||||
# "${CMAKE_SOURCE_DIR}/User/ports/lvgl"
|
||||
#)
|
||||
|
||||
#target_compile_options(lvgl PRIVATE
|
||||
# ${TARGET_BUILD_ARCH_OPTIONS}
|
||||
# ${TARGET_BUILD_DEFINATIONS}
|
||||
#)
|
||||
|
||||
#target_link_options(lvgl PRIVATE
|
||||
# ${TARGET_BUILD_ARCH_OPTIONS}
|
||||
#)
|
||||
|
||||
|
||||
# FreeRTOS
|
||||
set(FREERTOS_SOURCE_DIRS
|
||||
"FreeRTOS/Source/*.c"
|
||||
)
|
||||
file(GLOB_RECURSE FREERTOS_SOURCES ${FREERTOS_SOURCE_DIRS})
|
||||
|
||||
add_library(freertos ${FREERTOS_SOURCES})
|
||||
|
||||
target_include_directories(freertos PUBLIC
|
||||
"${CMAKE_CURRENT_LIST_DIR}/FreeRTOS/Source/CMSIS_RTOS"
|
||||
"${CMAKE_CURRENT_LIST_DIR}/FreeRTOS/Source/include"
|
||||
"${CMAKE_CURRENT_LIST_DIR}/FreeRTOS/Source/portable/GCC/ARM_CM4F"
|
||||
)
|
||||
|
||||
target_compile_options(freertos PRIVATE
|
||||
${TARGET_BUILD_ARCH_OPTIONS}
|
||||
${TARGET_BUILD_DEFINATIONS}
|
||||
)
|
||||
|
||||
target_link_options(freertos PRIVATE
|
||||
${TARGET_BUILD_ARCH_OPTIONS}
|
||||
)
|
||||
|
||||
|
||||
# easylogger
|
||||
set(EASYLOGGER_SOURCES
|
||||
"${CMAKE_CURRENT_LIST_DIR}/EasyLogger/src/elog_async.c"
|
||||
"${CMAKE_CURRENT_LIST_DIR}/EasyLogger/src/elog_buf.c"
|
||||
"${CMAKE_CURRENT_LIST_DIR}/EasyLogger/src/elog_utils.c"
|
||||
"${CMAKE_CURRENT_LIST_DIR}/EasyLogger/src/elog.c"
|
||||
)
|
||||
|
||||
add_library(easylogger ${EASYLOGGER_SOURCES})
|
||||
|
||||
target_include_directories(easylogger PUBLIC
|
||||
"${CMAKE_CURRENT_LIST_DIR}/EasyLogger/inc"
|
||||
"${CMAKE_SOURCE_DIR}/User/ports/EasyLogger"
|
||||
)
|
||||
|
||||
target_compile_options(easylogger PRIVATE
|
||||
${TARGET_BUILD_ARCH_OPTIONS}
|
||||
${TARGET_BUILD_DEFINATIONS}
|
||||
)
|
||||
|
||||
target_link_options(easylogger PRIVATE
|
||||
${TARGET_BUILD_ARCH_OPTIONS}
|
||||
)
|
||||
|
||||
|
||||
# fatfs
|
||||
set(FATFS_SOURCES
|
||||
"${CMAKE_CURRENT_LIST_DIR}/FatFs/ff.c"
|
||||
"${CMAKE_CURRENT_LIST_DIR}/FatFs/ffsystem.c"
|
||||
"${CMAKE_CURRENT_LIST_DIR}/FatFs/ffunicode.c"
|
||||
)
|
||||
|
||||
add_library(fatfs ${FATFS_SOURCES})
|
||||
|
||||
target_include_directories(fatfs PUBLIC
|
||||
"${CMAKE_CURRENT_LIST_DIR}/FatFs"
|
||||
"${CMAKE_SOURCE_DIR}/User/ports/Fatfs"
|
||||
)
|
||||
|
||||
target_link_libraries(fatfs PRIVATE
|
||||
freertos
|
||||
)
|
||||
|
||||
target_compile_options(fatfs PRIVATE
|
||||
${TARGET_BUILD_ARCH_OPTIONS}
|
||||
${TARGET_BUILD_DEFINATIONS}
|
||||
)
|
||||
|
||||
target_link_options(fatfs PRIVATE
|
||||
${TARGET_BUILD_ARCH_OPTIONS}
|
||||
)
|
||||
20
Middlewares/Third_Party/EasyLogger/CMakeLists.txt
vendored
Normal file
20
Middlewares/Third_Party/EasyLogger/CMakeLists.txt
vendored
Normal file
@ -0,0 +1,20 @@
|
||||
cmake_minimum_required(VERSION 3.22)
|
||||
|
||||
set(EASYLOGGER_SOURCES
|
||||
"${CMAKE_CURRENT_LIST_DIR}/src/elog_async.c"
|
||||
"${CMAKE_CURRENT_LIST_DIR}/src/elog_buf.c"
|
||||
"${CMAKE_CURRENT_LIST_DIR}/src/elog_utils.c"
|
||||
"${CMAKE_CURRENT_LIST_DIR}/src/elog.c"
|
||||
"${CMAKE_CURRENT_LIST_DIR}/port/elog_port.c"
|
||||
)
|
||||
|
||||
add_library(easylogger ${EASYLOGGER_SOURCES})
|
||||
|
||||
target_include_directories(easylogger PUBLIC
|
||||
"${CMAKE_CURRENT_LIST_DIR}/inc"
|
||||
)
|
||||
|
||||
target_link_libraries(easylogger PRIVATE
|
||||
hal_driver
|
||||
freertos
|
||||
)
|
||||
31
Middlewares/Third_Party/EasyLogger/inc/elog.h
vendored
31
Middlewares/Third_Party/EasyLogger/inc/elog.h
vendored
@ -81,45 +81,64 @@ extern "C" {
|
||||
#define elog_debug(tag, ...)
|
||||
#define elog_verbose(tag, ...)
|
||||
#else /* ELOG_OUTPUT_ENABLE */
|
||||
|
||||
#ifdef ELOG_FMT_USING_FUNC
|
||||
#define ELOG_OUTPUT_FUNC __FUNCTION__
|
||||
#else
|
||||
#define ELOG_OUTPUT_FUNC NULL
|
||||
#endif
|
||||
|
||||
#ifdef ELOG_FMT_USING_DIR
|
||||
#define ELOG_OUTPUT_DIR __FILE__
|
||||
#else
|
||||
#define ELOG_OUTPUT_DIR NULL
|
||||
#endif
|
||||
|
||||
#ifdef ELOG_FMT_USING_LINE
|
||||
#define ELOG_OUTPUT_LINE __LINE__
|
||||
#else
|
||||
#define ELOG_OUTPUT_LINE 0
|
||||
#endif
|
||||
|
||||
#define elog_raw(...) elog_raw_output(__VA_ARGS__)
|
||||
#if ELOG_OUTPUT_LVL >= ELOG_LVL_ASSERT
|
||||
#define elog_assert(tag, ...) \
|
||||
elog_output(ELOG_LVL_ASSERT, tag, __FILE__, __FUNCTION__, __LINE__, __VA_ARGS__)
|
||||
elog_output(ELOG_LVL_ASSERT, tag, ELOG_OUTPUT_DIR, ELOG_OUTPUT_FUNC, ELOG_OUTPUT_LINE, __VA_ARGS__)
|
||||
#else
|
||||
#define elog_assert(tag, ...)
|
||||
#endif /* ELOG_OUTPUT_LVL >= ELOG_LVL_ASSERT */
|
||||
|
||||
#if ELOG_OUTPUT_LVL >= ELOG_LVL_ERROR
|
||||
#define elog_error(tag, ...) \
|
||||
elog_output(ELOG_LVL_ERROR, tag, __FILE__, __FUNCTION__, __LINE__, __VA_ARGS__)
|
||||
elog_output(ELOG_LVL_ERROR, tag, ELOG_OUTPUT_DIR, ELOG_OUTPUT_FUNC, ELOG_OUTPUT_LINE, __VA_ARGS__)
|
||||
#else
|
||||
#define elog_error(tag, ...)
|
||||
#endif /* ELOG_OUTPUT_LVL >= ELOG_LVL_ERROR */
|
||||
|
||||
#if ELOG_OUTPUT_LVL >= ELOG_LVL_WARN
|
||||
#define elog_warn(tag, ...) \
|
||||
elog_output(ELOG_LVL_WARN, tag, __FILE__, __FUNCTION__, __LINE__, __VA_ARGS__)
|
||||
elog_output(ELOG_LVL_WARN, tag, ELOG_OUTPUT_DIR, ELOG_OUTPUT_FUNC, ELOG_OUTPUT_LINE, __VA_ARGS__)
|
||||
#else
|
||||
#define elog_warn(tag, ...)
|
||||
#endif /* ELOG_OUTPUT_LVL >= ELOG_LVL_WARN */
|
||||
|
||||
#if ELOG_OUTPUT_LVL >= ELOG_LVL_INFO
|
||||
#define elog_info(tag, ...) \
|
||||
elog_output(ELOG_LVL_INFO, tag, __FILE__, __FUNCTION__, __LINE__, __VA_ARGS__)
|
||||
elog_output(ELOG_LVL_INFO, tag, ELOG_OUTPUT_DIR, ELOG_OUTPUT_FUNC, ELOG_OUTPUT_LINE, __VA_ARGS__)
|
||||
#else
|
||||
#define elog_info(tag, ...)
|
||||
#endif /* ELOG_OUTPUT_LVL >= ELOG_LVL_INFO */
|
||||
|
||||
#if ELOG_OUTPUT_LVL >= ELOG_LVL_DEBUG
|
||||
#define elog_debug(tag, ...) \
|
||||
elog_output(ELOG_LVL_DEBUG, tag, __FILE__, __FUNCTION__, __LINE__, __VA_ARGS__)
|
||||
elog_output(ELOG_LVL_DEBUG, tag, ELOG_OUTPUT_DIR, ELOG_OUTPUT_FUNC, ELOG_OUTPUT_LINE, __VA_ARGS__)
|
||||
#else
|
||||
#define elog_debug(tag, ...)
|
||||
#endif /* ELOG_OUTPUT_LVL >= ELOG_LVL_DEBUG */
|
||||
|
||||
#if ELOG_OUTPUT_LVL == ELOG_LVL_VERBOSE
|
||||
#define elog_verbose(tag, ...) \
|
||||
elog_output(ELOG_LVL_VERBOSE, tag, __FILE__, __FUNCTION__, __LINE__, __VA_ARGS__)
|
||||
elog_output(ELOG_LVL_VERBOSE, tag, ELOG_OUTPUT_DIR, ELOG_OUTPUT_FUNC, ELOG_OUTPUT_LINE, __VA_ARGS__)
|
||||
#else
|
||||
#define elog_verbose(tag, ...)
|
||||
#endif /* ELOG_OUTPUT_LVL == ELOG_LVL_VERBOSE */
|
||||
|
||||
37
Middlewares/Third_Party/EasyLogger/src/elog.c
vendored
37
Middlewares/Third_Party/EasyLogger/src/elog.c
vendored
@ -141,6 +141,8 @@ static const char *color_output_info[] = {
|
||||
#endif /* ELOG_COLOR_ENABLE */
|
||||
|
||||
static bool get_fmt_enabled(uint8_t level, size_t set);
|
||||
static bool get_fmt_used_and_enabled_u32(uint8_t level, size_t set, uint32_t arg);
|
||||
static bool get_fmt_used_and_enabled_ptr(uint8_t level, size_t set, const char* arg);
|
||||
static void elog_set_filter_tag_lvl_default(void);
|
||||
|
||||
/* EasyLogger assert hook */
|
||||
@ -211,7 +213,7 @@ void elog_deinit(void) {
|
||||
if (!elog.init_ok) {
|
||||
return ;
|
||||
}
|
||||
|
||||
|
||||
#ifdef ELOG_ASYNC_OUTPUT_ENABLE
|
||||
elog_async_deinit();
|
||||
#endif
|
||||
@ -230,7 +232,7 @@ void elog_start(void) {
|
||||
if (!elog.init_ok) {
|
||||
return ;
|
||||
}
|
||||
|
||||
|
||||
/* enable output */
|
||||
elog_set_output_enabled(true);
|
||||
|
||||
@ -241,7 +243,7 @@ void elog_start(void) {
|
||||
#endif
|
||||
|
||||
/* show version */
|
||||
log_i("EasyLogger V%s is successfully initialized.", ELOG_SW_VERSION);
|
||||
log_i("EasyLogger V%s is initialize success.", ELOG_SW_VERSION);
|
||||
}
|
||||
|
||||
/**
|
||||
@ -280,7 +282,7 @@ void elog_set_output_enabled(bool enabled) {
|
||||
#ifdef ELOG_COLOR_ENABLE
|
||||
/**
|
||||
* set log text color enable or disable
|
||||
*
|
||||
*
|
||||
* @param enabled TRUE: enable FALSE:disable
|
||||
*/
|
||||
void elog_set_text_color_enabled(bool enabled) {
|
||||
@ -365,7 +367,7 @@ void elog_set_filter_kw(const char *keyword) {
|
||||
}
|
||||
|
||||
/**
|
||||
* lock output
|
||||
* lock output
|
||||
*/
|
||||
void elog_output_lock(void) {
|
||||
if (elog.output_lock_enabled) {
|
||||
@ -632,29 +634,31 @@ void elog_output(uint8_t level, const char *tag, const char *file, const char *f
|
||||
log_len += elog_strcpy(log_len, log_buf + log_len, "] ");
|
||||
}
|
||||
/* package file directory and name, function name and line number info */
|
||||
if (get_fmt_enabled(level, ELOG_FMT_DIR | ELOG_FMT_FUNC | ELOG_FMT_LINE)) {
|
||||
if (get_fmt_used_and_enabled_ptr(level, ELOG_FMT_DIR, file) ||
|
||||
get_fmt_used_and_enabled_ptr(level, ELOG_FMT_FUNC, func) ||
|
||||
get_fmt_used_and_enabled_u32(level, ELOG_FMT_LINE, line)) {
|
||||
log_len += elog_strcpy(log_len, log_buf + log_len, "(");
|
||||
/* package file info */
|
||||
if (get_fmt_enabled(level, ELOG_FMT_DIR)) {
|
||||
if (get_fmt_used_and_enabled_ptr(level, ELOG_FMT_DIR, file)) {
|
||||
log_len += elog_strcpy(log_len, log_buf + log_len, file);
|
||||
if (get_fmt_enabled(level, ELOG_FMT_FUNC)) {
|
||||
if (get_fmt_used_and_enabled_ptr(level, ELOG_FMT_FUNC, func)) {
|
||||
log_len += elog_strcpy(log_len, log_buf + log_len, ":");
|
||||
} else if (get_fmt_enabled(level, ELOG_FMT_LINE)) {
|
||||
} else if (get_fmt_used_and_enabled_u32(level, ELOG_FMT_LINE, line)) {
|
||||
log_len += elog_strcpy(log_len, log_buf + log_len, " ");
|
||||
}
|
||||
}
|
||||
/* package line info */
|
||||
if (get_fmt_enabled(level, ELOG_FMT_LINE)) {
|
||||
if (get_fmt_used_and_enabled_u32(level, ELOG_FMT_LINE, line)) {
|
||||
snprintf(line_num, ELOG_LINE_NUM_MAX_LEN, "%ld", line);
|
||||
log_len += elog_strcpy(log_len, log_buf + log_len, line_num);
|
||||
if (get_fmt_enabled(level, ELOG_FMT_FUNC)) {
|
||||
if (get_fmt_used_and_enabled_ptr(level, ELOG_FMT_FUNC, func)) {
|
||||
log_len += elog_strcpy(log_len, log_buf + log_len, " ");
|
||||
}
|
||||
}
|
||||
/* package func info */
|
||||
if (get_fmt_enabled(level, ELOG_FMT_FUNC)) {
|
||||
if (get_fmt_used_and_enabled_ptr(level, ELOG_FMT_FUNC, func)) {
|
||||
log_len += elog_strcpy(log_len, log_buf + log_len, func);
|
||||
|
||||
|
||||
}
|
||||
log_len += elog_strcpy(log_len, log_buf + log_len, ")");
|
||||
}
|
||||
@ -737,6 +741,13 @@ static bool get_fmt_enabled(uint8_t level, size_t set) {
|
||||
}
|
||||
}
|
||||
|
||||
static bool get_fmt_used_and_enabled_u32(uint8_t level, size_t set, uint32_t arg) {
|
||||
return arg && get_fmt_enabled(level, set);
|
||||
}
|
||||
static bool get_fmt_used_and_enabled_ptr(uint8_t level, size_t set, const char* arg) {
|
||||
return arg && get_fmt_enabled(level, set);
|
||||
}
|
||||
|
||||
/**
|
||||
* enable or disable logger output lock
|
||||
* @note disable this lock is not recommended except you want output system exception log
|
||||
|
||||
@ -87,7 +87,7 @@ static bool thread_running = false;
|
||||
/* asynchronous output mode enabled flag */
|
||||
static bool is_enabled = false;
|
||||
/* asynchronous output mode's ring buffer */
|
||||
static char __attribute__((section(".ram_ahb"))) log_buf[OUTPUT_BUF_SIZE] = { 0 };
|
||||
static char log_buf[OUTPUT_BUF_SIZE] = { 0 };
|
||||
/* log ring buffer write index */
|
||||
static size_t write_index = 0;
|
||||
/* log ring buffer read index */
|
||||
@ -376,7 +376,7 @@ void elog_async_deinit(void) {
|
||||
elog_async_output_notice();
|
||||
|
||||
pthread_join(async_output_thread, NULL);
|
||||
|
||||
|
||||
sem_destroy(&output_notice);
|
||||
#endif
|
||||
|
||||
|
||||
14
Middlewares/Third_Party/FatFs/CMakeLists.txt
vendored
Normal file
14
Middlewares/Third_Party/FatFs/CMakeLists.txt
vendored
Normal file
@ -0,0 +1,14 @@
|
||||
cmake_minimum_required(VERSION 3.22)
|
||||
|
||||
file(GLOB_RECURSE FATFS_SOURCES "${CMAKE_CURRENT_LIST_DIR}/*.c")
|
||||
|
||||
add_library(fatfs ${FATFS_SOURCES})
|
||||
|
||||
target_include_directories(fatfs PUBLIC
|
||||
"${CMAKE_CURRENT_LIST_DIR}"
|
||||
)
|
||||
|
||||
target_link_libraries(fatfs PRIVATE
|
||||
hal_driver
|
||||
freertos
|
||||
)
|
||||
11
Middlewares/Third_Party/FreeRTOS/CMakeLists.txt
vendored
Normal file
11
Middlewares/Third_Party/FreeRTOS/CMakeLists.txt
vendored
Normal file
@ -0,0 +1,11 @@
|
||||
cmake_minimum_required(VERSION 3.22)
|
||||
|
||||
file(GLOB_RECURSE FREERTOS_SOURCES "${CMAKE_CURRENT_LIST_DIR}/Source/*.c")
|
||||
|
||||
add_library(freertos ${FREERTOS_SOURCES})
|
||||
|
||||
target_include_directories(freertos PUBLIC
|
||||
"${CMAKE_CURRENT_LIST_DIR}/Source/CMSIS_RTOS"
|
||||
"${CMAKE_CURRENT_LIST_DIR}/Source/include"
|
||||
"${CMAKE_CURRENT_LIST_DIR}/Source/portable/GCC/ARM_CM4F"
|
||||
)
|
||||
9
Middlewares/Third_Party/minimp3/CMakeLists.txt
vendored
Normal file
9
Middlewares/Third_Party/minimp3/CMakeLists.txt
vendored
Normal file
@ -0,0 +1,9 @@
|
||||
cmake_minimum_required(VERSION 3.22)
|
||||
|
||||
add_library(minimp3 INTERFACE)
|
||||
|
||||
enable_language(C)
|
||||
|
||||
target_include_directories(minimp3 INTERFACE
|
||||
"${CMAKE_CURRENT_LIST_DIR}"
|
||||
)
|
||||
9
Middlewares/Third_Party/tlsf/CMakeLists.txt
vendored
Normal file
9
Middlewares/Third_Party/tlsf/CMakeLists.txt
vendored
Normal file
@ -0,0 +1,9 @@
|
||||
cmake_minimum_required(VERSION 3.22)
|
||||
|
||||
file(GLOB_RECURSE TLSF_SOURCES "${CMAKE_CURRENT_LIST_DIR}/*.c")
|
||||
|
||||
add_library(tlsf ${TLSF_SOURCES})
|
||||
|
||||
target_include_directories(tlsf PUBLIC
|
||||
"${CMAKE_CURRENT_LIST_DIR}"
|
||||
)
|
||||
@ -37,7 +37,7 @@ ENTRY(Reset_Handler)
|
||||
/* Highest address of the user mode stack */
|
||||
_estack = ORIGIN(DTCMRAM) + LENGTH(DTCMRAM); /* end of RAM */
|
||||
/* Generate a link error if heap and stack don't fit into RAM */
|
||||
_Min_Heap_Size = 0x1000; /* required amount of heap */
|
||||
_Min_Heap_Size = 0x0; /* required amount of heap */
|
||||
_Min_Stack_Size = 0x800; /* required amount of stack */
|
||||
|
||||
/* Specify the memory areas */
|
||||
|
||||
@ -10,8 +10,8 @@
|
||||
#define BSP_OLED_WRITE_CMD 0x00
|
||||
|
||||
static const char *TAG = "bsp_oled";
|
||||
static const uint8_t OLED_FONT6x8[][6];
|
||||
static const uint8_t OLED_FONT8x16[][16];
|
||||
static const uint8_t OLED_FONT6x8[94][6];
|
||||
static const uint8_t OLED_FONT8x16[94][16];
|
||||
static const uint8_t OLED_INIT_REGS[23];
|
||||
|
||||
static SemaphoreHandle_t bsp_oled_i2c_tx_semphr = NULL;
|
||||
@ -338,7 +338,7 @@ HAL_StatusTypeDef bsp_oled_update(void)
|
||||
* @brief 6*8的点阵字库
|
||||
*
|
||||
*/
|
||||
static const uint8_t OLED_FONT6x8[][6] = {
|
||||
static const uint8_t OLED_FONT6x8[94][6] = {
|
||||
{0x00, 0x00, 0x00, 0x00, 0x00, 0x00}, // ' '
|
||||
{0x00, 0x00, 0x00, 0x2f, 0x00, 0x00}, // !
|
||||
{0x00, 0x00, 0x07, 0x00, 0x07, 0x00}, // "
|
||||
@ -439,7 +439,7 @@ static const uint8_t OLED_FONT6x8[][6] = {
|
||||
* @brief 8*16的点阵字库
|
||||
*
|
||||
*/
|
||||
static const uint8_t OLED_FONT8x16[][16] = {
|
||||
static const uint8_t OLED_FONT8x16[94][16] = {
|
||||
{0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // ' '
|
||||
{0x00,0x00,0x00,0xF8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x33,0x30,0x00,0x00,0x00}, // !
|
||||
{0x00,0x10,0x0C,0x06,0x10,0x0C,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00}, // "
|
||||
|
||||
@ -60,7 +60,7 @@
|
||||
#endif
|
||||
|
||||
#else /*LV_MEM_CUSTOM*/
|
||||
#define LV_MEM_CUSTOM_INCLUDE "../../User/ports/tlsf/heap.h" /*Header for the dynamic memory function*/
|
||||
#define LV_MEM_CUSTOM_INCLUDE "heap.h" /*Header for the dynamic memory function*/
|
||||
#define LV_MEM_CUSTOM_ALLOC malloc_dtcm
|
||||
#define LV_MEM_CUSTOM_FREE free_dtcm
|
||||
#define LV_MEM_CUSTOM_REALLOC realloc_dtcm
|
||||
|
||||
@ -1,6 +1,7 @@
|
||||
#include "heap.h"
|
||||
#include "FreeRTOS.h"
|
||||
#include "task.h"
|
||||
#include "main.h"
|
||||
#include "tlsf.h"
|
||||
#include "elog.h"
|
||||
#include <sys/lock.h>
|
||||
@ -2,9 +2,9 @@
|
||||
#define __HEAP_H
|
||||
|
||||
#include <stdlib.h>
|
||||
#include "main.h"
|
||||
#include <stdint.h>
|
||||
|
||||
#define HEAP_DTCM_SIZE_KB 112 //保留16k用于系统栈、Newlib堆与静态内存
|
||||
#define HEAP_DTCM_SIZE_KB 96 //保留32k用于系统栈、Newlib堆与静态内存
|
||||
#define HEAP_AXI_SIZE_KB 512 //全部用于堆
|
||||
#define HEAP_APB_SIZE_KB 256 //保留32k用于elog异步输出缓冲区
|
||||
|
||||
@ -242,8 +242,8 @@ Mcu.PinsNb=108
|
||||
Mcu.ThirdPartyNb=0
|
||||
Mcu.UserConstants=
|
||||
Mcu.UserName=STM32H743IITx
|
||||
MxCube.Version=6.10.0
|
||||
MxDb.Version=DB.6.0.100
|
||||
MxCube.Version=6.11.0
|
||||
MxDb.Version=DB.6.0.110
|
||||
NVIC.BusFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
|
||||
NVIC.DMA1_Stream0_IRQn=true\:6\:0\:true\:false\:true\:true\:false\:true\:true
|
||||
NVIC.DMA2_Stream0_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
|
||||
@ -634,10 +634,10 @@ ProjectManager.CustomerFirmwarePackage=
|
||||
ProjectManager.DefaultFWLocation=true
|
||||
ProjectManager.DeletePrevious=true
|
||||
ProjectManager.DeviceId=STM32H743IITx
|
||||
ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.11.1
|
||||
ProjectManager.FirmwarePackage=STM32Cube FW_H7 V1.11.2
|
||||
ProjectManager.FreePins=false
|
||||
ProjectManager.HalAssertFull=false
|
||||
ProjectManager.HeapSize=0x1000
|
||||
ProjectManager.HeapSize=0x0
|
||||
ProjectManager.KeepUserCode=true
|
||||
ProjectManager.LastFirmware=true
|
||||
ProjectManager.LibraryCopy=1
|
||||
|
||||
Loading…
Reference in New Issue
Block a user